1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef TEGRA210_EMC_H 7 #define TEGRA210_EMC_H 8 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/clk/tegra.h> 12 #include <linux/io.h> 13 #include <linux/platform_device.h> 14 15 #define DVFS_FGCG_HIGH_SPEED_THRESHOLD 1000 16 #define IOBRICK_DCC_THRESHOLD 2400 17 #define DVFS_FGCG_MID_SPEED_THRESHOLD 600 18 19 #define EMC_STATUS_UPDATE_TIMEOUT 1000 20 21 /* register definitions */ 22 #define EMC_INTSTATUS 0x0 23 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) 24 #define EMC_DBG 0x8 25 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 26 #define EMC_DBG_WRITE_ACTIVE_ONLY BIT(30) 27 #define EMC_CFG 0xc 28 #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) 29 #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) 30 #define EMC_CFG_DRAM_ACPD BIT(29) 31 #define EMC_CFG_DYN_SELF_REF BIT(28) 32 #define EMC_PIN 0x24 33 #define EMC_PIN_PIN_CKE BIT(0) 34 #define EMC_PIN_PIN_CKEB BIT(1) 35 #define EMC_PIN_PIN_CKE_PER_DEV BIT(2) 36 #define EMC_TIMING_CONTROL 0x28 37 #define EMC_RC 0x2c 38 #define EMC_RFC 0x30 39 #define EMC_RAS 0x34 40 #define EMC_RP 0x38 41 #define EMC_R2W 0x3c 42 #define EMC_W2R 0x40 43 #define EMC_R2P 0x44 44 #define EMC_W2P 0x48 45 #define EMC_RD_RCD 0x4c 46 #define EMC_WR_RCD 0x50 47 #define EMC_RRD 0x54 48 #define EMC_REXT 0x58 49 #define EMC_WDV 0x5c 50 #define EMC_QUSE 0x60 51 #define EMC_QRST 0x64 52 #define EMC_QSAFE 0x68 53 #define EMC_RDV 0x6c 54 #define EMC_REFRESH 0x70 55 #define EMC_BURST_REFRESH_NUM 0x74 56 #define EMC_PDEX2WR 0x78 57 #define EMC_PDEX2RD 0x7c 58 #define EMC_PCHG2PDEN 0x80 59 #define EMC_ACT2PDEN 0x84 60 #define EMC_AR2PDEN 0x88 61 #define EMC_RW2PDEN 0x8c 62 #define EMC_TXSR 0x90 63 #define EMC_TCKE 0x94 64 #define EMC_TFAW 0x98 65 #define EMC_TRPAB 0x9c 66 #define EMC_TCLKSTABLE 0xa0 67 #define EMC_TCLKSTOP 0xa4 68 #define EMC_TREFBW 0xa8 69 #define EMC_TPPD 0xac 70 #define EMC_ODT_WRITE 0xb0 71 #define EMC_PDEX2MRR 0xb4 72 #define EMC_WEXT 0xb8 73 #define EMC_RFC_SLR 0xc0 74 #define EMC_MRS_WAIT_CNT2 0xc4 75 #define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT 16 76 #define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT 0 77 #define EMC_MRS_WAIT_CNT 0xc8 78 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 79 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ 80 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) 81 82 #define EMC_MRS 0xcc 83 #define EMC_EMRS 0xd0 84 #define EMC_EMRS_USE_EMRS_LONG_CNT BIT(26) 85 #define EMC_REF 0xd4 86 #define EMC_REF_REF_CMD BIT(0) 87 #define EMC_SELF_REF 0xe0 88 #define EMC_MRW 0xe8 89 #define EMC_MRW_MRW_OP_SHIFT 0 90 #define EMC_MRW_MRW_OP_MASK \ 91 (0xff << EMC_MRW_MRW_OP_SHIFT) 92 #define EMC_MRW_MRW_MA_SHIFT 16 93 #define EMC_MRW_USE_MRW_EXT_CNT 27 94 #define EMC_MRW_MRW_DEV_SELECTN_SHIFT 30 95 96 #define EMC_MRR 0xec 97 #define EMC_MRR_DEV_SEL_SHIFT 30 98 #define EMC_MRR_DEV_SEL_MASK 0x3 99 #define EMC_MRR_MA_SHIFT 16 100 #define EMC_MRR_MA_MASK 0xff 101 #define EMC_MRR_DATA_SHIFT 0 102 #define EMC_MRR_DATA_MASK 0xffff 103 104 #define EMC_FBIO_SPARE 0x100 105 #define EMC_FBIO_CFG5 0x104 106 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 107 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK \ 108 (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT) 109 #define EMC_FBIO_CFG5_CMD_TX_DIS BIT(8) 110 111 #define EMC_PDEX2CKE 0x118 112 #define EMC_CKE2PDEN 0x11c 113 #define EMC_MPC 0x128 114 #define EMC_EMRS2 0x12c 115 #define EMC_EMRS2_USE_EMRS2_LONG_CNT BIT(26) 116 #define EMC_MRW2 0x134 117 #define EMC_MRW3 0x138 118 #define EMC_MRW4 0x13c 119 #define EMC_R2R 0x144 120 #define EMC_EINPUT 0x14c 121 #define EMC_EINPUT_DURATION 0x150 122 #define EMC_PUTERM_EXTRA 0x154 123 #define EMC_TCKESR 0x158 124 #define EMC_TPD 0x15c 125 #define EMC_AUTO_CAL_CONFIG 0x2a4 126 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START BIT(0) 127 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL BIT(9) 128 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL BIT(10) 129 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE BIT(29) 130 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) 131 #define EMC_EMC_STATUS 0x2b4 132 #define EMC_EMC_STATUS_MRR_DIVLD BIT(20) 133 #define EMC_EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) 134 #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT 4 135 #define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK \ 136 (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT) 137 #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT 8 138 #define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK \ 139 (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT) 140 141 #define EMC_CFG_2 0x2b8 142 #define EMC_CFG_DIG_DLL 0x2bc 143 #define EMC_CFG_DIG_DLL_CFG_DLL_EN BIT(0) 144 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK BIT(1) 145 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC BIT(3) 146 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK BIT(4) 147 #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT 6 148 #define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK \ 149 (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT) 150 #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT 8 151 #define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK \ 152 (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT) 153 154 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0 155 #define EMC_DIG_DLL_STATUS 0x2c4 156 #define EMC_DIG_DLL_STATUS_DLL_LOCK BIT(15) 157 #define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED BIT(17) 158 #define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT 0 159 #define EMC_DIG_DLL_STATUS_DLL_OUT_MASK \ 160 (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT) 161 162 #define EMC_CFG_DIG_DLL_1 0x2c8 163 #define EMC_RDV_MASK 0x2cc 164 #define EMC_WDV_MASK 0x2d0 165 #define EMC_RDV_EARLY_MASK 0x2d4 166 #define EMC_RDV_EARLY 0x2d8 167 #define EMC_AUTO_CAL_CONFIG8 0x2dc 168 #define EMC_ZCAL_INTERVAL 0x2e0 169 #define EMC_ZCAL_WAIT_CNT 0x2e4 170 #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK 0x7ff 171 #define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT 0 172 173 #define EMC_ZQ_CAL 0x2ec 174 #define EMC_ZQ_CAL_DEV_SEL_SHIFT 30 175 #define EMC_ZQ_CAL_LONG BIT(4) 176 #define EMC_ZQ_CAL_ZQ_LATCH_CMD BIT(1) 177 #define EMC_ZQ_CAL_ZQ_CAL_CMD BIT(0) 178 #define EMC_FDPD_CTRL_DQ 0x310 179 #define EMC_FDPD_CTRL_CMD 0x314 180 #define EMC_PMACRO_CMD_BRICK_CTRL_FDPD 0x318 181 #define EMC_PMACRO_DATA_BRICK_CTRL_FDPD 0x31c 182 #define EMC_PMACRO_BRICK_CTRL_RFU1 0x330 183 #define EMC_PMACRO_BRICK_CTRL_RFU2 0x334 184 #define EMC_TR_TIMING_0 0x3b4 185 #define EMC_TR_CTRL_1 0x3bc 186 #define EMC_TR_RDV 0x3c4 187 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc 188 #define EMC_SEL_DPD_CTRL 0x3d8 189 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN BIT(8) 190 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN BIT(5) 191 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN BIT(4) 192 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN BIT(3) 193 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN BIT(2) 194 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc 195 #define EMC_DYN_SELF_REF_CONTROL 0x3e0 196 #define EMC_TXSRDLL 0x3e4 197 #define EMC_CCFIFO_ADDR 0x3e8 198 #define EMC_CCFIFO_ADDR_STALL_BY_1 (1 << 31) 199 #define EMC_CCFIFO_ADDR_STALL(x) (((x) & 0x7fff) << 16) 200 #define EMC_CCFIFO_ADDR_OFFSET(x) ((x) & 0xffff) 201 #define EMC_CCFIFO_DATA 0x3ec 202 #define EMC_TR_QPOP 0x3f4 203 #define EMC_TR_RDV_MASK 0x3f8 204 #define EMC_TR_QSAFE 0x3fc 205 #define EMC_TR_QRST 0x400 206 #define EMC_ISSUE_QRST 0x428 207 #define EMC_AUTO_CAL_CONFIG2 0x458 208 #define EMC_AUTO_CAL_CONFIG3 0x45c 209 #define EMC_TR_DVFS 0x460 210 #define EMC_AUTO_CAL_CHANNEL 0x464 211 #define EMC_IBDLY 0x468 212 #define EMC_OBDLY 0x46c 213 #define EMC_TXDSRVTTGEN 0x480 214 #define EMC_WE_DURATION 0x48c 215 #define EMC_WS_DURATION 0x490 216 #define EMC_WEV 0x494 217 #define EMC_WSV 0x498 218 #define EMC_CFG_3 0x49c 219 #define EMC_MRW6 0x4a4 220 #define EMC_MRW7 0x4a8 221 #define EMC_MRW8 0x4ac 222 #define EMC_MRW9 0x4b0 223 #define EMC_MRW10 0x4b4 224 #define EMC_MRW11 0x4b8 225 #define EMC_MRW12 0x4bc 226 #define EMC_MRW13 0x4c0 227 #define EMC_MRW14 0x4c4 228 #define EMC_MRW15 0x4d0 229 #define EMC_CFG_SYNC 0x4d4 230 #define EMC_FDPD_CTRL_CMD_NO_RAMP 0x4d8 231 #define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE BIT(0) 232 #define EMC_WDV_CHK 0x4e0 233 #define EMC_CFG_PIPE_2 0x554 234 #define EMC_CFG_PIPE_CLK 0x558 235 #define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON BIT(0) 236 #define EMC_CFG_PIPE_1 0x55c 237 #define EMC_CFG_PIPE 0x560 238 #define EMC_QPOP 0x564 239 #define EMC_QUSE_WIDTH 0x568 240 #define EMC_PUTERM_WIDTH 0x56c 241 #define EMC_AUTO_CAL_CONFIG7 0x574 242 #define EMC_REFCTRL2 0x580 243 #define EMC_FBIO_CFG7 0x584 244 #define EMC_FBIO_CFG7_CH0_ENABLE BIT(1) 245 #define EMC_FBIO_CFG7_CH1_ENABLE BIT(2) 246 #define EMC_DATA_BRLSHFT_0 0x588 247 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT 21 248 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK \ 249 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT) 250 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT 18 251 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK \ 252 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT) 253 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT 15 254 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK \ 255 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT) 256 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT 12 257 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK \ 258 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT) 259 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT 9 260 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK \ 261 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT) 262 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT 6 263 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK \ 264 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT) 265 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT 3 266 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK \ 267 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT) 268 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT 0 269 #define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK \ 270 (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT) 271 272 #define EMC_DATA_BRLSHFT_1 0x58c 273 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT 21 274 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK \ 275 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT) 276 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT 18 277 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK \ 278 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT) 279 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT 15 280 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK \ 281 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT) 282 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT 12 283 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK \ 284 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT) 285 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT 9 286 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK \ 287 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT) 288 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT 6 289 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK \ 290 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT) 291 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT 3 292 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK \ 293 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT) 294 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT 0 295 #define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK \ 296 (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT) 297 298 #define EMC_RFCPB 0x590 299 #define EMC_DQS_BRLSHFT_0 0x594 300 #define EMC_DQS_BRLSHFT_1 0x598 301 #define EMC_CMD_BRLSHFT_0 0x59c 302 #define EMC_CMD_BRLSHFT_1 0x5a0 303 #define EMC_CMD_BRLSHFT_2 0x5a4 304 #define EMC_CMD_BRLSHFT_3 0x5a8 305 #define EMC_QUSE_BRLSHFT_0 0x5ac 306 #define EMC_AUTO_CAL_CONFIG4 0x5b0 307 #define EMC_AUTO_CAL_CONFIG5 0x5b4 308 #define EMC_QUSE_BRLSHFT_1 0x5b8 309 #define EMC_QUSE_BRLSHFT_2 0x5bc 310 #define EMC_CCDMW 0x5c0 311 #define EMC_QUSE_BRLSHFT_3 0x5c4 312 #define EMC_AUTO_CAL_CONFIG6 0x5cc 313 #define EMC_DLL_CFG_0 0x5e4 314 #define EMC_DLL_CFG_1 0x5e8 315 #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT 10 316 #define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK \ 317 (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT) 318 319 #define EMC_CONFIG_SAMPLE_DELAY 0x5f0 320 #define EMC_CFG_UPDATE 0x5f4 321 #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT 9 322 #define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK \ 323 (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT) 324 325 #define EMC_PMACRO_QUSE_DDLL_RANK0_0 0x600 326 #define EMC_PMACRO_QUSE_DDLL_RANK0_1 0x604 327 #define EMC_PMACRO_QUSE_DDLL_RANK0_2 0x608 328 #define EMC_PMACRO_QUSE_DDLL_RANK0_3 0x60c 329 #define EMC_PMACRO_QUSE_DDLL_RANK0_4 0x610 330 #define EMC_PMACRO_QUSE_DDLL_RANK0_5 0x614 331 #define EMC_PMACRO_QUSE_DDLL_RANK1_0 0x620 332 #define EMC_PMACRO_QUSE_DDLL_RANK1_1 0x624 333 #define EMC_PMACRO_QUSE_DDLL_RANK1_2 0x628 334 #define EMC_PMACRO_QUSE_DDLL_RANK1_3 0x62c 335 #define EMC_PMACRO_QUSE_DDLL_RANK1_4 0x630 336 #define EMC_PMACRO_QUSE_DDLL_RANK1_5 0x634 337 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0 0x640 338 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \ 339 16 340 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \ 341 (0x3ff << \ 342 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT) 343 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \ 344 0 345 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \ 346 (0x3ff << \ 347 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT) 348 349 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1 0x644 350 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \ 351 16 352 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \ 353 (0x3ff << \ 354 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT) 355 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \ 356 0 357 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \ 358 (0x3ff << \ 359 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT) 360 361 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2 0x648 362 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \ 363 16 364 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \ 365 (0x3ff << \ 366 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT) 367 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \ 368 0 369 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \ 370 (0x3ff << \ 371 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT) 372 373 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3 0x64c 374 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \ 375 16 376 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \ 377 (0x3ff << \ 378 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT) 379 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \ 380 0 381 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \ 382 (0x3ff << \ 383 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT) 384 385 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4 0x650 386 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5 0x654 387 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0 0x660 388 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \ 389 16 390 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \ 391 (0x3ff << \ 392 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT) 393 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \ 394 0 395 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \ 396 (0x3ff << \ 397 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT) 398 399 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1 0x664 400 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \ 401 16 402 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \ 403 (0x3ff << \ 404 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT) 405 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \ 406 0 407 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \ 408 (0x3ff << \ 409 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT) 410 411 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2 0x668 412 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \ 413 16 414 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \ 415 (0x3ff << \ 416 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT) 417 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \ 418 0 419 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \ 420 (0x3ff << \ 421 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT) 422 423 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3 0x66c 424 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \ 425 16 426 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \ 427 (0x3ff << \ 428 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT) 429 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \ 430 0 431 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \ 432 (0x3ff << \ 433 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT) 434 435 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4 0x670 436 #define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5 0x674 437 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0 0x680 438 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1 0x684 439 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2 0x688 440 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3 0x68c 441 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4 0x690 442 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5 0x694 443 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0 0x6a0 444 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1 0x6a4 445 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2 0x6a8 446 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3 0x6ac 447 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4 0x6b0 448 #define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5 0x6b4 449 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0 0x6c0 450 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1 0x6c4 451 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2 0x6c8 452 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3 0x6cc 453 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0 0x6e0 454 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1 0x6e4 455 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2 0x6e8 456 #define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3 0x6ec 457 #define EMC_PMACRO_TX_PWRD_0 0x720 458 #define EMC_PMACRO_TX_PWRD_1 0x724 459 #define EMC_PMACRO_TX_PWRD_2 0x728 460 #define EMC_PMACRO_TX_PWRD_3 0x72c 461 #define EMC_PMACRO_TX_PWRD_4 0x730 462 #define EMC_PMACRO_TX_PWRD_5 0x734 463 #define EMC_PMACRO_TX_SEL_CLK_SRC_0 0x740 464 #define EMC_PMACRO_TX_SEL_CLK_SRC_1 0x744 465 #define EMC_PMACRO_TX_SEL_CLK_SRC_3 0x74c 466 #define EMC_PMACRO_TX_SEL_CLK_SRC_2 0x748 467 #define EMC_PMACRO_TX_SEL_CLK_SRC_4 0x750 468 #define EMC_PMACRO_TX_SEL_CLK_SRC_5 0x754 469 #define EMC_PMACRO_DDLL_BYPASS 0x760 470 #define EMC_PMACRO_DDLL_PWRD_0 0x770 471 #define EMC_PMACRO_DDLL_PWRD_1 0x774 472 #define EMC_PMACRO_DDLL_PWRD_2 0x778 473 #define EMC_PMACRO_CMD_CTRL_0 0x780 474 #define EMC_PMACRO_CMD_CTRL_1 0x784 475 #define EMC_PMACRO_CMD_CTRL_2 0x788 476 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0x800 477 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0x804 478 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0x808 479 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3 0x80c 480 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0x810 481 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0x814 482 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0x818 483 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3 0x81c 484 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0x820 485 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0x824 486 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0x828 487 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3 0x82c 488 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0x830 489 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0x834 490 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0x838 491 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3 0x83c 492 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0x840 493 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0x844 494 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0x848 495 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3 0x84c 496 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0x850 497 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0x854 498 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0x858 499 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3 0x85c 500 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0x860 501 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0x864 502 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0x868 503 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3 0x86c 504 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0x870 505 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0x874 506 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0x878 507 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3 0x87c 508 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0 0x880 509 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1 0x884 510 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2 0x888 511 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3 0x88c 512 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0 0x890 513 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1 0x894 514 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2 0x898 515 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3 0x89c 516 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0 0x8a0 517 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1 0x8a4 518 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2 0x8a8 519 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3 0x8ac 520 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0 0x8b0 521 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1 0x8b4 522 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2 0x8b8 523 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3 0x8bc 524 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0x900 525 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0x904 526 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0x908 527 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3 0x90c 528 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0x910 529 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0x914 530 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0x918 531 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3 0x91c 532 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0x920 533 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0x924 534 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0x928 535 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3 0x92c 536 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0x930 537 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0x934 538 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0x938 539 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3 0x93c 540 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0x940 541 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0x944 542 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0x948 543 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3 0x94c 544 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0x950 545 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0x954 546 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0x958 547 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3 0x95c 548 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0x960 549 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0x964 550 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0x968 551 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3 0x96c 552 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0x970 553 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0x974 554 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0x978 555 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3 0x97c 556 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0 0x980 557 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1 0x984 558 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2 0x988 559 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3 0x98c 560 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0 0x990 561 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1 0x994 562 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2 0x998 563 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3 0x99c 564 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0 0x9a0 565 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1 0x9a4 566 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2 0x9a8 567 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3 0x9ac 568 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0 0x9b0 569 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1 0x9b4 570 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2 0x9b8 571 #define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3 0x9bc 572 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0 0xa00 573 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1 0xa04 574 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2 0xa08 575 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0 0xa10 576 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1 0xa14 577 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2 0xa18 578 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0 0xa20 579 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1 0xa24 580 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2 0xa28 581 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0 0xa30 582 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1 0xa34 583 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2 0xa38 584 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0 0xa40 585 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1 0xa44 586 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2 0xa48 587 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0 0xa50 588 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1 0xa54 589 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2 0xa58 590 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0 0xa60 591 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1 0xa64 592 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2 0xa68 593 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0 0xa70 594 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1 0xa74 595 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2 0xa78 596 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0 0xb00 597 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1 0xb04 598 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2 0xb08 599 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0 0xb10 600 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1 0xb14 601 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2 0xb18 602 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0 0xb20 603 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1 0xb24 604 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2 0xb28 605 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0 0xb30 606 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1 0xb34 607 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2 0xb38 608 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0 0xb40 609 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1 0xb44 610 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2 0xb48 611 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0 0xb50 612 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1 0xb54 613 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2 0xb58 614 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0 0xb60 615 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1 0xb64 616 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2 0xb68 617 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0 0xb70 618 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1 0xb74 619 #define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2 0xb78 620 #define EMC_PMACRO_IB_VREF_DQ_0 0xbe0 621 #define EMC_PMACRO_IB_VREF_DQ_1 0xbe4 622 #define EMC_PMACRO_IB_VREF_DQS_0 0xbf0 623 #define EMC_PMACRO_IB_VREF_DQS_1 0xbf4 624 #define EMC_PMACRO_DDLL_LONG_CMD_0 0xc00 625 #define EMC_PMACRO_DDLL_LONG_CMD_1 0xc04 626 #define EMC_PMACRO_DDLL_LONG_CMD_2 0xc08 627 #define EMC_PMACRO_DDLL_LONG_CMD_3 0xc0c 628 #define EMC_PMACRO_DDLL_LONG_CMD_4 0xc10 629 #define EMC_PMACRO_DDLL_LONG_CMD_5 0xc14 630 #define EMC_PMACRO_DDLL_SHORT_CMD_0 0xc20 631 #define EMC_PMACRO_DDLL_SHORT_CMD_1 0xc24 632 #define EMC_PMACRO_DDLL_SHORT_CMD_2 0xc28 633 #define EMC_PMACRO_CFG_PM_GLOBAL_0 0xc30 634 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0 BIT(16) 635 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1 BIT(17) 636 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2 BIT(18) 637 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3 BIT(19) 638 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4 BIT(20) 639 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5 BIT(21) 640 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6 BIT(22) 641 #define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7 BIT(23) 642 #define EMC_PMACRO_VTTGEN_CTRL_0 0xc34 643 #define EMC_PMACRO_VTTGEN_CTRL_1 0xc38 644 #define EMC_PMACRO_BG_BIAS_CTRL_0 0xc3c 645 #define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD BIT(0) 646 #define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD BIT(2) 647 #define EMC_PMACRO_PAD_CFG_CTRL 0xc40 648 #define EMC_PMACRO_ZCTRL 0xc44 649 #define EMC_PMACRO_CMD_PAD_RX_CTRL 0xc50 650 #define EMC_PMACRO_DATA_PAD_RX_CTRL 0xc54 651 #define EMC_PMACRO_CMD_RX_TERM_MODE 0xc58 652 #define EMC_PMACRO_DATA_RX_TERM_MODE 0xc5c 653 #define EMC_PMACRO_CMD_PAD_TX_CTRL 0xc60 654 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC BIT(1) 655 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC BIT(9) 656 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC BIT(16) 657 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC BIT(24) 658 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON BIT(26) 659 660 #define EMC_PMACRO_DATA_PAD_TX_CTRL 0xc64 661 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF BIT(0) 662 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC BIT(1) 663 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF BIT(8) 664 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC BIT(9) 665 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC BIT(16) 666 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC BIT(24) 667 668 #define EMC_PMACRO_COMMON_PAD_TX_CTRL 0xc68 669 #define EMC_PMACRO_AUTOCAL_CFG_COMMON 0xc78 670 #define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS BIT(16) 671 #define EMC_PMACRO_VTTGEN_CTRL_2 0xcf0 672 #define EMC_PMACRO_IB_RXRT 0xcf4 673 #define EMC_PMACRO_TRAINING_CTRL_0 0xcf8 674 #define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR BIT(3) 675 #define EMC_PMACRO_TRAINING_CTRL_1 0xcfc 676 #define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR BIT(3) 677 #define EMC_TRAINING_CTRL 0xe04 678 #define EMC_TRAINING_QUSE_CORS_CTRL 0xe0c 679 #define EMC_TRAINING_QUSE_FINE_CTRL 0xe10 680 #define EMC_TRAINING_QUSE_CTRL_MISC 0xe14 681 #define EMC_TRAINING_WRITE_FINE_CTRL 0xe18 682 #define EMC_TRAINING_WRITE_CTRL_MISC 0xe1c 683 #define EMC_TRAINING_WRITE_VREF_CTRL 0xe20 684 #define EMC_TRAINING_READ_FINE_CTRL 0xe24 685 #define EMC_TRAINING_READ_CTRL_MISC 0xe28 686 #define EMC_TRAINING_READ_VREF_CTRL 0xe2c 687 #define EMC_TRAINING_CA_FINE_CTRL 0xe30 688 #define EMC_TRAINING_CA_CTRL_MISC 0xe34 689 #define EMC_TRAINING_CA_CTRL_MISC1 0xe38 690 #define EMC_TRAINING_CA_VREF_CTRL 0xe3c 691 #define EMC_TRAINING_SETTLE 0xe44 692 #define EMC_TRAINING_MPC 0xe5c 693 #define EMC_TRAINING_VREF_SETTLE 0xe6c 694 #define EMC_TRAINING_QUSE_VREF_CTRL 0xed0 695 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0 0xed4 696 #define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1 0xed8 697 698 #define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS BIT(0) 699 #define EMC_COPY_TABLE_PARAM_TRIM_REGS BIT(1) 700 701 enum burst_regs_list { 702 EMC_RP_INDEX = 6, 703 EMC_R2P_INDEX = 9, 704 EMC_W2P_INDEX, 705 EMC_MRW6_INDEX = 31, 706 EMC_REFRESH_INDEX = 41, 707 EMC_PRE_REFRESH_REQ_CNT_INDEX = 43, 708 EMC_TRPAB_INDEX = 59, 709 EMC_MRW7_INDEX = 62, 710 EMC_FBIO_CFG5_INDEX = 65, 711 EMC_FBIO_CFG7_INDEX, 712 EMC_CFG_DIG_DLL_INDEX, 713 EMC_ZCAL_INTERVAL_INDEX = 139, 714 EMC_ZCAL_WAIT_CNT_INDEX, 715 EMC_MRS_WAIT_CNT_INDEX = 141, 716 EMC_DLL_CFG_0_INDEX = 144, 717 EMC_PMACRO_AUTOCAL_CFG_COMMON_INDEX = 146, 718 EMC_CFG_INDEX = 148, 719 EMC_DYN_SELF_REF_CONTROL_INDEX = 150, 720 EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX = 161, 721 EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX, 722 EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX, 723 EMC_PMACRO_BRICK_CTRL_RFU1_INDEX = 167, 724 EMC_PMACRO_BG_BIAS_CTRL_0_INDEX = 171, 725 EMC_MRW14_INDEX = 199, 726 EMC_MRW15_INDEX = 220, 727 }; 728 729 enum trim_regs_list { 730 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_INDEX = 60, 731 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_INDEX, 732 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_INDEX, 733 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_INDEX, 734 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4_INDEX, 735 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5_INDEX, 736 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_INDEX, 737 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_INDEX, 738 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_INDEX, 739 EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_INDEX, 740 }; 741 742 enum burst_mc_regs_list { 743 MC_EMEM_ARB_MISC0_INDEX = 20, 744 }; 745 746 enum { 747 T_RP, 748 T_FC_LPDDR4, 749 T_RFC, 750 T_PDEX, 751 RL, 752 }; 753 754 enum { 755 AUTO_PD = 0, 756 MAN_SR = 2, 757 }; 758 759 enum { 760 ASSEMBLY = 0, 761 ACTIVE, 762 }; 763 764 enum { 765 C0D0U0, 766 C0D0U1, 767 C0D1U0, 768 C0D1U1, 769 C1D0U0, 770 C1D0U1, 771 C1D1U0, 772 C1D1U1, 773 DRAM_CLKTREE_NUM, 774 }; 775 776 #define VREF_REGS_PER_CHANNEL_SIZE 4 777 #define DRAM_TIMINGS_NUM 5 778 #define BURST_REGS_PER_CHANNEL_SIZE 8 779 #define TRIM_REGS_PER_CHANNEL_SIZE 10 780 #define PTFV_ARRAY_SIZE 12 781 #define SAVE_RESTORE_MOD_REGS_SIZE 12 782 #define TRAINING_MOD_REGS_SIZE 20 783 #define BURST_UP_DOWN_REGS_SIZE 24 784 #define BURST_MC_REGS_SIZE 33 785 #define TRIM_REGS_SIZE 138 786 #define BURST_REGS_SIZE 221 787 788 struct tegra210_emc_per_channel_regs { 789 u16 bank; 790 u16 offset; 791 }; 792 793 struct tegra210_emc_table_register_offsets { 794 u16 burst[BURST_REGS_SIZE]; 795 u16 trim[TRIM_REGS_SIZE]; 796 u16 burst_mc[BURST_MC_REGS_SIZE]; 797 u16 la_scale[BURST_UP_DOWN_REGS_SIZE]; 798 struct tegra210_emc_per_channel_regs burst_per_channel[BURST_REGS_PER_CHANNEL_SIZE]; 799 struct tegra210_emc_per_channel_regs trim_per_channel[TRIM_REGS_PER_CHANNEL_SIZE]; 800 struct tegra210_emc_per_channel_regs vref_per_channel[VREF_REGS_PER_CHANNEL_SIZE]; 801 }; 802 803 struct tegra210_emc_timing { 804 u32 revision; 805 const char dvfs_ver[60]; 806 u32 rate; 807 u32 min_volt; 808 u32 gpu_min_volt; 809 const char clock_src[32]; 810 u32 clk_src_emc; 811 u32 needs_training; 812 u32 training_pattern; 813 u32 trained; 814 815 u32 periodic_training; 816 u32 trained_dram_clktree[DRAM_CLKTREE_NUM]; 817 u32 current_dram_clktree[DRAM_CLKTREE_NUM]; 818 u32 run_clocks; 819 u32 tree_margin; 820 821 u32 num_burst; 822 u32 num_burst_per_ch; 823 u32 num_trim; 824 u32 num_trim_per_ch; 825 u32 num_mc_regs; 826 u32 num_up_down; 827 u32 vref_num; 828 u32 training_mod_num; 829 u32 dram_timing_num; 830 831 u32 ptfv_list[PTFV_ARRAY_SIZE]; 832 833 u32 burst_regs[BURST_REGS_SIZE]; 834 u32 burst_reg_per_ch[BURST_REGS_PER_CHANNEL_SIZE]; 835 u32 shadow_regs_ca_train[BURST_REGS_SIZE]; 836 u32 shadow_regs_quse_train[BURST_REGS_SIZE]; 837 u32 shadow_regs_rdwr_train[BURST_REGS_SIZE]; 838 839 u32 trim_regs[TRIM_REGS_SIZE]; 840 u32 trim_perch_regs[TRIM_REGS_PER_CHANNEL_SIZE]; 841 842 u32 vref_perch_regs[VREF_REGS_PER_CHANNEL_SIZE]; 843 844 u32 dram_timings[DRAM_TIMINGS_NUM]; 845 u32 training_mod_regs[TRAINING_MOD_REGS_SIZE]; 846 u32 save_restore_mod_regs[SAVE_RESTORE_MOD_REGS_SIZE]; 847 u32 burst_mc_regs[BURST_MC_REGS_SIZE]; 848 u32 la_scale_regs[BURST_UP_DOWN_REGS_SIZE]; 849 850 u32 min_mrs_wait; 851 u32 emc_mrw; 852 u32 emc_mrw2; 853 u32 emc_mrw3; 854 u32 emc_mrw4; 855 u32 emc_mrw9; 856 u32 emc_mrs; 857 u32 emc_emrs; 858 u32 emc_emrs2; 859 u32 emc_auto_cal_config; 860 u32 emc_auto_cal_config2; 861 u32 emc_auto_cal_config3; 862 u32 emc_auto_cal_config4; 863 u32 emc_auto_cal_config5; 864 u32 emc_auto_cal_config6; 865 u32 emc_auto_cal_config7; 866 u32 emc_auto_cal_config8; 867 u32 emc_cfg_2; 868 u32 emc_sel_dpd_ctrl; 869 u32 emc_fdpd_ctrl_cmd_no_ramp; 870 u32 dll_clk_src; 871 u32 clk_out_enb_x_0_clk_enb_emc_dll; 872 u32 latency; 873 }; 874 875 enum tegra210_emc_refresh { 876 TEGRA210_EMC_REFRESH_NOMINAL = 0, 877 TEGRA210_EMC_REFRESH_2X, 878 TEGRA210_EMC_REFRESH_4X, 879 TEGRA210_EMC_REFRESH_THROTTLE, /* 4x Refresh + derating. */ 880 }; 881 882 #define DRAM_TYPE_DDR3 0 883 #define DRAM_TYPE_LPDDR4 1 884 #define DRAM_TYPE_LPDDR2 2 885 #define DRAM_TYPE_DDR2 3 886 887 struct tegra210_emc { 888 struct tegra_mc *mc; 889 struct device *dev; 890 struct clk *clk; 891 892 /* nominal EMC frequency table */ 893 struct tegra210_emc_timing *nominal; 894 /* derated EMC frequency table */ 895 struct tegra210_emc_timing *derated; 896 897 /* currently selected table (nominal or derated) */ 898 struct tegra210_emc_timing *timings; 899 unsigned int num_timings; 900 901 const struct tegra210_emc_table_register_offsets *offsets; 902 903 const struct tegra210_emc_sequence *sequence; 904 spinlock_t lock; 905 906 void __iomem *regs, *channel[2]; 907 unsigned int num_channels; 908 unsigned int num_devices; 909 unsigned int dram_type; 910 911 struct tegra210_emc_timing *last; 912 struct tegra210_emc_timing *next; 913 914 unsigned int training_interval; 915 struct timer_list training; 916 917 enum tegra210_emc_refresh refresh; 918 unsigned int refresh_poll_interval; 919 struct timer_list refresh_timer; 920 unsigned int temperature; 921 atomic_t refresh_poll; 922 923 ktime_t clkchange_time; 924 int clkchange_delay; 925 926 unsigned long resume_rate; 927 928 struct { 929 struct dentry *root; 930 unsigned long min_rate; 931 unsigned long max_rate; 932 unsigned int temperature; 933 } debugfs; 934 935 struct tegra210_clk_emc_provider provider; 936 }; 937 938 struct tegra210_emc_sequence { 939 u8 revision; 940 void (*set_clock)(struct tegra210_emc *emc, u32 clksrc); 941 u32 (*periodic_compensation)(struct tegra210_emc *emc); 942 }; 943 944 static inline void emc_writel(struct tegra210_emc *emc, u32 value, 945 unsigned int offset) 946 { 947 writel_relaxed(value, emc->regs + offset); 948 } 949 950 static inline u32 emc_readl(struct tegra210_emc *emc, unsigned int offset) 951 { 952 return readl_relaxed(emc->regs + offset); 953 } 954 955 static inline void emc_channel_writel(struct tegra210_emc *emc, 956 unsigned int channel, 957 u32 value, unsigned int offset) 958 { 959 writel_relaxed(value, emc->channel[channel] + offset); 960 } 961 962 static inline u32 emc_channel_readl(struct tegra210_emc *emc, 963 unsigned int channel, unsigned int offset) 964 { 965 return readl_relaxed(emc->channel[channel] + offset); 966 } 967 968 static inline void ccfifo_writel(struct tegra210_emc *emc, u32 value, 969 unsigned int offset, u32 delay) 970 { 971 writel_relaxed(value, emc->regs + EMC_CCFIFO_DATA); 972 973 value = EMC_CCFIFO_ADDR_STALL_BY_1 | EMC_CCFIFO_ADDR_STALL(delay) | 974 EMC_CCFIFO_ADDR_OFFSET(offset); 975 writel_relaxed(value, emc->regs + EMC_CCFIFO_ADDR); 976 } 977 978 static inline u32 div_o3(u32 a, u32 b) 979 { 980 u32 result = a / b; 981 982 if ((b * result) < a) 983 return result + 1; 984 985 return result; 986 } 987 988 /* from tegra210-emc-r21021.c */ 989 extern const struct tegra210_emc_sequence tegra210_emc_r21021; 990 991 int tegra210_emc_set_refresh(struct tegra210_emc *emc, 992 enum tegra210_emc_refresh refresh); 993 u32 tegra210_emc_mrr_read(struct tegra210_emc *emc, unsigned int chip, 994 unsigned int address); 995 void tegra210_emc_do_clock_change(struct tegra210_emc *emc, u32 clksrc); 996 void tegra210_emc_set_shadow_bypass(struct tegra210_emc *emc, int set); 997 void tegra210_emc_timing_update(struct tegra210_emc *emc); 998 u32 tegra210_emc_get_dll_state(struct tegra210_emc_timing *next); 999 struct tegra210_emc_timing *tegra210_emc_find_timing(struct tegra210_emc *emc, 1000 unsigned long rate); 1001 void tegra210_emc_adjust_timing(struct tegra210_emc *emc, 1002 struct tegra210_emc_timing *timing); 1003 int tegra210_emc_wait_for_update(struct tegra210_emc *emc, unsigned int channel, 1004 unsigned int offset, u32 bit_mask, bool state); 1005 unsigned long tegra210_emc_actual_osc_clocks(u32 in); 1006 u32 tegra210_emc_compensate(struct tegra210_emc_timing *next, u32 offset); 1007 void tegra210_emc_dll_disable(struct tegra210_emc *emc); 1008 void tegra210_emc_dll_enable(struct tegra210_emc *emc); 1009 u32 tegra210_emc_dll_prelock(struct tegra210_emc *emc, u32 clksrc); 1010 u32 tegra210_emc_dvfs_power_ramp_down(struct tegra210_emc *emc, u32 clk, 1011 bool flip_backward); 1012 u32 tegra210_emc_dvfs_power_ramp_up(struct tegra210_emc *emc, u32 clk, 1013 bool flip_backward); 1014 void tegra210_emc_reset_dram_clktree_values(struct tegra210_emc_timing *timing); 1015 void tegra210_emc_start_periodic_compensation(struct tegra210_emc *emc); 1016 1017 #endif 1018