1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/iommu.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/platform_device.h> 13 14 #include <soc/tegra/mc.h> 15 16 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 17 #include <dt-bindings/memory/tegra186-mc.h> 18 #endif 19 20 #include "mc.h" 21 22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) 23 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) 24 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) 25 26 static int tegra186_mc_probe(struct tegra_mc *mc) 27 { 28 struct platform_device *pdev = to_platform_device(mc->dev); 29 struct resource *res; 30 unsigned int i; 31 char name[8]; 32 int err; 33 34 /* 35 * From Tegra264, the SID region is not present in MC node and BROADCAST is first. 36 * The common function 'tegra_mc_probe()' already maps first region entry from DT. 37 * Check if the SID region is present in DT then map BROADCAST. Otherwise, consider 38 * the first entry mapped in mc probe as the BROADCAST region. This is done to avoid 39 * mapping the region twice when SID is not present and keep backward compatibility. 40 */ 41 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid"); 42 if (res) 43 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); 44 else 45 mc->bcast_ch_regs = mc->regs; 46 47 if (IS_ERR(mc->bcast_ch_regs)) { 48 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { 49 dev_warn(&pdev->dev, 50 "Broadcast channel is missing, please update your device-tree\n"); 51 mc->bcast_ch_regs = NULL; 52 goto populate; 53 } 54 55 return PTR_ERR(mc->bcast_ch_regs); 56 } 57 58 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs), 59 GFP_KERNEL); 60 if (!mc->ch_regs) 61 return -ENOMEM; 62 63 for (i = 0; i < mc->soc->num_channels; i++) { 64 snprintf(name, sizeof(name), "ch%u", i); 65 66 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name); 67 if (IS_ERR(mc->ch_regs[i])) 68 return PTR_ERR(mc->ch_regs[i]); 69 } 70 71 populate: 72 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); 73 if (err < 0) 74 return err; 75 76 return 0; 77 } 78 79 static void tegra186_mc_remove(struct tegra_mc *mc) 80 { 81 of_platform_depopulate(mc->dev); 82 } 83 84 #if IS_ENABLED(CONFIG_IOMMU_API) 85 static void tegra186_mc_client_sid_override(struct tegra_mc *mc, 86 const struct tegra_mc_client *client, 87 unsigned int sid) 88 { 89 u32 value, old; 90 91 if (client->regs.sid.security == 0 && client->regs.sid.override == 0) 92 return; 93 94 value = readl(mc->regs + client->regs.sid.security); 95 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { 96 /* 97 * If the secure firmware has locked this down the override 98 * for this memory client, there's nothing we can do here. 99 */ 100 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) 101 return; 102 103 /* 104 * Otherwise, try to set the override itself. Typically the 105 * secure firmware will never have set this configuration. 106 * Instead, it will either have disabled write access to 107 * this field, or it will already have set an explicit 108 * override itself. 109 */ 110 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); 111 112 value |= MC_SID_STREAMID_SECURITY_OVERRIDE; 113 writel(value, mc->regs + client->regs.sid.security); 114 } 115 116 value = readl(mc->regs + client->regs.sid.override); 117 old = value & MC_SID_STREAMID_OVERRIDE_MASK; 118 119 if (old != sid) { 120 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, 121 client->name, sid); 122 writel(sid, mc->regs + client->regs.sid.override); 123 } 124 } 125 #endif 126 127 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) 128 { 129 #if IS_ENABLED(CONFIG_IOMMU_API) 130 struct of_phandle_args args; 131 unsigned int i, index = 0; 132 u32 sid; 133 134 if (!tegra_dev_iommu_get_stream_id(dev, &sid)) 135 return 0; 136 137 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", 138 index, &args)) { 139 if (args.np == mc->dev->of_node && args.args_count != 0) { 140 for (i = 0; i < mc->soc->num_clients; i++) { 141 const struct tegra_mc_client *client = &mc->soc->clients[i]; 142 143 if (client->id == args.args[0]) 144 tegra186_mc_client_sid_override( 145 mc, client, 146 sid & MC_SID_STREAMID_OVERRIDE_MASK); 147 } 148 } 149 150 index++; 151 } 152 #endif 153 154 return 0; 155 } 156 157 static void tegra186_mc_resume(struct tegra_mc *mc) 158 { 159 #if IS_ENABLED(CONFIG_IOMMU_API) 160 unsigned int i; 161 162 for (i = 0; i < mc->soc->num_clients; i++) { 163 const struct tegra_mc_client *client = &mc->soc->clients[i]; 164 165 tegra186_mc_client_sid_override(mc, client, client->sid); 166 } 167 #endif 168 } 169 170 const struct tegra_mc_ops tegra186_mc_ops = { 171 .probe = tegra186_mc_probe, 172 .remove = tegra186_mc_remove, 173 .resume = tegra186_mc_resume, 174 .probe_device = tegra186_mc_probe_device, 175 }; 176 177 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 178 static const struct tegra_mc_client tegra186_mc_clients[] = { 179 { 180 .id = TEGRA186_MEMORY_CLIENT_PTCR, 181 .name = "ptcr", 182 .sid = TEGRA186_SID_PASSTHROUGH, 183 .regs = { 184 .sid = { 185 .override = 0x000, 186 .security = 0x004, 187 }, 188 }, 189 }, { 190 .id = TEGRA186_MEMORY_CLIENT_AFIR, 191 .name = "afir", 192 .sid = TEGRA186_SID_AFI, 193 .regs = { 194 .sid = { 195 .override = 0x070, 196 .security = 0x074, 197 }, 198 }, 199 }, { 200 .id = TEGRA186_MEMORY_CLIENT_HDAR, 201 .name = "hdar", 202 .sid = TEGRA186_SID_HDA, 203 .regs = { 204 .sid = { 205 .override = 0x0a8, 206 .security = 0x0ac, 207 }, 208 }, 209 }, { 210 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, 211 .name = "host1xdmar", 212 .sid = TEGRA186_SID_HOST1X, 213 .regs = { 214 .sid = { 215 .override = 0x0b0, 216 .security = 0x0b4, 217 }, 218 }, 219 }, { 220 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD, 221 .name = "nvencsrd", 222 .sid = TEGRA186_SID_NVENC, 223 .regs = { 224 .sid = { 225 .override = 0x0e0, 226 .security = 0x0e4, 227 }, 228 }, 229 }, { 230 .id = TEGRA186_MEMORY_CLIENT_SATAR, 231 .name = "satar", 232 .sid = TEGRA186_SID_SATA, 233 .regs = { 234 .sid = { 235 .override = 0x0f8, 236 .security = 0x0fc, 237 }, 238 }, 239 }, { 240 .id = TEGRA186_MEMORY_CLIENT_MPCORER, 241 .name = "mpcorer", 242 .sid = TEGRA186_SID_PASSTHROUGH, 243 .regs = { 244 .sid = { 245 .override = 0x138, 246 .security = 0x13c, 247 }, 248 }, 249 }, { 250 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR, 251 .name = "nvencswr", 252 .sid = TEGRA186_SID_NVENC, 253 .regs = { 254 .sid = { 255 .override = 0x158, 256 .security = 0x15c, 257 }, 258 }, 259 }, { 260 .id = TEGRA186_MEMORY_CLIENT_AFIW, 261 .name = "afiw", 262 .sid = TEGRA186_SID_AFI, 263 .regs = { 264 .sid = { 265 .override = 0x188, 266 .security = 0x18c, 267 }, 268 }, 269 }, { 270 .id = TEGRA186_MEMORY_CLIENT_HDAW, 271 .name = "hdaw", 272 .sid = TEGRA186_SID_HDA, 273 .regs = { 274 .sid = { 275 .override = 0x1a8, 276 .security = 0x1ac, 277 }, 278 }, 279 }, { 280 .id = TEGRA186_MEMORY_CLIENT_MPCOREW, 281 .name = "mpcorew", 282 .sid = TEGRA186_SID_PASSTHROUGH, 283 .regs = { 284 .sid = { 285 .override = 0x1c8, 286 .security = 0x1cc, 287 }, 288 }, 289 }, { 290 .id = TEGRA186_MEMORY_CLIENT_SATAW, 291 .name = "sataw", 292 .sid = TEGRA186_SID_SATA, 293 .regs = { 294 .sid = { 295 .override = 0x1e8, 296 .security = 0x1ec, 297 }, 298 }, 299 }, { 300 .id = TEGRA186_MEMORY_CLIENT_ISPRA, 301 .name = "ispra", 302 .sid = TEGRA186_SID_ISP, 303 .regs = { 304 .sid = { 305 .override = 0x220, 306 .security = 0x224, 307 }, 308 }, 309 }, { 310 .id = TEGRA186_MEMORY_CLIENT_ISPWA, 311 .name = "ispwa", 312 .sid = TEGRA186_SID_ISP, 313 .regs = { 314 .sid = { 315 .override = 0x230, 316 .security = 0x234, 317 }, 318 }, 319 }, { 320 .id = TEGRA186_MEMORY_CLIENT_ISPWB, 321 .name = "ispwb", 322 .sid = TEGRA186_SID_ISP, 323 .regs = { 324 .sid = { 325 .override = 0x238, 326 .security = 0x23c, 327 }, 328 }, 329 }, { 330 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, 331 .name = "xusb_hostr", 332 .sid = TEGRA186_SID_XUSB_HOST, 333 .regs = { 334 .sid = { 335 .override = 0x250, 336 .security = 0x254, 337 }, 338 }, 339 }, { 340 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, 341 .name = "xusb_hostw", 342 .sid = TEGRA186_SID_XUSB_HOST, 343 .regs = { 344 .sid = { 345 .override = 0x258, 346 .security = 0x25c, 347 }, 348 }, 349 }, { 350 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, 351 .name = "xusb_devr", 352 .sid = TEGRA186_SID_XUSB_DEV, 353 .regs = { 354 .sid = { 355 .override = 0x260, 356 .security = 0x264, 357 }, 358 }, 359 }, { 360 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, 361 .name = "xusb_devw", 362 .sid = TEGRA186_SID_XUSB_DEV, 363 .regs = { 364 .sid = { 365 .override = 0x268, 366 .security = 0x26c, 367 }, 368 }, 369 }, { 370 .id = TEGRA186_MEMORY_CLIENT_TSECSRD, 371 .name = "tsecsrd", 372 .sid = TEGRA186_SID_TSEC, 373 .regs = { 374 .sid = { 375 .override = 0x2a0, 376 .security = 0x2a4, 377 }, 378 }, 379 }, { 380 .id = TEGRA186_MEMORY_CLIENT_TSECSWR, 381 .name = "tsecswr", 382 .sid = TEGRA186_SID_TSEC, 383 .regs = { 384 .sid = { 385 .override = 0x2a8, 386 .security = 0x2ac, 387 }, 388 }, 389 }, { 390 .id = TEGRA186_MEMORY_CLIENT_GPUSRD, 391 .name = "gpusrd", 392 .sid = TEGRA186_SID_GPU, 393 .regs = { 394 .sid = { 395 .override = 0x2c0, 396 .security = 0x2c4, 397 }, 398 }, 399 }, { 400 .id = TEGRA186_MEMORY_CLIENT_GPUSWR, 401 .name = "gpuswr", 402 .sid = TEGRA186_SID_GPU, 403 .regs = { 404 .sid = { 405 .override = 0x2c8, 406 .security = 0x2cc, 407 }, 408 }, 409 }, { 410 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA, 411 .name = "sdmmcra", 412 .sid = TEGRA186_SID_SDMMC1, 413 .regs = { 414 .sid = { 415 .override = 0x300, 416 .security = 0x304, 417 }, 418 }, 419 }, { 420 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, 421 .name = "sdmmcraa", 422 .sid = TEGRA186_SID_SDMMC2, 423 .regs = { 424 .sid = { 425 .override = 0x308, 426 .security = 0x30c, 427 }, 428 }, 429 }, { 430 .id = TEGRA186_MEMORY_CLIENT_SDMMCR, 431 .name = "sdmmcr", 432 .sid = TEGRA186_SID_SDMMC3, 433 .regs = { 434 .sid = { 435 .override = 0x310, 436 .security = 0x314, 437 }, 438 }, 439 }, { 440 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, 441 .name = "sdmmcrab", 442 .sid = TEGRA186_SID_SDMMC4, 443 .regs = { 444 .sid = { 445 .override = 0x318, 446 .security = 0x31c, 447 }, 448 }, 449 }, { 450 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA, 451 .name = "sdmmcwa", 452 .sid = TEGRA186_SID_SDMMC1, 453 .regs = { 454 .sid = { 455 .override = 0x320, 456 .security = 0x324, 457 }, 458 }, 459 }, { 460 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, 461 .name = "sdmmcwaa", 462 .sid = TEGRA186_SID_SDMMC2, 463 .regs = { 464 .sid = { 465 .override = 0x328, 466 .security = 0x32c, 467 }, 468 }, 469 }, { 470 .id = TEGRA186_MEMORY_CLIENT_SDMMCW, 471 .name = "sdmmcw", 472 .sid = TEGRA186_SID_SDMMC3, 473 .regs = { 474 .sid = { 475 .override = 0x330, 476 .security = 0x334, 477 }, 478 }, 479 }, { 480 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, 481 .name = "sdmmcwab", 482 .sid = TEGRA186_SID_SDMMC4, 483 .regs = { 484 .sid = { 485 .override = 0x338, 486 .security = 0x33c, 487 }, 488 }, 489 }, { 490 .id = TEGRA186_MEMORY_CLIENT_VICSRD, 491 .name = "vicsrd", 492 .sid = TEGRA186_SID_VIC, 493 .regs = { 494 .sid = { 495 .override = 0x360, 496 .security = 0x364, 497 }, 498 }, 499 }, { 500 .id = TEGRA186_MEMORY_CLIENT_VICSWR, 501 .name = "vicswr", 502 .sid = TEGRA186_SID_VIC, 503 .regs = { 504 .sid = { 505 .override = 0x368, 506 .security = 0x36c, 507 }, 508 }, 509 }, { 510 .id = TEGRA186_MEMORY_CLIENT_VIW, 511 .name = "viw", 512 .sid = TEGRA186_SID_VI, 513 .regs = { 514 .sid = { 515 .override = 0x390, 516 .security = 0x394, 517 }, 518 }, 519 }, { 520 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD, 521 .name = "nvdecsrd", 522 .sid = TEGRA186_SID_NVDEC, 523 .regs = { 524 .sid = { 525 .override = 0x3c0, 526 .security = 0x3c4, 527 }, 528 }, 529 }, { 530 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR, 531 .name = "nvdecswr", 532 .sid = TEGRA186_SID_NVDEC, 533 .regs = { 534 .sid = { 535 .override = 0x3c8, 536 .security = 0x3cc, 537 }, 538 }, 539 }, { 540 .id = TEGRA186_MEMORY_CLIENT_APER, 541 .name = "aper", 542 .sid = TEGRA186_SID_APE, 543 .regs = { 544 .sid = { 545 .override = 0x3d0, 546 .security = 0x3d4, 547 }, 548 }, 549 }, { 550 .id = TEGRA186_MEMORY_CLIENT_APEW, 551 .name = "apew", 552 .sid = TEGRA186_SID_APE, 553 .regs = { 554 .sid = { 555 .override = 0x3d8, 556 .security = 0x3dc, 557 }, 558 }, 559 }, { 560 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, 561 .name = "nvjpgsrd", 562 .sid = TEGRA186_SID_NVJPG, 563 .regs = { 564 .sid = { 565 .override = 0x3f0, 566 .security = 0x3f4, 567 }, 568 }, 569 }, { 570 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, 571 .name = "nvjpgswr", 572 .sid = TEGRA186_SID_NVJPG, 573 .regs = { 574 .sid = { 575 .override = 0x3f8, 576 .security = 0x3fc, 577 }, 578 }, 579 }, { 580 .id = TEGRA186_MEMORY_CLIENT_SESRD, 581 .name = "sesrd", 582 .sid = TEGRA186_SID_SE, 583 .regs = { 584 .sid = { 585 .override = 0x400, 586 .security = 0x404, 587 }, 588 }, 589 }, { 590 .id = TEGRA186_MEMORY_CLIENT_SESWR, 591 .name = "seswr", 592 .sid = TEGRA186_SID_SE, 593 .regs = { 594 .sid = { 595 .override = 0x408, 596 .security = 0x40c, 597 }, 598 }, 599 }, { 600 .id = TEGRA186_MEMORY_CLIENT_ETRR, 601 .name = "etrr", 602 .sid = TEGRA186_SID_ETR, 603 .regs = { 604 .sid = { 605 .override = 0x420, 606 .security = 0x424, 607 }, 608 }, 609 }, { 610 .id = TEGRA186_MEMORY_CLIENT_ETRW, 611 .name = "etrw", 612 .sid = TEGRA186_SID_ETR, 613 .regs = { 614 .sid = { 615 .override = 0x428, 616 .security = 0x42c, 617 }, 618 }, 619 }, { 620 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB, 621 .name = "tsecsrdb", 622 .sid = TEGRA186_SID_TSECB, 623 .regs = { 624 .sid = { 625 .override = 0x430, 626 .security = 0x434, 627 }, 628 }, 629 }, { 630 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB, 631 .name = "tsecswrb", 632 .sid = TEGRA186_SID_TSECB, 633 .regs = { 634 .sid = { 635 .override = 0x438, 636 .security = 0x43c, 637 }, 638 }, 639 }, { 640 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2, 641 .name = "gpusrd2", 642 .sid = TEGRA186_SID_GPU, 643 .regs = { 644 .sid = { 645 .override = 0x440, 646 .security = 0x444, 647 }, 648 }, 649 }, { 650 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2, 651 .name = "gpuswr2", 652 .sid = TEGRA186_SID_GPU, 653 .regs = { 654 .sid = { 655 .override = 0x448, 656 .security = 0x44c, 657 }, 658 }, 659 }, { 660 .id = TEGRA186_MEMORY_CLIENT_AXISR, 661 .name = "axisr", 662 .sid = TEGRA186_SID_GPCDMA_0, 663 .regs = { 664 .sid = { 665 .override = 0x460, 666 .security = 0x464, 667 }, 668 }, 669 }, { 670 .id = TEGRA186_MEMORY_CLIENT_AXISW, 671 .name = "axisw", 672 .sid = TEGRA186_SID_GPCDMA_0, 673 .regs = { 674 .sid = { 675 .override = 0x468, 676 .security = 0x46c, 677 }, 678 }, 679 }, { 680 .id = TEGRA186_MEMORY_CLIENT_EQOSR, 681 .name = "eqosr", 682 .sid = TEGRA186_SID_EQOS, 683 .regs = { 684 .sid = { 685 .override = 0x470, 686 .security = 0x474, 687 }, 688 }, 689 }, { 690 .id = TEGRA186_MEMORY_CLIENT_EQOSW, 691 .name = "eqosw", 692 .sid = TEGRA186_SID_EQOS, 693 .regs = { 694 .sid = { 695 .override = 0x478, 696 .security = 0x47c, 697 }, 698 }, 699 }, { 700 .id = TEGRA186_MEMORY_CLIENT_UFSHCR, 701 .name = "ufshcr", 702 .sid = TEGRA186_SID_UFSHC, 703 .regs = { 704 .sid = { 705 .override = 0x480, 706 .security = 0x484, 707 }, 708 }, 709 }, { 710 .id = TEGRA186_MEMORY_CLIENT_UFSHCW, 711 .name = "ufshcw", 712 .sid = TEGRA186_SID_UFSHC, 713 .regs = { 714 .sid = { 715 .override = 0x488, 716 .security = 0x48c, 717 }, 718 }, 719 }, { 720 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, 721 .name = "nvdisplayr", 722 .sid = TEGRA186_SID_NVDISPLAY, 723 .regs = { 724 .sid = { 725 .override = 0x490, 726 .security = 0x494, 727 }, 728 }, 729 }, { 730 .id = TEGRA186_MEMORY_CLIENT_BPMPR, 731 .name = "bpmpr", 732 .sid = TEGRA186_SID_BPMP, 733 .regs = { 734 .sid = { 735 .override = 0x498, 736 .security = 0x49c, 737 }, 738 }, 739 }, { 740 .id = TEGRA186_MEMORY_CLIENT_BPMPW, 741 .name = "bpmpw", 742 .sid = TEGRA186_SID_BPMP, 743 .regs = { 744 .sid = { 745 .override = 0x4a0, 746 .security = 0x4a4, 747 }, 748 }, 749 }, { 750 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, 751 .name = "bpmpdmar", 752 .sid = TEGRA186_SID_BPMP, 753 .regs = { 754 .sid = { 755 .override = 0x4a8, 756 .security = 0x4ac, 757 }, 758 }, 759 }, { 760 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, 761 .name = "bpmpdmaw", 762 .sid = TEGRA186_SID_BPMP, 763 .regs = { 764 .sid = { 765 .override = 0x4b0, 766 .security = 0x4b4, 767 }, 768 }, 769 }, { 770 .id = TEGRA186_MEMORY_CLIENT_AONR, 771 .name = "aonr", 772 .sid = TEGRA186_SID_AON, 773 .regs = { 774 .sid = { 775 .override = 0x4b8, 776 .security = 0x4bc, 777 }, 778 }, 779 }, { 780 .id = TEGRA186_MEMORY_CLIENT_AONW, 781 .name = "aonw", 782 .sid = TEGRA186_SID_AON, 783 .regs = { 784 .sid = { 785 .override = 0x4c0, 786 .security = 0x4c4, 787 }, 788 }, 789 }, { 790 .id = TEGRA186_MEMORY_CLIENT_AONDMAR, 791 .name = "aondmar", 792 .sid = TEGRA186_SID_AON, 793 .regs = { 794 .sid = { 795 .override = 0x4c8, 796 .security = 0x4cc, 797 }, 798 }, 799 }, { 800 .id = TEGRA186_MEMORY_CLIENT_AONDMAW, 801 .name = "aondmaw", 802 .sid = TEGRA186_SID_AON, 803 .regs = { 804 .sid = { 805 .override = 0x4d0, 806 .security = 0x4d4, 807 }, 808 }, 809 }, { 810 .id = TEGRA186_MEMORY_CLIENT_SCER, 811 .name = "scer", 812 .sid = TEGRA186_SID_SCE, 813 .regs = { 814 .sid = { 815 .override = 0x4d8, 816 .security = 0x4dc, 817 }, 818 }, 819 }, { 820 .id = TEGRA186_MEMORY_CLIENT_SCEW, 821 .name = "scew", 822 .sid = TEGRA186_SID_SCE, 823 .regs = { 824 .sid = { 825 .override = 0x4e0, 826 .security = 0x4e4, 827 }, 828 }, 829 }, { 830 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR, 831 .name = "scedmar", 832 .sid = TEGRA186_SID_SCE, 833 .regs = { 834 .sid = { 835 .override = 0x4e8, 836 .security = 0x4ec, 837 }, 838 }, 839 }, { 840 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW, 841 .name = "scedmaw", 842 .sid = TEGRA186_SID_SCE, 843 .regs = { 844 .sid = { 845 .override = 0x4f0, 846 .security = 0x4f4, 847 }, 848 }, 849 }, { 850 .id = TEGRA186_MEMORY_CLIENT_APEDMAR, 851 .name = "apedmar", 852 .sid = TEGRA186_SID_APE, 853 .regs = { 854 .sid = { 855 .override = 0x4f8, 856 .security = 0x4fc, 857 }, 858 }, 859 }, { 860 .id = TEGRA186_MEMORY_CLIENT_APEDMAW, 861 .name = "apedmaw", 862 .sid = TEGRA186_SID_APE, 863 .regs = { 864 .sid = { 865 .override = 0x500, 866 .security = 0x504, 867 }, 868 }, 869 }, { 870 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, 871 .name = "nvdisplayr1", 872 .sid = TEGRA186_SID_NVDISPLAY, 873 .regs = { 874 .sid = { 875 .override = 0x508, 876 .security = 0x50c, 877 }, 878 }, 879 }, { 880 .id = TEGRA186_MEMORY_CLIENT_VICSRD1, 881 .name = "vicsrd1", 882 .sid = TEGRA186_SID_VIC, 883 .regs = { 884 .sid = { 885 .override = 0x510, 886 .security = 0x514, 887 }, 888 }, 889 }, { 890 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, 891 .name = "nvdecsrd1", 892 .sid = TEGRA186_SID_NVDEC, 893 .regs = { 894 .sid = { 895 .override = 0x518, 896 .security = 0x51c, 897 }, 898 }, 899 }, 900 }; 901 902 static const struct tegra_mc_intmask tegra186_mc_intmasks[] = { 903 { 904 .reg = MC_INTMASK, 905 .mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 906 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 907 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, 908 }, 909 }; 910 911 const struct tegra_mc_soc tegra186_mc_soc = { 912 .num_clients = ARRAY_SIZE(tegra186_mc_clients), 913 .clients = tegra186_mc_clients, 914 .num_address_bits = 40, 915 .num_channels = 4, 916 .client_id_mask = 0xff, 917 .intmasks = tegra186_mc_intmasks, 918 .num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks), 919 .ops = &tegra186_mc_ops, 920 .ch_intmask = 0x0000000f, 921 .global_intstatus_channel_shift = 0, 922 .regs = &tegra20_mc_regs, 923 .handle_irq = tegra30_mc_irq_handlers, 924 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 925 .mc_addr_hi_mask = 0x3, 926 .mc_err_status_type_mask = (0x7 << 28), 927 }; 928 #endif 929