1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017-2021 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/iommu.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/platform_device.h> 13 14 #include <soc/tegra/mc.h> 15 16 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 17 #include <dt-bindings/memory/tegra186-mc.h> 18 #endif 19 20 #include "mc.h" 21 22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) 23 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) 24 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) 25 26 static int tegra186_mc_probe(struct tegra_mc *mc) 27 { 28 struct platform_device *pdev = to_platform_device(mc->dev); 29 unsigned int i; 30 char name[8]; 31 int err; 32 33 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); 34 if (IS_ERR(mc->bcast_ch_regs)) { 35 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { 36 dev_warn(&pdev->dev, 37 "Broadcast channel is missing, please update your device-tree\n"); 38 mc->bcast_ch_regs = NULL; 39 goto populate; 40 } 41 42 return PTR_ERR(mc->bcast_ch_regs); 43 } 44 45 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs), 46 GFP_KERNEL); 47 if (!mc->ch_regs) 48 return -ENOMEM; 49 50 for (i = 0; i < mc->soc->num_channels; i++) { 51 snprintf(name, sizeof(name), "ch%u", i); 52 53 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name); 54 if (IS_ERR(mc->ch_regs[i])) 55 return PTR_ERR(mc->ch_regs[i]); 56 } 57 58 populate: 59 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); 60 if (err < 0) 61 return err; 62 63 return 0; 64 } 65 66 static void tegra186_mc_remove(struct tegra_mc *mc) 67 { 68 of_platform_depopulate(mc->dev); 69 } 70 71 #if IS_ENABLED(CONFIG_IOMMU_API) 72 static void tegra186_mc_client_sid_override(struct tegra_mc *mc, 73 const struct tegra_mc_client *client, 74 unsigned int sid) 75 { 76 u32 value, old; 77 78 if (client->regs.sid.security == 0 && client->regs.sid.override == 0) 79 return; 80 81 value = readl(mc->regs + client->regs.sid.security); 82 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { 83 /* 84 * If the secure firmware has locked this down the override 85 * for this memory client, there's nothing we can do here. 86 */ 87 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) 88 return; 89 90 /* 91 * Otherwise, try to set the override itself. Typically the 92 * secure firmware will never have set this configuration. 93 * Instead, it will either have disabled write access to 94 * this field, or it will already have set an explicit 95 * override itself. 96 */ 97 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); 98 99 value |= MC_SID_STREAMID_SECURITY_OVERRIDE; 100 writel(value, mc->regs + client->regs.sid.security); 101 } 102 103 value = readl(mc->regs + client->regs.sid.override); 104 old = value & MC_SID_STREAMID_OVERRIDE_MASK; 105 106 if (old != sid) { 107 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, 108 client->name, sid); 109 writel(sid, mc->regs + client->regs.sid.override); 110 } 111 } 112 #endif 113 114 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) 115 { 116 #if IS_ENABLED(CONFIG_IOMMU_API) 117 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev); 118 struct of_phandle_args args; 119 unsigned int i, index = 0; 120 121 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", 122 index, &args)) { 123 if (args.np == mc->dev->of_node && args.args_count != 0) { 124 for (i = 0; i < mc->soc->num_clients; i++) { 125 const struct tegra_mc_client *client = &mc->soc->clients[i]; 126 127 if (client->id == args.args[0]) { 128 u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK; 129 130 tegra186_mc_client_sid_override(mc, client, sid); 131 } 132 } 133 } 134 135 index++; 136 } 137 #endif 138 139 return 0; 140 } 141 142 static int tegra186_mc_resume(struct tegra_mc *mc) 143 { 144 #if IS_ENABLED(CONFIG_IOMMU_API) 145 unsigned int i; 146 147 for (i = 0; i < mc->soc->num_clients; i++) { 148 const struct tegra_mc_client *client = &mc->soc->clients[i]; 149 150 tegra186_mc_client_sid_override(mc, client, client->sid); 151 } 152 #endif 153 154 return 0; 155 } 156 157 const struct tegra_mc_ops tegra186_mc_ops = { 158 .probe = tegra186_mc_probe, 159 .remove = tegra186_mc_remove, 160 .resume = tegra186_mc_resume, 161 .probe_device = tegra186_mc_probe_device, 162 .handle_irq = tegra30_mc_handle_irq, 163 }; 164 165 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 166 static const struct tegra_mc_client tegra186_mc_clients[] = { 167 { 168 .id = TEGRA186_MEMORY_CLIENT_PTCR, 169 .name = "ptcr", 170 .sid = TEGRA186_SID_PASSTHROUGH, 171 .regs = { 172 .sid = { 173 .override = 0x000, 174 .security = 0x004, 175 }, 176 }, 177 }, { 178 .id = TEGRA186_MEMORY_CLIENT_AFIR, 179 .name = "afir", 180 .sid = TEGRA186_SID_AFI, 181 .regs = { 182 .sid = { 183 .override = 0x070, 184 .security = 0x074, 185 }, 186 }, 187 }, { 188 .id = TEGRA186_MEMORY_CLIENT_HDAR, 189 .name = "hdar", 190 .sid = TEGRA186_SID_HDA, 191 .regs = { 192 .sid = { 193 .override = 0x0a8, 194 .security = 0x0ac, 195 }, 196 }, 197 }, { 198 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, 199 .name = "host1xdmar", 200 .sid = TEGRA186_SID_HOST1X, 201 .regs = { 202 .sid = { 203 .override = 0x0b0, 204 .security = 0x0b4, 205 }, 206 }, 207 }, { 208 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD, 209 .name = "nvencsrd", 210 .sid = TEGRA186_SID_NVENC, 211 .regs = { 212 .sid = { 213 .override = 0x0e0, 214 .security = 0x0e4, 215 }, 216 }, 217 }, { 218 .id = TEGRA186_MEMORY_CLIENT_SATAR, 219 .name = "satar", 220 .sid = TEGRA186_SID_SATA, 221 .regs = { 222 .sid = { 223 .override = 0x0f8, 224 .security = 0x0fc, 225 }, 226 }, 227 }, { 228 .id = TEGRA186_MEMORY_CLIENT_MPCORER, 229 .name = "mpcorer", 230 .sid = TEGRA186_SID_PASSTHROUGH, 231 .regs = { 232 .sid = { 233 .override = 0x138, 234 .security = 0x13c, 235 }, 236 }, 237 }, { 238 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR, 239 .name = "nvencswr", 240 .sid = TEGRA186_SID_NVENC, 241 .regs = { 242 .sid = { 243 .override = 0x158, 244 .security = 0x15c, 245 }, 246 }, 247 }, { 248 .id = TEGRA186_MEMORY_CLIENT_AFIW, 249 .name = "afiw", 250 .sid = TEGRA186_SID_AFI, 251 .regs = { 252 .sid = { 253 .override = 0x188, 254 .security = 0x18c, 255 }, 256 }, 257 }, { 258 .id = TEGRA186_MEMORY_CLIENT_HDAW, 259 .name = "hdaw", 260 .sid = TEGRA186_SID_HDA, 261 .regs = { 262 .sid = { 263 .override = 0x1a8, 264 .security = 0x1ac, 265 }, 266 }, 267 }, { 268 .id = TEGRA186_MEMORY_CLIENT_MPCOREW, 269 .name = "mpcorew", 270 .sid = TEGRA186_SID_PASSTHROUGH, 271 .regs = { 272 .sid = { 273 .override = 0x1c8, 274 .security = 0x1cc, 275 }, 276 }, 277 }, { 278 .id = TEGRA186_MEMORY_CLIENT_SATAW, 279 .name = "sataw", 280 .sid = TEGRA186_SID_SATA, 281 .regs = { 282 .sid = { 283 .override = 0x1e8, 284 .security = 0x1ec, 285 }, 286 }, 287 }, { 288 .id = TEGRA186_MEMORY_CLIENT_ISPRA, 289 .name = "ispra", 290 .sid = TEGRA186_SID_ISP, 291 .regs = { 292 .sid = { 293 .override = 0x220, 294 .security = 0x224, 295 }, 296 }, 297 }, { 298 .id = TEGRA186_MEMORY_CLIENT_ISPWA, 299 .name = "ispwa", 300 .sid = TEGRA186_SID_ISP, 301 .regs = { 302 .sid = { 303 .override = 0x230, 304 .security = 0x234, 305 }, 306 }, 307 }, { 308 .id = TEGRA186_MEMORY_CLIENT_ISPWB, 309 .name = "ispwb", 310 .sid = TEGRA186_SID_ISP, 311 .regs = { 312 .sid = { 313 .override = 0x238, 314 .security = 0x23c, 315 }, 316 }, 317 }, { 318 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, 319 .name = "xusb_hostr", 320 .sid = TEGRA186_SID_XUSB_HOST, 321 .regs = { 322 .sid = { 323 .override = 0x250, 324 .security = 0x254, 325 }, 326 }, 327 }, { 328 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, 329 .name = "xusb_hostw", 330 .sid = TEGRA186_SID_XUSB_HOST, 331 .regs = { 332 .sid = { 333 .override = 0x258, 334 .security = 0x25c, 335 }, 336 }, 337 }, { 338 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, 339 .name = "xusb_devr", 340 .sid = TEGRA186_SID_XUSB_DEV, 341 .regs = { 342 .sid = { 343 .override = 0x260, 344 .security = 0x264, 345 }, 346 }, 347 }, { 348 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, 349 .name = "xusb_devw", 350 .sid = TEGRA186_SID_XUSB_DEV, 351 .regs = { 352 .sid = { 353 .override = 0x268, 354 .security = 0x26c, 355 }, 356 }, 357 }, { 358 .id = TEGRA186_MEMORY_CLIENT_TSECSRD, 359 .name = "tsecsrd", 360 .sid = TEGRA186_SID_TSEC, 361 .regs = { 362 .sid = { 363 .override = 0x2a0, 364 .security = 0x2a4, 365 }, 366 }, 367 }, { 368 .id = TEGRA186_MEMORY_CLIENT_TSECSWR, 369 .name = "tsecswr", 370 .sid = TEGRA186_SID_TSEC, 371 .regs = { 372 .sid = { 373 .override = 0x2a8, 374 .security = 0x2ac, 375 }, 376 }, 377 }, { 378 .id = TEGRA186_MEMORY_CLIENT_GPUSRD, 379 .name = "gpusrd", 380 .sid = TEGRA186_SID_GPU, 381 .regs = { 382 .sid = { 383 .override = 0x2c0, 384 .security = 0x2c4, 385 }, 386 }, 387 }, { 388 .id = TEGRA186_MEMORY_CLIENT_GPUSWR, 389 .name = "gpuswr", 390 .sid = TEGRA186_SID_GPU, 391 .regs = { 392 .sid = { 393 .override = 0x2c8, 394 .security = 0x2cc, 395 }, 396 }, 397 }, { 398 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA, 399 .name = "sdmmcra", 400 .sid = TEGRA186_SID_SDMMC1, 401 .regs = { 402 .sid = { 403 .override = 0x300, 404 .security = 0x304, 405 }, 406 }, 407 }, { 408 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, 409 .name = "sdmmcraa", 410 .sid = TEGRA186_SID_SDMMC2, 411 .regs = { 412 .sid = { 413 .override = 0x308, 414 .security = 0x30c, 415 }, 416 }, 417 }, { 418 .id = TEGRA186_MEMORY_CLIENT_SDMMCR, 419 .name = "sdmmcr", 420 .sid = TEGRA186_SID_SDMMC3, 421 .regs = { 422 .sid = { 423 .override = 0x310, 424 .security = 0x314, 425 }, 426 }, 427 }, { 428 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, 429 .name = "sdmmcrab", 430 .sid = TEGRA186_SID_SDMMC4, 431 .regs = { 432 .sid = { 433 .override = 0x318, 434 .security = 0x31c, 435 }, 436 }, 437 }, { 438 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA, 439 .name = "sdmmcwa", 440 .sid = TEGRA186_SID_SDMMC1, 441 .regs = { 442 .sid = { 443 .override = 0x320, 444 .security = 0x324, 445 }, 446 }, 447 }, { 448 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, 449 .name = "sdmmcwaa", 450 .sid = TEGRA186_SID_SDMMC2, 451 .regs = { 452 .sid = { 453 .override = 0x328, 454 .security = 0x32c, 455 }, 456 }, 457 }, { 458 .id = TEGRA186_MEMORY_CLIENT_SDMMCW, 459 .name = "sdmmcw", 460 .sid = TEGRA186_SID_SDMMC3, 461 .regs = { 462 .sid = { 463 .override = 0x330, 464 .security = 0x334, 465 }, 466 }, 467 }, { 468 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, 469 .name = "sdmmcwab", 470 .sid = TEGRA186_SID_SDMMC4, 471 .regs = { 472 .sid = { 473 .override = 0x338, 474 .security = 0x33c, 475 }, 476 }, 477 }, { 478 .id = TEGRA186_MEMORY_CLIENT_VICSRD, 479 .name = "vicsrd", 480 .sid = TEGRA186_SID_VIC, 481 .regs = { 482 .sid = { 483 .override = 0x360, 484 .security = 0x364, 485 }, 486 }, 487 }, { 488 .id = TEGRA186_MEMORY_CLIENT_VICSWR, 489 .name = "vicswr", 490 .sid = TEGRA186_SID_VIC, 491 .regs = { 492 .sid = { 493 .override = 0x368, 494 .security = 0x36c, 495 }, 496 }, 497 }, { 498 .id = TEGRA186_MEMORY_CLIENT_VIW, 499 .name = "viw", 500 .sid = TEGRA186_SID_VI, 501 .regs = { 502 .sid = { 503 .override = 0x390, 504 .security = 0x394, 505 }, 506 }, 507 }, { 508 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD, 509 .name = "nvdecsrd", 510 .sid = TEGRA186_SID_NVDEC, 511 .regs = { 512 .sid = { 513 .override = 0x3c0, 514 .security = 0x3c4, 515 }, 516 }, 517 }, { 518 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR, 519 .name = "nvdecswr", 520 .sid = TEGRA186_SID_NVDEC, 521 .regs = { 522 .sid = { 523 .override = 0x3c8, 524 .security = 0x3cc, 525 }, 526 }, 527 }, { 528 .id = TEGRA186_MEMORY_CLIENT_APER, 529 .name = "aper", 530 .sid = TEGRA186_SID_APE, 531 .regs = { 532 .sid = { 533 .override = 0x3d0, 534 .security = 0x3d4, 535 }, 536 }, 537 }, { 538 .id = TEGRA186_MEMORY_CLIENT_APEW, 539 .name = "apew", 540 .sid = TEGRA186_SID_APE, 541 .regs = { 542 .sid = { 543 .override = 0x3d8, 544 .security = 0x3dc, 545 }, 546 }, 547 }, { 548 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, 549 .name = "nvjpgsrd", 550 .sid = TEGRA186_SID_NVJPG, 551 .regs = { 552 .sid = { 553 .override = 0x3f0, 554 .security = 0x3f4, 555 }, 556 }, 557 }, { 558 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, 559 .name = "nvjpgswr", 560 .sid = TEGRA186_SID_NVJPG, 561 .regs = { 562 .sid = { 563 .override = 0x3f8, 564 .security = 0x3fc, 565 }, 566 }, 567 }, { 568 .id = TEGRA186_MEMORY_CLIENT_SESRD, 569 .name = "sesrd", 570 .sid = TEGRA186_SID_SE, 571 .regs = { 572 .sid = { 573 .override = 0x400, 574 .security = 0x404, 575 }, 576 }, 577 }, { 578 .id = TEGRA186_MEMORY_CLIENT_SESWR, 579 .name = "seswr", 580 .sid = TEGRA186_SID_SE, 581 .regs = { 582 .sid = { 583 .override = 0x408, 584 .security = 0x40c, 585 }, 586 }, 587 }, { 588 .id = TEGRA186_MEMORY_CLIENT_ETRR, 589 .name = "etrr", 590 .sid = TEGRA186_SID_ETR, 591 .regs = { 592 .sid = { 593 .override = 0x420, 594 .security = 0x424, 595 }, 596 }, 597 }, { 598 .id = TEGRA186_MEMORY_CLIENT_ETRW, 599 .name = "etrw", 600 .sid = TEGRA186_SID_ETR, 601 .regs = { 602 .sid = { 603 .override = 0x428, 604 .security = 0x42c, 605 }, 606 }, 607 }, { 608 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB, 609 .name = "tsecsrdb", 610 .sid = TEGRA186_SID_TSECB, 611 .regs = { 612 .sid = { 613 .override = 0x430, 614 .security = 0x434, 615 }, 616 }, 617 }, { 618 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB, 619 .name = "tsecswrb", 620 .sid = TEGRA186_SID_TSECB, 621 .regs = { 622 .sid = { 623 .override = 0x438, 624 .security = 0x43c, 625 }, 626 }, 627 }, { 628 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2, 629 .name = "gpusrd2", 630 .sid = TEGRA186_SID_GPU, 631 .regs = { 632 .sid = { 633 .override = 0x440, 634 .security = 0x444, 635 }, 636 }, 637 }, { 638 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2, 639 .name = "gpuswr2", 640 .sid = TEGRA186_SID_GPU, 641 .regs = { 642 .sid = { 643 .override = 0x448, 644 .security = 0x44c, 645 }, 646 }, 647 }, { 648 .id = TEGRA186_MEMORY_CLIENT_AXISR, 649 .name = "axisr", 650 .sid = TEGRA186_SID_GPCDMA_0, 651 .regs = { 652 .sid = { 653 .override = 0x460, 654 .security = 0x464, 655 }, 656 }, 657 }, { 658 .id = TEGRA186_MEMORY_CLIENT_AXISW, 659 .name = "axisw", 660 .sid = TEGRA186_SID_GPCDMA_0, 661 .regs = { 662 .sid = { 663 .override = 0x468, 664 .security = 0x46c, 665 }, 666 }, 667 }, { 668 .id = TEGRA186_MEMORY_CLIENT_EQOSR, 669 .name = "eqosr", 670 .sid = TEGRA186_SID_EQOS, 671 .regs = { 672 .sid = { 673 .override = 0x470, 674 .security = 0x474, 675 }, 676 }, 677 }, { 678 .id = TEGRA186_MEMORY_CLIENT_EQOSW, 679 .name = "eqosw", 680 .sid = TEGRA186_SID_EQOS, 681 .regs = { 682 .sid = { 683 .override = 0x478, 684 .security = 0x47c, 685 }, 686 }, 687 }, { 688 .id = TEGRA186_MEMORY_CLIENT_UFSHCR, 689 .name = "ufshcr", 690 .sid = TEGRA186_SID_UFSHC, 691 .regs = { 692 .sid = { 693 .override = 0x480, 694 .security = 0x484, 695 }, 696 }, 697 }, { 698 .id = TEGRA186_MEMORY_CLIENT_UFSHCW, 699 .name = "ufshcw", 700 .sid = TEGRA186_SID_UFSHC, 701 .regs = { 702 .sid = { 703 .override = 0x488, 704 .security = 0x48c, 705 }, 706 }, 707 }, { 708 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, 709 .name = "nvdisplayr", 710 .sid = TEGRA186_SID_NVDISPLAY, 711 .regs = { 712 .sid = { 713 .override = 0x490, 714 .security = 0x494, 715 }, 716 }, 717 }, { 718 .id = TEGRA186_MEMORY_CLIENT_BPMPR, 719 .name = "bpmpr", 720 .sid = TEGRA186_SID_BPMP, 721 .regs = { 722 .sid = { 723 .override = 0x498, 724 .security = 0x49c, 725 }, 726 }, 727 }, { 728 .id = TEGRA186_MEMORY_CLIENT_BPMPW, 729 .name = "bpmpw", 730 .sid = TEGRA186_SID_BPMP, 731 .regs = { 732 .sid = { 733 .override = 0x4a0, 734 .security = 0x4a4, 735 }, 736 }, 737 }, { 738 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, 739 .name = "bpmpdmar", 740 .sid = TEGRA186_SID_BPMP, 741 .regs = { 742 .sid = { 743 .override = 0x4a8, 744 .security = 0x4ac, 745 }, 746 }, 747 }, { 748 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, 749 .name = "bpmpdmaw", 750 .sid = TEGRA186_SID_BPMP, 751 .regs = { 752 .sid = { 753 .override = 0x4b0, 754 .security = 0x4b4, 755 }, 756 }, 757 }, { 758 .id = TEGRA186_MEMORY_CLIENT_AONR, 759 .name = "aonr", 760 .sid = TEGRA186_SID_AON, 761 .regs = { 762 .sid = { 763 .override = 0x4b8, 764 .security = 0x4bc, 765 }, 766 }, 767 }, { 768 .id = TEGRA186_MEMORY_CLIENT_AONW, 769 .name = "aonw", 770 .sid = TEGRA186_SID_AON, 771 .regs = { 772 .sid = { 773 .override = 0x4c0, 774 .security = 0x4c4, 775 }, 776 }, 777 }, { 778 .id = TEGRA186_MEMORY_CLIENT_AONDMAR, 779 .name = "aondmar", 780 .sid = TEGRA186_SID_AON, 781 .regs = { 782 .sid = { 783 .override = 0x4c8, 784 .security = 0x4cc, 785 }, 786 }, 787 }, { 788 .id = TEGRA186_MEMORY_CLIENT_AONDMAW, 789 .name = "aondmaw", 790 .sid = TEGRA186_SID_AON, 791 .regs = { 792 .sid = { 793 .override = 0x4d0, 794 .security = 0x4d4, 795 }, 796 }, 797 }, { 798 .id = TEGRA186_MEMORY_CLIENT_SCER, 799 .name = "scer", 800 .sid = TEGRA186_SID_SCE, 801 .regs = { 802 .sid = { 803 .override = 0x4d8, 804 .security = 0x4dc, 805 }, 806 }, 807 }, { 808 .id = TEGRA186_MEMORY_CLIENT_SCEW, 809 .name = "scew", 810 .sid = TEGRA186_SID_SCE, 811 .regs = { 812 .sid = { 813 .override = 0x4e0, 814 .security = 0x4e4, 815 }, 816 }, 817 }, { 818 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR, 819 .name = "scedmar", 820 .sid = TEGRA186_SID_SCE, 821 .regs = { 822 .sid = { 823 .override = 0x4e8, 824 .security = 0x4ec, 825 }, 826 }, 827 }, { 828 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW, 829 .name = "scedmaw", 830 .sid = TEGRA186_SID_SCE, 831 .regs = { 832 .sid = { 833 .override = 0x4f0, 834 .security = 0x4f4, 835 }, 836 }, 837 }, { 838 .id = TEGRA186_MEMORY_CLIENT_APEDMAR, 839 .name = "apedmar", 840 .sid = TEGRA186_SID_APE, 841 .regs = { 842 .sid = { 843 .override = 0x4f8, 844 .security = 0x4fc, 845 }, 846 }, 847 }, { 848 .id = TEGRA186_MEMORY_CLIENT_APEDMAW, 849 .name = "apedmaw", 850 .sid = TEGRA186_SID_APE, 851 .regs = { 852 .sid = { 853 .override = 0x500, 854 .security = 0x504, 855 }, 856 }, 857 }, { 858 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, 859 .name = "nvdisplayr1", 860 .sid = TEGRA186_SID_NVDISPLAY, 861 .regs = { 862 .sid = { 863 .override = 0x508, 864 .security = 0x50c, 865 }, 866 }, 867 }, { 868 .id = TEGRA186_MEMORY_CLIENT_VICSRD1, 869 .name = "vicsrd1", 870 .sid = TEGRA186_SID_VIC, 871 .regs = { 872 .sid = { 873 .override = 0x510, 874 .security = 0x514, 875 }, 876 }, 877 }, { 878 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, 879 .name = "nvdecsrd1", 880 .sid = TEGRA186_SID_NVDEC, 881 .regs = { 882 .sid = { 883 .override = 0x518, 884 .security = 0x51c, 885 }, 886 }, 887 }, 888 }; 889 890 const struct tegra_mc_soc tegra186_mc_soc = { 891 .num_clients = ARRAY_SIZE(tegra186_mc_clients), 892 .clients = tegra186_mc_clients, 893 .num_address_bits = 40, 894 .num_channels = 4, 895 .client_id_mask = 0xff, 896 .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 897 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 898 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, 899 .ops = &tegra186_mc_ops, 900 .ch_intmask = 0x0000000f, 901 .global_intstatus_channel_shift = 0, 902 }; 903 #endif 904