1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2017-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/io.h> 7 #include <linux/iommu.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 13 #include <soc/tegra/mc.h> 14 15 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 16 #include <dt-bindings/memory/tegra186-mc.h> 17 #endif 18 19 #include "mc.h" 20 21 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0) 22 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16) 23 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8) 24 25 static int tegra186_mc_probe(struct tegra_mc *mc) 26 { 27 struct platform_device *pdev = to_platform_device(mc->dev); 28 struct resource *res; 29 unsigned int i; 30 char name[8]; 31 int err; 32 33 /* 34 * From Tegra264, the SID region is not present in MC node and BROADCAST is first. 35 * The common function 'tegra_mc_probe()' already maps first region entry from DT. 36 * Check if the SID region is present in DT then map BROADCAST. Otherwise, consider 37 * the first entry mapped in mc probe as the BROADCAST region. This is done to avoid 38 * mapping the region twice when SID is not present and keep backward compatibility. 39 */ 40 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid"); 41 if (res) 42 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast"); 43 else 44 mc->bcast_ch_regs = mc->regs; 45 46 if (IS_ERR(mc->bcast_ch_regs)) { 47 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) { 48 dev_warn(&pdev->dev, 49 "Broadcast channel is missing, please update your device-tree\n"); 50 mc->bcast_ch_regs = NULL; 51 goto populate; 52 } 53 54 return PTR_ERR(mc->bcast_ch_regs); 55 } 56 57 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs), 58 GFP_KERNEL); 59 if (!mc->ch_regs) 60 return -ENOMEM; 61 62 for (i = 0; i < mc->soc->num_channels; i++) { 63 snprintf(name, sizeof(name), "ch%u", i); 64 65 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name); 66 if (IS_ERR(mc->ch_regs[i])) 67 return PTR_ERR(mc->ch_regs[i]); 68 } 69 70 populate: 71 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev); 72 if (err < 0) 73 return err; 74 75 return 0; 76 } 77 78 static void tegra186_mc_remove(struct tegra_mc *mc) 79 { 80 of_platform_depopulate(mc->dev); 81 } 82 83 #if IS_ENABLED(CONFIG_IOMMU_API) 84 static void tegra186_mc_client_sid_override(struct tegra_mc *mc, 85 const struct tegra_mc_client *client, 86 unsigned int sid) 87 { 88 u32 value, old; 89 90 if (client->regs.sid.security == 0 && client->regs.sid.override == 0) 91 return; 92 93 value = readl(mc->regs + client->regs.sid.security); 94 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) { 95 /* 96 * If the secure firmware has locked this down the override 97 * for this memory client, there's nothing we can do here. 98 */ 99 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED) 100 return; 101 102 /* 103 * Otherwise, try to set the override itself. Typically the 104 * secure firmware will never have set this configuration. 105 * Instead, it will either have disabled write access to 106 * this field, or it will already have set an explicit 107 * override itself. 108 */ 109 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0); 110 111 value |= MC_SID_STREAMID_SECURITY_OVERRIDE; 112 writel(value, mc->regs + client->regs.sid.security); 113 } 114 115 value = readl(mc->regs + client->regs.sid.override); 116 old = value & MC_SID_STREAMID_OVERRIDE_MASK; 117 118 if (old != sid) { 119 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old, 120 client->name, sid); 121 writel(sid, mc->regs + client->regs.sid.override); 122 } 123 } 124 #endif 125 126 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev) 127 { 128 #if IS_ENABLED(CONFIG_IOMMU_API) 129 struct of_phandle_args args; 130 unsigned int i, index = 0; 131 u32 sid; 132 133 if (!tegra_dev_iommu_get_stream_id(dev, &sid)) 134 return 0; 135 136 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells", 137 index, &args)) { 138 if (args.np == mc->dev->of_node && args.args_count != 0) { 139 for (i = 0; i < mc->soc->num_clients; i++) { 140 const struct tegra_mc_client *client = &mc->soc->clients[i]; 141 142 if (client->id == args.args[0]) 143 tegra186_mc_client_sid_override( 144 mc, client, 145 sid & MC_SID_STREAMID_OVERRIDE_MASK); 146 } 147 } 148 149 index++; 150 } 151 #endif 152 153 return 0; 154 } 155 156 static void tegra186_mc_resume(struct tegra_mc *mc) 157 { 158 #if IS_ENABLED(CONFIG_IOMMU_API) 159 unsigned int i; 160 161 for (i = 0; i < mc->soc->num_clients; i++) { 162 const struct tegra_mc_client *client = &mc->soc->clients[i]; 163 164 tegra186_mc_client_sid_override(mc, client, client->sid); 165 } 166 #endif 167 } 168 169 const struct tegra_mc_ops tegra186_mc_ops = { 170 .probe = tegra186_mc_probe, 171 .remove = tegra186_mc_remove, 172 .resume = tegra186_mc_resume, 173 .probe_device = tegra186_mc_probe_device, 174 }; 175 176 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 177 static const struct tegra_mc_client tegra186_mc_clients[] = { 178 { 179 .id = TEGRA186_MEMORY_CLIENT_PTCR, 180 .name = "ptcr", 181 .sid = TEGRA186_SID_PASSTHROUGH, 182 .regs = { 183 .sid = { 184 .override = 0x000, 185 .security = 0x004, 186 }, 187 }, 188 }, { 189 .id = TEGRA186_MEMORY_CLIENT_AFIR, 190 .name = "afir", 191 .sid = TEGRA186_SID_AFI, 192 .regs = { 193 .sid = { 194 .override = 0x070, 195 .security = 0x074, 196 }, 197 }, 198 }, { 199 .id = TEGRA186_MEMORY_CLIENT_HDAR, 200 .name = "hdar", 201 .sid = TEGRA186_SID_HDA, 202 .regs = { 203 .sid = { 204 .override = 0x0a8, 205 .security = 0x0ac, 206 }, 207 }, 208 }, { 209 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR, 210 .name = "host1xdmar", 211 .sid = TEGRA186_SID_HOST1X, 212 .regs = { 213 .sid = { 214 .override = 0x0b0, 215 .security = 0x0b4, 216 }, 217 }, 218 }, { 219 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD, 220 .name = "nvencsrd", 221 .sid = TEGRA186_SID_NVENC, 222 .regs = { 223 .sid = { 224 .override = 0x0e0, 225 .security = 0x0e4, 226 }, 227 }, 228 }, { 229 .id = TEGRA186_MEMORY_CLIENT_SATAR, 230 .name = "satar", 231 .sid = TEGRA186_SID_SATA, 232 .regs = { 233 .sid = { 234 .override = 0x0f8, 235 .security = 0x0fc, 236 }, 237 }, 238 }, { 239 .id = TEGRA186_MEMORY_CLIENT_MPCORER, 240 .name = "mpcorer", 241 .sid = TEGRA186_SID_PASSTHROUGH, 242 .regs = { 243 .sid = { 244 .override = 0x138, 245 .security = 0x13c, 246 }, 247 }, 248 }, { 249 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR, 250 .name = "nvencswr", 251 .sid = TEGRA186_SID_NVENC, 252 .regs = { 253 .sid = { 254 .override = 0x158, 255 .security = 0x15c, 256 }, 257 }, 258 }, { 259 .id = TEGRA186_MEMORY_CLIENT_AFIW, 260 .name = "afiw", 261 .sid = TEGRA186_SID_AFI, 262 .regs = { 263 .sid = { 264 .override = 0x188, 265 .security = 0x18c, 266 }, 267 }, 268 }, { 269 .id = TEGRA186_MEMORY_CLIENT_HDAW, 270 .name = "hdaw", 271 .sid = TEGRA186_SID_HDA, 272 .regs = { 273 .sid = { 274 .override = 0x1a8, 275 .security = 0x1ac, 276 }, 277 }, 278 }, { 279 .id = TEGRA186_MEMORY_CLIENT_MPCOREW, 280 .name = "mpcorew", 281 .sid = TEGRA186_SID_PASSTHROUGH, 282 .regs = { 283 .sid = { 284 .override = 0x1c8, 285 .security = 0x1cc, 286 }, 287 }, 288 }, { 289 .id = TEGRA186_MEMORY_CLIENT_SATAW, 290 .name = "sataw", 291 .sid = TEGRA186_SID_SATA, 292 .regs = { 293 .sid = { 294 .override = 0x1e8, 295 .security = 0x1ec, 296 }, 297 }, 298 }, { 299 .id = TEGRA186_MEMORY_CLIENT_ISPRA, 300 .name = "ispra", 301 .sid = TEGRA186_SID_ISP, 302 .regs = { 303 .sid = { 304 .override = 0x220, 305 .security = 0x224, 306 }, 307 }, 308 }, { 309 .id = TEGRA186_MEMORY_CLIENT_ISPWA, 310 .name = "ispwa", 311 .sid = TEGRA186_SID_ISP, 312 .regs = { 313 .sid = { 314 .override = 0x230, 315 .security = 0x234, 316 }, 317 }, 318 }, { 319 .id = TEGRA186_MEMORY_CLIENT_ISPWB, 320 .name = "ispwb", 321 .sid = TEGRA186_SID_ISP, 322 .regs = { 323 .sid = { 324 .override = 0x238, 325 .security = 0x23c, 326 }, 327 }, 328 }, { 329 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR, 330 .name = "xusb_hostr", 331 .sid = TEGRA186_SID_XUSB_HOST, 332 .regs = { 333 .sid = { 334 .override = 0x250, 335 .security = 0x254, 336 }, 337 }, 338 }, { 339 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW, 340 .name = "xusb_hostw", 341 .sid = TEGRA186_SID_XUSB_HOST, 342 .regs = { 343 .sid = { 344 .override = 0x258, 345 .security = 0x25c, 346 }, 347 }, 348 }, { 349 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR, 350 .name = "xusb_devr", 351 .sid = TEGRA186_SID_XUSB_DEV, 352 .regs = { 353 .sid = { 354 .override = 0x260, 355 .security = 0x264, 356 }, 357 }, 358 }, { 359 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW, 360 .name = "xusb_devw", 361 .sid = TEGRA186_SID_XUSB_DEV, 362 .regs = { 363 .sid = { 364 .override = 0x268, 365 .security = 0x26c, 366 }, 367 }, 368 }, { 369 .id = TEGRA186_MEMORY_CLIENT_TSECSRD, 370 .name = "tsecsrd", 371 .sid = TEGRA186_SID_TSEC, 372 .regs = { 373 .sid = { 374 .override = 0x2a0, 375 .security = 0x2a4, 376 }, 377 }, 378 }, { 379 .id = TEGRA186_MEMORY_CLIENT_TSECSWR, 380 .name = "tsecswr", 381 .sid = TEGRA186_SID_TSEC, 382 .regs = { 383 .sid = { 384 .override = 0x2a8, 385 .security = 0x2ac, 386 }, 387 }, 388 }, { 389 .id = TEGRA186_MEMORY_CLIENT_GPUSRD, 390 .name = "gpusrd", 391 .sid = TEGRA186_SID_GPU, 392 .regs = { 393 .sid = { 394 .override = 0x2c0, 395 .security = 0x2c4, 396 }, 397 }, 398 }, { 399 .id = TEGRA186_MEMORY_CLIENT_GPUSWR, 400 .name = "gpuswr", 401 .sid = TEGRA186_SID_GPU, 402 .regs = { 403 .sid = { 404 .override = 0x2c8, 405 .security = 0x2cc, 406 }, 407 }, 408 }, { 409 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA, 410 .name = "sdmmcra", 411 .sid = TEGRA186_SID_SDMMC1, 412 .regs = { 413 .sid = { 414 .override = 0x300, 415 .security = 0x304, 416 }, 417 }, 418 }, { 419 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA, 420 .name = "sdmmcraa", 421 .sid = TEGRA186_SID_SDMMC2, 422 .regs = { 423 .sid = { 424 .override = 0x308, 425 .security = 0x30c, 426 }, 427 }, 428 }, { 429 .id = TEGRA186_MEMORY_CLIENT_SDMMCR, 430 .name = "sdmmcr", 431 .sid = TEGRA186_SID_SDMMC3, 432 .regs = { 433 .sid = { 434 .override = 0x310, 435 .security = 0x314, 436 }, 437 }, 438 }, { 439 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB, 440 .name = "sdmmcrab", 441 .sid = TEGRA186_SID_SDMMC4, 442 .regs = { 443 .sid = { 444 .override = 0x318, 445 .security = 0x31c, 446 }, 447 }, 448 }, { 449 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA, 450 .name = "sdmmcwa", 451 .sid = TEGRA186_SID_SDMMC1, 452 .regs = { 453 .sid = { 454 .override = 0x320, 455 .security = 0x324, 456 }, 457 }, 458 }, { 459 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA, 460 .name = "sdmmcwaa", 461 .sid = TEGRA186_SID_SDMMC2, 462 .regs = { 463 .sid = { 464 .override = 0x328, 465 .security = 0x32c, 466 }, 467 }, 468 }, { 469 .id = TEGRA186_MEMORY_CLIENT_SDMMCW, 470 .name = "sdmmcw", 471 .sid = TEGRA186_SID_SDMMC3, 472 .regs = { 473 .sid = { 474 .override = 0x330, 475 .security = 0x334, 476 }, 477 }, 478 }, { 479 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB, 480 .name = "sdmmcwab", 481 .sid = TEGRA186_SID_SDMMC4, 482 .regs = { 483 .sid = { 484 .override = 0x338, 485 .security = 0x33c, 486 }, 487 }, 488 }, { 489 .id = TEGRA186_MEMORY_CLIENT_VICSRD, 490 .name = "vicsrd", 491 .sid = TEGRA186_SID_VIC, 492 .regs = { 493 .sid = { 494 .override = 0x360, 495 .security = 0x364, 496 }, 497 }, 498 }, { 499 .id = TEGRA186_MEMORY_CLIENT_VICSWR, 500 .name = "vicswr", 501 .sid = TEGRA186_SID_VIC, 502 .regs = { 503 .sid = { 504 .override = 0x368, 505 .security = 0x36c, 506 }, 507 }, 508 }, { 509 .id = TEGRA186_MEMORY_CLIENT_VIW, 510 .name = "viw", 511 .sid = TEGRA186_SID_VI, 512 .regs = { 513 .sid = { 514 .override = 0x390, 515 .security = 0x394, 516 }, 517 }, 518 }, { 519 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD, 520 .name = "nvdecsrd", 521 .sid = TEGRA186_SID_NVDEC, 522 .regs = { 523 .sid = { 524 .override = 0x3c0, 525 .security = 0x3c4, 526 }, 527 }, 528 }, { 529 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR, 530 .name = "nvdecswr", 531 .sid = TEGRA186_SID_NVDEC, 532 .regs = { 533 .sid = { 534 .override = 0x3c8, 535 .security = 0x3cc, 536 }, 537 }, 538 }, { 539 .id = TEGRA186_MEMORY_CLIENT_APER, 540 .name = "aper", 541 .sid = TEGRA186_SID_APE, 542 .regs = { 543 .sid = { 544 .override = 0x3d0, 545 .security = 0x3d4, 546 }, 547 }, 548 }, { 549 .id = TEGRA186_MEMORY_CLIENT_APEW, 550 .name = "apew", 551 .sid = TEGRA186_SID_APE, 552 .regs = { 553 .sid = { 554 .override = 0x3d8, 555 .security = 0x3dc, 556 }, 557 }, 558 }, { 559 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD, 560 .name = "nvjpgsrd", 561 .sid = TEGRA186_SID_NVJPG, 562 .regs = { 563 .sid = { 564 .override = 0x3f0, 565 .security = 0x3f4, 566 }, 567 }, 568 }, { 569 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR, 570 .name = "nvjpgswr", 571 .sid = TEGRA186_SID_NVJPG, 572 .regs = { 573 .sid = { 574 .override = 0x3f8, 575 .security = 0x3fc, 576 }, 577 }, 578 }, { 579 .id = TEGRA186_MEMORY_CLIENT_SESRD, 580 .name = "sesrd", 581 .sid = TEGRA186_SID_SE, 582 .regs = { 583 .sid = { 584 .override = 0x400, 585 .security = 0x404, 586 }, 587 }, 588 }, { 589 .id = TEGRA186_MEMORY_CLIENT_SESWR, 590 .name = "seswr", 591 .sid = TEGRA186_SID_SE, 592 .regs = { 593 .sid = { 594 .override = 0x408, 595 .security = 0x40c, 596 }, 597 }, 598 }, { 599 .id = TEGRA186_MEMORY_CLIENT_ETRR, 600 .name = "etrr", 601 .sid = TEGRA186_SID_ETR, 602 .regs = { 603 .sid = { 604 .override = 0x420, 605 .security = 0x424, 606 }, 607 }, 608 }, { 609 .id = TEGRA186_MEMORY_CLIENT_ETRW, 610 .name = "etrw", 611 .sid = TEGRA186_SID_ETR, 612 .regs = { 613 .sid = { 614 .override = 0x428, 615 .security = 0x42c, 616 }, 617 }, 618 }, { 619 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB, 620 .name = "tsecsrdb", 621 .sid = TEGRA186_SID_TSECB, 622 .regs = { 623 .sid = { 624 .override = 0x430, 625 .security = 0x434, 626 }, 627 }, 628 }, { 629 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB, 630 .name = "tsecswrb", 631 .sid = TEGRA186_SID_TSECB, 632 .regs = { 633 .sid = { 634 .override = 0x438, 635 .security = 0x43c, 636 }, 637 }, 638 }, { 639 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2, 640 .name = "gpusrd2", 641 .sid = TEGRA186_SID_GPU, 642 .regs = { 643 .sid = { 644 .override = 0x440, 645 .security = 0x444, 646 }, 647 }, 648 }, { 649 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2, 650 .name = "gpuswr2", 651 .sid = TEGRA186_SID_GPU, 652 .regs = { 653 .sid = { 654 .override = 0x448, 655 .security = 0x44c, 656 }, 657 }, 658 }, { 659 .id = TEGRA186_MEMORY_CLIENT_AXISR, 660 .name = "axisr", 661 .sid = TEGRA186_SID_GPCDMA_0, 662 .regs = { 663 .sid = { 664 .override = 0x460, 665 .security = 0x464, 666 }, 667 }, 668 }, { 669 .id = TEGRA186_MEMORY_CLIENT_AXISW, 670 .name = "axisw", 671 .sid = TEGRA186_SID_GPCDMA_0, 672 .regs = { 673 .sid = { 674 .override = 0x468, 675 .security = 0x46c, 676 }, 677 }, 678 }, { 679 .id = TEGRA186_MEMORY_CLIENT_EQOSR, 680 .name = "eqosr", 681 .sid = TEGRA186_SID_EQOS, 682 .regs = { 683 .sid = { 684 .override = 0x470, 685 .security = 0x474, 686 }, 687 }, 688 }, { 689 .id = TEGRA186_MEMORY_CLIENT_EQOSW, 690 .name = "eqosw", 691 .sid = TEGRA186_SID_EQOS, 692 .regs = { 693 .sid = { 694 .override = 0x478, 695 .security = 0x47c, 696 }, 697 }, 698 }, { 699 .id = TEGRA186_MEMORY_CLIENT_UFSHCR, 700 .name = "ufshcr", 701 .sid = TEGRA186_SID_UFSHC, 702 .regs = { 703 .sid = { 704 .override = 0x480, 705 .security = 0x484, 706 }, 707 }, 708 }, { 709 .id = TEGRA186_MEMORY_CLIENT_UFSHCW, 710 .name = "ufshcw", 711 .sid = TEGRA186_SID_UFSHC, 712 .regs = { 713 .sid = { 714 .override = 0x488, 715 .security = 0x48c, 716 }, 717 }, 718 }, { 719 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR, 720 .name = "nvdisplayr", 721 .sid = TEGRA186_SID_NVDISPLAY, 722 .regs = { 723 .sid = { 724 .override = 0x490, 725 .security = 0x494, 726 }, 727 }, 728 }, { 729 .id = TEGRA186_MEMORY_CLIENT_BPMPR, 730 .name = "bpmpr", 731 .sid = TEGRA186_SID_BPMP, 732 .regs = { 733 .sid = { 734 .override = 0x498, 735 .security = 0x49c, 736 }, 737 }, 738 }, { 739 .id = TEGRA186_MEMORY_CLIENT_BPMPW, 740 .name = "bpmpw", 741 .sid = TEGRA186_SID_BPMP, 742 .regs = { 743 .sid = { 744 .override = 0x4a0, 745 .security = 0x4a4, 746 }, 747 }, 748 }, { 749 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR, 750 .name = "bpmpdmar", 751 .sid = TEGRA186_SID_BPMP, 752 .regs = { 753 .sid = { 754 .override = 0x4a8, 755 .security = 0x4ac, 756 }, 757 }, 758 }, { 759 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW, 760 .name = "bpmpdmaw", 761 .sid = TEGRA186_SID_BPMP, 762 .regs = { 763 .sid = { 764 .override = 0x4b0, 765 .security = 0x4b4, 766 }, 767 }, 768 }, { 769 .id = TEGRA186_MEMORY_CLIENT_AONR, 770 .name = "aonr", 771 .sid = TEGRA186_SID_AON, 772 .regs = { 773 .sid = { 774 .override = 0x4b8, 775 .security = 0x4bc, 776 }, 777 }, 778 }, { 779 .id = TEGRA186_MEMORY_CLIENT_AONW, 780 .name = "aonw", 781 .sid = TEGRA186_SID_AON, 782 .regs = { 783 .sid = { 784 .override = 0x4c0, 785 .security = 0x4c4, 786 }, 787 }, 788 }, { 789 .id = TEGRA186_MEMORY_CLIENT_AONDMAR, 790 .name = "aondmar", 791 .sid = TEGRA186_SID_AON, 792 .regs = { 793 .sid = { 794 .override = 0x4c8, 795 .security = 0x4cc, 796 }, 797 }, 798 }, { 799 .id = TEGRA186_MEMORY_CLIENT_AONDMAW, 800 .name = "aondmaw", 801 .sid = TEGRA186_SID_AON, 802 .regs = { 803 .sid = { 804 .override = 0x4d0, 805 .security = 0x4d4, 806 }, 807 }, 808 }, { 809 .id = TEGRA186_MEMORY_CLIENT_SCER, 810 .name = "scer", 811 .sid = TEGRA186_SID_SCE, 812 .regs = { 813 .sid = { 814 .override = 0x4d8, 815 .security = 0x4dc, 816 }, 817 }, 818 }, { 819 .id = TEGRA186_MEMORY_CLIENT_SCEW, 820 .name = "scew", 821 .sid = TEGRA186_SID_SCE, 822 .regs = { 823 .sid = { 824 .override = 0x4e0, 825 .security = 0x4e4, 826 }, 827 }, 828 }, { 829 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR, 830 .name = "scedmar", 831 .sid = TEGRA186_SID_SCE, 832 .regs = { 833 .sid = { 834 .override = 0x4e8, 835 .security = 0x4ec, 836 }, 837 }, 838 }, { 839 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW, 840 .name = "scedmaw", 841 .sid = TEGRA186_SID_SCE, 842 .regs = { 843 .sid = { 844 .override = 0x4f0, 845 .security = 0x4f4, 846 }, 847 }, 848 }, { 849 .id = TEGRA186_MEMORY_CLIENT_APEDMAR, 850 .name = "apedmar", 851 .sid = TEGRA186_SID_APE, 852 .regs = { 853 .sid = { 854 .override = 0x4f8, 855 .security = 0x4fc, 856 }, 857 }, 858 }, { 859 .id = TEGRA186_MEMORY_CLIENT_APEDMAW, 860 .name = "apedmaw", 861 .sid = TEGRA186_SID_APE, 862 .regs = { 863 .sid = { 864 .override = 0x500, 865 .security = 0x504, 866 }, 867 }, 868 }, { 869 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1, 870 .name = "nvdisplayr1", 871 .sid = TEGRA186_SID_NVDISPLAY, 872 .regs = { 873 .sid = { 874 .override = 0x508, 875 .security = 0x50c, 876 }, 877 }, 878 }, { 879 .id = TEGRA186_MEMORY_CLIENT_VICSRD1, 880 .name = "vicsrd1", 881 .sid = TEGRA186_SID_VIC, 882 .regs = { 883 .sid = { 884 .override = 0x510, 885 .security = 0x514, 886 }, 887 }, 888 }, { 889 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1, 890 .name = "nvdecsrd1", 891 .sid = TEGRA186_SID_NVDEC, 892 .regs = { 893 .sid = { 894 .override = 0x518, 895 .security = 0x51c, 896 }, 897 }, 898 }, 899 }; 900 901 static const struct tegra_mc_intmask tegra186_mc_intmasks[] = { 902 { 903 .reg = MC_INTMASK, 904 .mask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS | 905 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | 906 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, 907 }, 908 }; 909 910 const struct tegra_mc_soc tegra186_mc_soc = { 911 .num_clients = ARRAY_SIZE(tegra186_mc_clients), 912 .clients = tegra186_mc_clients, 913 .num_address_bits = 40, 914 .num_channels = 4, 915 .client_id_mask = 0xff, 916 .intmasks = tegra186_mc_intmasks, 917 .num_intmasks = ARRAY_SIZE(tegra186_mc_intmasks), 918 .ops = &tegra186_mc_ops, 919 .ch_intmask = 0x0000000f, 920 .global_intstatus_channel_shift = 0, 921 .regs = &tegra20_mc_regs, 922 .handle_irq = tegra30_mc_irq_handlers, 923 .num_interrupts = ARRAY_SIZE(tegra30_mc_irq_handlers), 924 .mc_addr_hi_mask = 0x3, 925 .mc_err_status_type_mask = (0x7 << 28), 926 }; 927 #endif 928