1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2019-2025 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/module.h> 9 #include <linux/mod_devicetable.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 13 #include <soc/tegra/bpmp.h> 14 #include "mc.h" 15 16 struct tegra186_emc_dvfs { 17 unsigned long latency; 18 unsigned long rate; 19 }; 20 21 struct tegra186_emc { 22 struct tegra_bpmp *bpmp; 23 struct device *dev; 24 struct clk *clk; 25 struct clk *clk_dbb; 26 27 struct tegra186_emc_dvfs *dvfs; 28 unsigned int num_dvfs; 29 30 struct { 31 struct dentry *root; 32 unsigned long min_rate; 33 unsigned long max_rate; 34 } debugfs; 35 36 struct icc_provider provider; 37 }; 38 39 /* 40 * debugfs interface 41 * 42 * The memory controller driver exposes some files in debugfs that can be used 43 * to control the EMC frequency. The top-level directory can be found here: 44 * 45 * /sys/kernel/debug/emc 46 * 47 * It contains the following files: 48 * 49 * - available_rates: This file contains a list of valid, space-separated 50 * EMC frequencies. 51 * 52 * - min_rate: Writing a value to this file sets the given frequency as the 53 * floor of the permitted range. If this is higher than the currently 54 * configured EMC frequency, this will cause the frequency to be 55 * increased so that it stays within the valid range. 56 * 57 * - max_rate: Similarily to the min_rate file, writing a value to this file 58 * sets the given frequency as the ceiling of the permitted range. If 59 * the value is lower than the currently configured EMC frequency, this 60 * will cause the frequency to be decreased so that it stays within the 61 * valid range. 62 */ 63 64 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, 65 unsigned long rate) 66 { 67 unsigned int i; 68 69 for (i = 0; i < emc->num_dvfs; i++) 70 if (rate == emc->dvfs[i].rate) 71 return true; 72 73 return false; 74 } 75 76 static int tegra186_emc_debug_available_rates_show(struct seq_file *s, 77 void *data) 78 { 79 struct tegra186_emc *emc = s->private; 80 const char *prefix = ""; 81 unsigned int i; 82 83 for (i = 0; i < emc->num_dvfs; i++) { 84 seq_printf(s, "%s%lu", prefix, emc->dvfs[i].rate); 85 prefix = " "; 86 } 87 88 seq_puts(s, "\n"); 89 90 return 0; 91 } 92 DEFINE_SHOW_ATTRIBUTE(tegra186_emc_debug_available_rates); 93 94 static int tegra186_emc_debug_min_rate_get(void *data, u64 *rate) 95 { 96 struct tegra186_emc *emc = data; 97 98 *rate = emc->debugfs.min_rate; 99 100 return 0; 101 } 102 103 static int tegra186_emc_debug_min_rate_set(void *data, u64 rate) 104 { 105 struct tegra186_emc *emc = data; 106 int err; 107 108 if (!tegra186_emc_validate_rate(emc, rate)) 109 return -EINVAL; 110 111 err = clk_set_min_rate(emc->clk, rate); 112 if (err < 0) 113 return err; 114 115 emc->debugfs.min_rate = rate; 116 117 return 0; 118 } 119 120 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_min_rate_fops, 121 tegra186_emc_debug_min_rate_get, 122 tegra186_emc_debug_min_rate_set, "%llu\n"); 123 124 static int tegra186_emc_debug_max_rate_get(void *data, u64 *rate) 125 { 126 struct tegra186_emc *emc = data; 127 128 *rate = emc->debugfs.max_rate; 129 130 return 0; 131 } 132 133 static int tegra186_emc_debug_max_rate_set(void *data, u64 rate) 134 { 135 struct tegra186_emc *emc = data; 136 int err; 137 138 if (!tegra186_emc_validate_rate(emc, rate)) 139 return -EINVAL; 140 141 err = clk_set_max_rate(emc->clk, rate); 142 if (err < 0) 143 return err; 144 145 emc->debugfs.max_rate = rate; 146 147 return 0; 148 } 149 150 DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, 151 tegra186_emc_debug_max_rate_get, 152 tegra186_emc_debug_max_rate_set, "%llu\n"); 153 154 static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) 155 { 156 struct mrq_emc_dvfs_latency_response response; 157 struct tegra_bpmp_message msg; 158 unsigned int i; 159 int err; 160 161 memset(&msg, 0, sizeof(msg)); 162 msg.mrq = MRQ_EMC_DVFS_LATENCY; 163 msg.tx.data = NULL; 164 msg.tx.size = 0; 165 msg.rx.data = &response; 166 msg.rx.size = sizeof(response); 167 168 err = tegra_bpmp_transfer(emc->bpmp, &msg); 169 if (err < 0) { 170 dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err); 171 return err; 172 } 173 if (msg.rx.ret < 0) { 174 dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); 175 return -EINVAL; 176 } 177 178 emc->debugfs.min_rate = ULONG_MAX; 179 emc->debugfs.max_rate = 0; 180 181 emc->num_dvfs = response.num_pairs; 182 183 emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL); 184 if (!emc->dvfs) 185 return -ENOMEM; 186 187 dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs); 188 189 for (i = 0; i < emc->num_dvfs; i++) { 190 emc->dvfs[i].rate = response.pairs[i].freq * 1000; 191 emc->dvfs[i].latency = response.pairs[i].latency; 192 193 if (emc->dvfs[i].rate < emc->debugfs.min_rate) 194 emc->debugfs.min_rate = emc->dvfs[i].rate; 195 196 if (emc->dvfs[i].rate > emc->debugfs.max_rate) 197 emc->debugfs.max_rate = emc->dvfs[i].rate; 198 199 dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i, 200 emc->dvfs[i].rate, emc->dvfs[i].latency); 201 } 202 203 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate); 204 if (err < 0) { 205 dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n", 206 emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk); 207 return err; 208 } 209 210 emc->debugfs.root = debugfs_create_dir("emc", NULL); 211 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, 212 &tegra186_emc_debug_available_rates_fops); 213 debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc, 214 &tegra186_emc_debug_min_rate_fops); 215 debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc, 216 &tegra186_emc_debug_max_rate_fops); 217 218 return 0; 219 } 220 221 /* 222 * tegra186_emc_icc_set_bw() - Set BW api for EMC provider 223 * @src: ICC node for External Memory Controller (EMC) 224 * @dst: ICC node for External Memory (DRAM) 225 * 226 * Do nothing here as info to BPMP-FW is now passed in the BW set function 227 * of the MC driver. BPMP-FW sets the final Freq based on the passed values. 228 */ 229 static int tegra186_emc_icc_set_bw(struct icc_node *src, struct icc_node *dst) 230 { 231 return 0; 232 } 233 234 static struct icc_node * 235 tegra186_emc_of_icc_xlate(const struct of_phandle_args *spec, void *data) 236 { 237 struct icc_provider *provider = data; 238 struct icc_node *node; 239 240 /* External Memory is the only possible ICC route */ 241 list_for_each_entry(node, &provider->nodes, node_list) { 242 if (node->id != TEGRA_ICC_EMEM) 243 continue; 244 245 return node; 246 } 247 248 return ERR_PTR(-EPROBE_DEFER); 249 } 250 251 static int tegra186_emc_icc_get_init_bw(struct icc_node *node, u32 *avg, u32 *peak) 252 { 253 *avg = 0; 254 *peak = 0; 255 256 return 0; 257 } 258 259 static int tegra186_emc_interconnect_init(struct tegra186_emc *emc) 260 { 261 struct icc_node *node; 262 int err; 263 264 emc->provider.dev = emc->dev; 265 emc->provider.set = tegra186_emc_icc_set_bw; 266 emc->provider.data = &emc->provider; 267 emc->provider.aggregate = icc_std_aggregate; 268 emc->provider.xlate = tegra186_emc_of_icc_xlate; 269 emc->provider.get_bw = tegra186_emc_icc_get_init_bw; 270 271 icc_provider_init(&emc->provider); 272 273 /* create External Memory Controller node */ 274 node = icc_node_create(TEGRA_ICC_EMC); 275 if (IS_ERR(node)) 276 return PTR_ERR(node); 277 278 node->name = "External Memory Controller"; 279 icc_node_add(node, &emc->provider); 280 281 /* link External Memory Controller to External Memory (DRAM) */ 282 err = icc_link_create(node, TEGRA_ICC_EMEM); 283 if (err) 284 goto remove_nodes; 285 286 /* create External Memory node */ 287 node = icc_node_create(TEGRA_ICC_EMEM); 288 if (IS_ERR(node)) { 289 err = PTR_ERR(node); 290 goto remove_nodes; 291 } 292 293 node->name = "External Memory (DRAM)"; 294 icc_node_add(node, &emc->provider); 295 296 err = icc_provider_register(&emc->provider); 297 if (err) 298 goto remove_nodes; 299 300 return 0; 301 302 remove_nodes: 303 icc_nodes_remove(&emc->provider); 304 305 return dev_err_probe(emc->dev, err, "failed to initialize ICC\n"); 306 } 307 308 static int tegra186_emc_probe(struct platform_device *pdev) 309 { 310 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); 311 struct tegra186_emc *emc; 312 int err; 313 314 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 315 if (!emc) 316 return -ENOMEM; 317 318 emc->bpmp = tegra_bpmp_get(&pdev->dev); 319 if (IS_ERR(emc->bpmp)) 320 return dev_err_probe(&pdev->dev, PTR_ERR(emc->bpmp), 321 "failed to get BPMP\n"); 322 323 emc->clk = devm_clk_get(&pdev->dev, "emc"); 324 if (IS_ERR(emc->clk)) { 325 err = dev_err_probe(&pdev->dev, PTR_ERR(emc->clk), 326 "failed to get EMC clock\n"); 327 goto put_bpmp; 328 } 329 330 emc->clk_dbb = devm_clk_get_optional_enabled(&pdev->dev, "dbb"); 331 if (IS_ERR(emc->clk_dbb)) { 332 err = dev_err_probe(&pdev->dev, PTR_ERR(emc->clk_dbb), 333 "failed to get DBB clock\n"); 334 goto put_bpmp; 335 } 336 337 platform_set_drvdata(pdev, emc); 338 emc->dev = &pdev->dev; 339 340 if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { 341 err = tegra186_emc_get_emc_dvfs_latency(emc); 342 if (err) 343 goto put_bpmp; 344 } 345 346 if (mc && mc->soc->icc_ops) { 347 if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { 348 mc->bwmgr_mrq_supported = true; 349 350 /* 351 * MC driver probe can't get BPMP reference as it gets probed 352 * earlier than BPMP. So, save the BPMP ref got from the EMC 353 * DT node in the mc->bpmp and use it in MC's icc_set hook. 354 */ 355 mc->bpmp = emc->bpmp; 356 barrier(); 357 } 358 359 /* 360 * Initialize the ICC even if BPMP-FW doesn't support 'MRQ_BWMGR_INT'. 361 * Use the flag 'mc->bwmgr_mrq_supported' within MC driver and return 362 * EINVAL instead of passing the request to BPMP-FW later when the BW 363 * request is made by client with 'icc_set_bw()' call. 364 */ 365 err = tegra186_emc_interconnect_init(emc); 366 if (err) { 367 mc->bpmp = NULL; 368 goto put_bpmp; 369 } 370 } 371 372 return 0; 373 374 put_bpmp: 375 tegra_bpmp_put(emc->bpmp); 376 return err; 377 } 378 379 static void tegra186_emc_remove(struct platform_device *pdev) 380 { 381 struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); 382 struct tegra186_emc *emc = platform_get_drvdata(pdev); 383 384 debugfs_remove_recursive(emc->debugfs.root); 385 386 mc->bpmp = NULL; 387 tegra_bpmp_put(emc->bpmp); 388 } 389 390 static const struct of_device_id tegra186_emc_of_match[] = { 391 #if defined(CONFIG_ARCH_TEGRA_186_SOC) 392 { .compatible = "nvidia,tegra186-emc" }, 393 #endif 394 #if defined(CONFIG_ARCH_TEGRA_194_SOC) 395 { .compatible = "nvidia,tegra194-emc" }, 396 #endif 397 #if defined(CONFIG_ARCH_TEGRA_234_SOC) 398 { .compatible = "nvidia,tegra234-emc" }, 399 #endif 400 #if defined(CONFIG_ARCH_TEGRA_264_SOC) 401 { .compatible = "nvidia,tegra264-emc" }, 402 #endif 403 { /* sentinel */ } 404 }; 405 MODULE_DEVICE_TABLE(of, tegra186_emc_of_match); 406 407 static struct platform_driver tegra186_emc_driver = { 408 .driver = { 409 .name = "tegra186-emc", 410 .of_match_table = tegra186_emc_of_match, 411 .suppress_bind_attrs = true, 412 .sync_state = icc_sync_state, 413 }, 414 .probe = tegra186_emc_probe, 415 .remove = tegra186_emc_remove, 416 }; 417 module_platform_driver(tegra186_emc_driver); 418 419 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 420 MODULE_DESCRIPTION("NVIDIA Tegra186 External Memory Controller driver"); 421