1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * 5 * Author: 6 * Mikko Perttunen <mperttunen@nvidia.com> 7 */ 8 9 #include <linux/clk-provider.h> 10 #include <linux/clk.h> 11 #include <linux/clkdev.h> 12 #include <linux/clk/tegra.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/interconnect-provider.h> 16 #include <linux/io.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of_address.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_opp.h> 23 #include <linux/sort.h> 24 #include <linux/string.h> 25 26 #include <soc/tegra/fuse.h> 27 #include <soc/tegra/mc.h> 28 29 #include "mc.h" 30 #include "tegra-emc-common.h" 31 32 #define EMC_FBIO_CFG5 0x104 33 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 34 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 35 #define EMC_FBIO_CFG5_DRAM_WIDTH_X64 BIT(4) 36 37 #define EMC_INTSTATUS 0x0 38 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) 39 40 #define EMC_CFG 0xc 41 #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) 42 #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) 43 #define EMC_CFG_DRAM_ACPD BIT(29) 44 #define EMC_CFG_DYN_SREF BIT(28) 45 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) 46 #define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) 47 48 #define EMC_REFCTRL 0x20 49 #define EMC_REFCTRL_DEV_SEL_SHIFT 0 50 #define EMC_REFCTRL_ENABLE BIT(31) 51 52 #define EMC_TIMING_CONTROL 0x28 53 #define EMC_RC 0x2c 54 #define EMC_RFC 0x30 55 #define EMC_RAS 0x34 56 #define EMC_RP 0x38 57 #define EMC_R2W 0x3c 58 #define EMC_W2R 0x40 59 #define EMC_R2P 0x44 60 #define EMC_W2P 0x48 61 #define EMC_RD_RCD 0x4c 62 #define EMC_WR_RCD 0x50 63 #define EMC_RRD 0x54 64 #define EMC_REXT 0x58 65 #define EMC_WDV 0x5c 66 #define EMC_QUSE 0x60 67 #define EMC_QRST 0x64 68 #define EMC_QSAFE 0x68 69 #define EMC_RDV 0x6c 70 #define EMC_REFRESH 0x70 71 #define EMC_BURST_REFRESH_NUM 0x74 72 #define EMC_PDEX2WR 0x78 73 #define EMC_PDEX2RD 0x7c 74 #define EMC_PCHG2PDEN 0x80 75 #define EMC_ACT2PDEN 0x84 76 #define EMC_AR2PDEN 0x88 77 #define EMC_RW2PDEN 0x8c 78 #define EMC_TXSR 0x90 79 #define EMC_TCKE 0x94 80 #define EMC_TFAW 0x98 81 #define EMC_TRPAB 0x9c 82 #define EMC_TCLKSTABLE 0xa0 83 #define EMC_TCLKSTOP 0xa4 84 #define EMC_TREFBW 0xa8 85 #define EMC_ODT_WRITE 0xb0 86 #define EMC_ODT_READ 0xb4 87 #define EMC_WEXT 0xb8 88 #define EMC_CTT 0xbc 89 #define EMC_RFC_SLR 0xc0 90 #define EMC_MRS_WAIT_CNT2 0xc4 91 92 #define EMC_MRS_WAIT_CNT 0xc8 93 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 94 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ 95 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) 96 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 97 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ 98 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) 99 100 #define EMC_MRS 0xcc 101 #define EMC_MODE_SET_DLL_RESET BIT(8) 102 #define EMC_MODE_SET_LONG_CNT BIT(26) 103 #define EMC_EMRS 0xd0 104 #define EMC_REF 0xd4 105 #define EMC_PRE 0xd8 106 107 #define EMC_SELF_REF 0xe0 108 #define EMC_SELF_REF_CMD_ENABLED BIT(0) 109 #define EMC_SELF_REF_DEV_SEL_SHIFT 30 110 111 #define EMC_MRW 0xe8 112 113 #define EMC_MRR 0xec 114 #define EMC_MRR_MA_SHIFT 16 115 #define LPDDR2_MR4_TEMP_SHIFT 0 116 117 #define EMC_XM2DQSPADCTRL3 0xf8 118 #define EMC_FBIO_SPARE 0x100 119 120 #define EMC_FBIO_CFG6 0x114 121 #define EMC_EMRS2 0x12c 122 #define EMC_MRW2 0x134 123 #define EMC_MRW4 0x13c 124 #define EMC_EINPUT 0x14c 125 #define EMC_EINPUT_DURATION 0x150 126 #define EMC_PUTERM_EXTRA 0x154 127 #define EMC_TCKESR 0x158 128 #define EMC_TPD 0x15c 129 130 #define EMC_AUTO_CAL_CONFIG 0x2a4 131 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) 132 #define EMC_AUTO_CAL_INTERVAL 0x2a8 133 #define EMC_AUTO_CAL_STATUS 0x2ac 134 #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) 135 #define EMC_STATUS 0x2b4 136 #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) 137 138 #define EMC_CFG_2 0x2b8 139 #define EMC_CFG_2_MODE_SHIFT 0 140 #define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6) 141 142 #define EMC_CFG_DIG_DLL 0x2bc 143 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0 144 #define EMC_RDV_MASK 0x2cc 145 #define EMC_WDV_MASK 0x2d0 146 #define EMC_CTT_DURATION 0x2d8 147 #define EMC_CTT_TERM_CTRL 0x2dc 148 #define EMC_ZCAL_INTERVAL 0x2e0 149 #define EMC_ZCAL_WAIT_CNT 0x2e4 150 151 #define EMC_ZQ_CAL 0x2ec 152 #define EMC_ZQ_CAL_CMD BIT(0) 153 #define EMC_ZQ_CAL_LONG BIT(4) 154 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \ 155 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 156 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \ 157 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 158 159 #define EMC_XM2CMDPADCTRL 0x2f0 160 #define EMC_XM2DQSPADCTRL 0x2f8 161 #define EMC_XM2DQSPADCTRL2 0x2fc 162 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) 163 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) 164 #define EMC_XM2DQPADCTRL 0x300 165 #define EMC_XM2DQPADCTRL2 0x304 166 #define EMC_XM2CLKPADCTRL 0x308 167 #define EMC_XM2COMPPADCTRL 0x30c 168 #define EMC_XM2VTTGENPADCTRL 0x310 169 #define EMC_XM2VTTGENPADCTRL2 0x314 170 #define EMC_XM2VTTGENPADCTRL3 0x318 171 #define EMC_XM2DQSPADCTRL4 0x320 172 #define EMC_DLL_XFORM_DQS0 0x328 173 #define EMC_DLL_XFORM_DQS1 0x32c 174 #define EMC_DLL_XFORM_DQS2 0x330 175 #define EMC_DLL_XFORM_DQS3 0x334 176 #define EMC_DLL_XFORM_DQS4 0x338 177 #define EMC_DLL_XFORM_DQS5 0x33c 178 #define EMC_DLL_XFORM_DQS6 0x340 179 #define EMC_DLL_XFORM_DQS7 0x344 180 #define EMC_DLL_XFORM_QUSE0 0x348 181 #define EMC_DLL_XFORM_QUSE1 0x34c 182 #define EMC_DLL_XFORM_QUSE2 0x350 183 #define EMC_DLL_XFORM_QUSE3 0x354 184 #define EMC_DLL_XFORM_QUSE4 0x358 185 #define EMC_DLL_XFORM_QUSE5 0x35c 186 #define EMC_DLL_XFORM_QUSE6 0x360 187 #define EMC_DLL_XFORM_QUSE7 0x364 188 #define EMC_DLL_XFORM_DQ0 0x368 189 #define EMC_DLL_XFORM_DQ1 0x36c 190 #define EMC_DLL_XFORM_DQ2 0x370 191 #define EMC_DLL_XFORM_DQ3 0x374 192 #define EMC_DLI_TRIM_TXDQS0 0x3a8 193 #define EMC_DLI_TRIM_TXDQS1 0x3ac 194 #define EMC_DLI_TRIM_TXDQS2 0x3b0 195 #define EMC_DLI_TRIM_TXDQS3 0x3b4 196 #define EMC_DLI_TRIM_TXDQS4 0x3b8 197 #define EMC_DLI_TRIM_TXDQS5 0x3bc 198 #define EMC_DLI_TRIM_TXDQS6 0x3c0 199 #define EMC_DLI_TRIM_TXDQS7 0x3c4 200 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc 201 #define EMC_SEL_DPD_CTRL 0x3d8 202 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) 203 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) 204 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) 205 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) 206 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) 207 #define EMC_SEL_DPD_CTRL_DDR3_MASK \ 208 ((0xf << 2) | BIT(8)) 209 #define EMC_SEL_DPD_CTRL_MASK \ 210 ((0x3 << 2) | BIT(5) | BIT(8)) 211 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc 212 #define EMC_DYN_SELF_REF_CONTROL 0x3e0 213 #define EMC_TXSRDLL 0x3e4 214 #define EMC_CCFIFO_ADDR 0x3e8 215 #define EMC_CCFIFO_DATA 0x3ec 216 #define EMC_CCFIFO_STATUS 0x3f0 217 #define EMC_CDB_CNTL_1 0x3f4 218 #define EMC_CDB_CNTL_2 0x3f8 219 #define EMC_XM2CLKPADCTRL2 0x3fc 220 #define EMC_AUTO_CAL_CONFIG2 0x458 221 #define EMC_AUTO_CAL_CONFIG3 0x45c 222 #define EMC_IBDLY 0x468 223 #define EMC_DLL_XFORM_ADDR0 0x46c 224 #define EMC_DLL_XFORM_ADDR1 0x470 225 #define EMC_DLL_XFORM_ADDR2 0x474 226 #define EMC_DSR_VTTGEN_DRV 0x47c 227 #define EMC_TXDSRVTTGEN 0x480 228 #define EMC_XM2CMDPADCTRL4 0x484 229 #define EMC_XM2CMDPADCTRL5 0x488 230 #define EMC_DLL_XFORM_DQS8 0x4a0 231 #define EMC_DLL_XFORM_DQS9 0x4a4 232 #define EMC_DLL_XFORM_DQS10 0x4a8 233 #define EMC_DLL_XFORM_DQS11 0x4ac 234 #define EMC_DLL_XFORM_DQS12 0x4b0 235 #define EMC_DLL_XFORM_DQS13 0x4b4 236 #define EMC_DLL_XFORM_DQS14 0x4b8 237 #define EMC_DLL_XFORM_DQS15 0x4bc 238 #define EMC_DLL_XFORM_QUSE8 0x4c0 239 #define EMC_DLL_XFORM_QUSE9 0x4c4 240 #define EMC_DLL_XFORM_QUSE10 0x4c8 241 #define EMC_DLL_XFORM_QUSE11 0x4cc 242 #define EMC_DLL_XFORM_QUSE12 0x4d0 243 #define EMC_DLL_XFORM_QUSE13 0x4d4 244 #define EMC_DLL_XFORM_QUSE14 0x4d8 245 #define EMC_DLL_XFORM_QUSE15 0x4dc 246 #define EMC_DLL_XFORM_DQ4 0x4e0 247 #define EMC_DLL_XFORM_DQ5 0x4e4 248 #define EMC_DLL_XFORM_DQ6 0x4e8 249 #define EMC_DLL_XFORM_DQ7 0x4ec 250 #define EMC_DLI_TRIM_TXDQS8 0x520 251 #define EMC_DLI_TRIM_TXDQS9 0x524 252 #define EMC_DLI_TRIM_TXDQS10 0x528 253 #define EMC_DLI_TRIM_TXDQS11 0x52c 254 #define EMC_DLI_TRIM_TXDQS12 0x530 255 #define EMC_DLI_TRIM_TXDQS13 0x534 256 #define EMC_DLI_TRIM_TXDQS14 0x538 257 #define EMC_DLI_TRIM_TXDQS15 0x53c 258 #define EMC_CDB_CNTL_3 0x540 259 #define EMC_XM2DQSPADCTRL5 0x544 260 #define EMC_XM2DQSPADCTRL6 0x548 261 #define EMC_XM2DQPADCTRL3 0x54c 262 #define EMC_DLL_XFORM_ADDR3 0x550 263 #define EMC_DLL_XFORM_ADDR4 0x554 264 #define EMC_DLL_XFORM_ADDR5 0x558 265 #define EMC_CFG_PIPE 0x560 266 #define EMC_QPOP 0x564 267 #define EMC_QUSE_WIDTH 0x568 268 #define EMC_PUTERM_WIDTH 0x56c 269 #define EMC_BGBIAS_CTL0 0x570 270 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3) 271 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2) 272 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1) 273 #define EMC_PUTERM_ADJ 0x574 274 275 #define DRAM_DEV_SEL_ALL 0 276 #define DRAM_DEV_SEL_0 BIT(31) 277 #define DRAM_DEV_SEL_1 BIT(30) 278 279 #define EMC_CFG_POWER_FEATURES_MASK \ 280 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ 281 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN) 282 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) 283 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) 284 285 /* Maximum amount of time in us. to wait for changes to become effective */ 286 #define EMC_STATUS_UPDATE_TIMEOUT 1000 287 288 enum emc_dram_type { 289 DRAM_TYPE_DDR3 = 0, 290 DRAM_TYPE_DDR1 = 1, 291 DRAM_TYPE_LPDDR3 = 2, 292 DRAM_TYPE_DDR2 = 3 293 }; 294 295 enum emc_dll_change { 296 DLL_CHANGE_NONE, 297 DLL_CHANGE_ON, 298 DLL_CHANGE_OFF 299 }; 300 301 static const unsigned long emc_burst_regs[] = { 302 EMC_RC, 303 EMC_RFC, 304 EMC_RFC_SLR, 305 EMC_RAS, 306 EMC_RP, 307 EMC_R2W, 308 EMC_W2R, 309 EMC_R2P, 310 EMC_W2P, 311 EMC_RD_RCD, 312 EMC_WR_RCD, 313 EMC_RRD, 314 EMC_REXT, 315 EMC_WEXT, 316 EMC_WDV, 317 EMC_WDV_MASK, 318 EMC_QUSE, 319 EMC_QUSE_WIDTH, 320 EMC_IBDLY, 321 EMC_EINPUT, 322 EMC_EINPUT_DURATION, 323 EMC_PUTERM_EXTRA, 324 EMC_PUTERM_WIDTH, 325 EMC_PUTERM_ADJ, 326 EMC_CDB_CNTL_1, 327 EMC_CDB_CNTL_2, 328 EMC_CDB_CNTL_3, 329 EMC_QRST, 330 EMC_QSAFE, 331 EMC_RDV, 332 EMC_RDV_MASK, 333 EMC_REFRESH, 334 EMC_BURST_REFRESH_NUM, 335 EMC_PRE_REFRESH_REQ_CNT, 336 EMC_PDEX2WR, 337 EMC_PDEX2RD, 338 EMC_PCHG2PDEN, 339 EMC_ACT2PDEN, 340 EMC_AR2PDEN, 341 EMC_RW2PDEN, 342 EMC_TXSR, 343 EMC_TXSRDLL, 344 EMC_TCKE, 345 EMC_TCKESR, 346 EMC_TPD, 347 EMC_TFAW, 348 EMC_TRPAB, 349 EMC_TCLKSTABLE, 350 EMC_TCLKSTOP, 351 EMC_TREFBW, 352 EMC_FBIO_CFG6, 353 EMC_ODT_WRITE, 354 EMC_ODT_READ, 355 EMC_FBIO_CFG5, 356 EMC_CFG_DIG_DLL, 357 EMC_CFG_DIG_DLL_PERIOD, 358 EMC_DLL_XFORM_DQS0, 359 EMC_DLL_XFORM_DQS1, 360 EMC_DLL_XFORM_DQS2, 361 EMC_DLL_XFORM_DQS3, 362 EMC_DLL_XFORM_DQS4, 363 EMC_DLL_XFORM_DQS5, 364 EMC_DLL_XFORM_DQS6, 365 EMC_DLL_XFORM_DQS7, 366 EMC_DLL_XFORM_DQS8, 367 EMC_DLL_XFORM_DQS9, 368 EMC_DLL_XFORM_DQS10, 369 EMC_DLL_XFORM_DQS11, 370 EMC_DLL_XFORM_DQS12, 371 EMC_DLL_XFORM_DQS13, 372 EMC_DLL_XFORM_DQS14, 373 EMC_DLL_XFORM_DQS15, 374 EMC_DLL_XFORM_QUSE0, 375 EMC_DLL_XFORM_QUSE1, 376 EMC_DLL_XFORM_QUSE2, 377 EMC_DLL_XFORM_QUSE3, 378 EMC_DLL_XFORM_QUSE4, 379 EMC_DLL_XFORM_QUSE5, 380 EMC_DLL_XFORM_QUSE6, 381 EMC_DLL_XFORM_QUSE7, 382 EMC_DLL_XFORM_ADDR0, 383 EMC_DLL_XFORM_ADDR1, 384 EMC_DLL_XFORM_ADDR2, 385 EMC_DLL_XFORM_ADDR3, 386 EMC_DLL_XFORM_ADDR4, 387 EMC_DLL_XFORM_ADDR5, 388 EMC_DLL_XFORM_QUSE8, 389 EMC_DLL_XFORM_QUSE9, 390 EMC_DLL_XFORM_QUSE10, 391 EMC_DLL_XFORM_QUSE11, 392 EMC_DLL_XFORM_QUSE12, 393 EMC_DLL_XFORM_QUSE13, 394 EMC_DLL_XFORM_QUSE14, 395 EMC_DLL_XFORM_QUSE15, 396 EMC_DLI_TRIM_TXDQS0, 397 EMC_DLI_TRIM_TXDQS1, 398 EMC_DLI_TRIM_TXDQS2, 399 EMC_DLI_TRIM_TXDQS3, 400 EMC_DLI_TRIM_TXDQS4, 401 EMC_DLI_TRIM_TXDQS5, 402 EMC_DLI_TRIM_TXDQS6, 403 EMC_DLI_TRIM_TXDQS7, 404 EMC_DLI_TRIM_TXDQS8, 405 EMC_DLI_TRIM_TXDQS9, 406 EMC_DLI_TRIM_TXDQS10, 407 EMC_DLI_TRIM_TXDQS11, 408 EMC_DLI_TRIM_TXDQS12, 409 EMC_DLI_TRIM_TXDQS13, 410 EMC_DLI_TRIM_TXDQS14, 411 EMC_DLI_TRIM_TXDQS15, 412 EMC_DLL_XFORM_DQ0, 413 EMC_DLL_XFORM_DQ1, 414 EMC_DLL_XFORM_DQ2, 415 EMC_DLL_XFORM_DQ3, 416 EMC_DLL_XFORM_DQ4, 417 EMC_DLL_XFORM_DQ5, 418 EMC_DLL_XFORM_DQ6, 419 EMC_DLL_XFORM_DQ7, 420 EMC_XM2CMDPADCTRL, 421 EMC_XM2CMDPADCTRL4, 422 EMC_XM2CMDPADCTRL5, 423 EMC_XM2DQPADCTRL2, 424 EMC_XM2DQPADCTRL3, 425 EMC_XM2CLKPADCTRL, 426 EMC_XM2CLKPADCTRL2, 427 EMC_XM2COMPPADCTRL, 428 EMC_XM2VTTGENPADCTRL, 429 EMC_XM2VTTGENPADCTRL2, 430 EMC_XM2VTTGENPADCTRL3, 431 EMC_XM2DQSPADCTRL3, 432 EMC_XM2DQSPADCTRL4, 433 EMC_XM2DQSPADCTRL5, 434 EMC_XM2DQSPADCTRL6, 435 EMC_DSR_VTTGEN_DRV, 436 EMC_TXDSRVTTGEN, 437 EMC_FBIO_SPARE, 438 EMC_ZCAL_WAIT_CNT, 439 EMC_MRS_WAIT_CNT2, 440 EMC_CTT, 441 EMC_CTT_DURATION, 442 EMC_CFG_PIPE, 443 EMC_DYN_SELF_REF_CONTROL, 444 EMC_QPOP 445 }; 446 447 struct emc_timing { 448 unsigned long rate; 449 450 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)]; 451 452 u32 emc_auto_cal_config; 453 u32 emc_auto_cal_config2; 454 u32 emc_auto_cal_config3; 455 u32 emc_auto_cal_interval; 456 u32 emc_bgbias_ctl0; 457 u32 emc_cfg; 458 u32 emc_cfg_2; 459 u32 emc_ctt_term_ctrl; 460 u32 emc_mode_1; 461 u32 emc_mode_2; 462 u32 emc_mode_4; 463 u32 emc_mode_reset; 464 u32 emc_mrs_wait_cnt; 465 u32 emc_sel_dpd_ctrl; 466 u32 emc_xm2dqspadctrl2; 467 u32 emc_zcal_cnt_long; 468 u32 emc_zcal_interval; 469 }; 470 471 struct tegra_emc { 472 struct device *dev; 473 474 struct tegra_mc *mc; 475 476 void __iomem *regs; 477 478 struct clk *clk; 479 480 enum emc_dram_type dram_type; 481 unsigned int dram_bus_width; 482 unsigned int dram_num; 483 484 struct emc_timing last_timing; 485 struct emc_timing *timings; 486 unsigned int num_timings; 487 488 struct { 489 struct dentry *root; 490 unsigned long min_rate; 491 unsigned long max_rate; 492 } debugfs; 493 494 struct icc_provider provider; 495 496 struct tegra_emc_rate_requests reqs; 497 }; 498 499 /* Timing change sequence functions */ 500 501 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, 502 unsigned long offset) 503 { 504 writel(value, emc->regs + EMC_CCFIFO_DATA); 505 writel(offset, emc->regs + EMC_CCFIFO_ADDR); 506 } 507 508 static void emc_seq_update_timing(struct tegra_emc *emc) 509 { 510 unsigned int i; 511 u32 value; 512 513 writel(1, emc->regs + EMC_TIMING_CONTROL); 514 515 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { 516 value = readl(emc->regs + EMC_STATUS); 517 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0) 518 return; 519 udelay(1); 520 } 521 522 dev_err(emc->dev, "timing update timed out\n"); 523 } 524 525 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) 526 { 527 unsigned int i; 528 u32 value; 529 530 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); 531 532 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { 533 value = readl(emc->regs + EMC_AUTO_CAL_STATUS); 534 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0) 535 return; 536 udelay(1); 537 } 538 539 dev_err(emc->dev, "auto cal disable timed out\n"); 540 } 541 542 static void emc_seq_wait_clkchange(struct tegra_emc *emc) 543 { 544 unsigned int i; 545 u32 value; 546 547 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) { 548 value = readl(emc->regs + EMC_INTSTATUS); 549 if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE) 550 return; 551 udelay(1); 552 } 553 554 dev_err(emc->dev, "clock change timed out\n"); 555 } 556 557 static struct emc_timing *tegra124_emc_find_timing(struct tegra_emc *emc, 558 unsigned long rate) 559 { 560 struct emc_timing *timing = NULL; 561 unsigned int i; 562 563 for (i = 0; i < emc->num_timings; i++) { 564 if (emc->timings[i].rate == rate) { 565 timing = &emc->timings[i]; 566 break; 567 } 568 } 569 570 if (!timing) { 571 dev_err(emc->dev, "no timing for rate %lu\n", rate); 572 return NULL; 573 } 574 575 return timing; 576 } 577 578 static int tegra124_emc_prepare_timing_change(struct tegra_emc *emc, 579 unsigned long rate) 580 { 581 struct emc_timing *timing = tegra124_emc_find_timing(emc, rate); 582 struct emc_timing *last = &emc->last_timing; 583 enum emc_dll_change dll_change; 584 unsigned int pre_wait = 0; 585 u32 val, val2, mask; 586 bool update = false; 587 unsigned int i; 588 589 if (!timing) 590 return -ENOENT; 591 592 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1)) 593 dll_change = DLL_CHANGE_NONE; 594 else if (!(timing->emc_mode_1 & 0x1)) 595 dll_change = DLL_CHANGE_ON; 596 else 597 dll_change = DLL_CHANGE_OFF; 598 599 /* Clear CLKCHANGE_COMPLETE interrupts */ 600 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); 601 602 /* Disable dynamic self-refresh */ 603 val = readl(emc->regs + EMC_CFG); 604 if (val & EMC_CFG_PWR_MASK) { 605 val &= ~EMC_CFG_POWER_FEATURES_MASK; 606 writel(val, emc->regs + EMC_CFG); 607 608 pre_wait = 5; 609 } 610 611 /* Disable SEL_DPD_CTRL for clock change */ 612 if (emc->dram_type == DRAM_TYPE_DDR3) 613 mask = EMC_SEL_DPD_CTRL_DDR3_MASK; 614 else 615 mask = EMC_SEL_DPD_CTRL_MASK; 616 617 val = readl(emc->regs + EMC_SEL_DPD_CTRL); 618 if (val & mask) { 619 val &= ~mask; 620 writel(val, emc->regs + EMC_SEL_DPD_CTRL); 621 } 622 623 /* Prepare DQ/DQS for clock change */ 624 val = readl(emc->regs + EMC_BGBIAS_CTL0); 625 val2 = last->emc_bgbias_ctl0; 626 if (!(timing->emc_bgbias_ctl0 & 627 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) && 628 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) { 629 val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX; 630 update = true; 631 } 632 633 if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) || 634 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) { 635 update = true; 636 } 637 638 if (update) { 639 writel(val2, emc->regs + EMC_BGBIAS_CTL0); 640 if (pre_wait < 5) 641 pre_wait = 5; 642 } 643 644 update = false; 645 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); 646 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && 647 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { 648 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; 649 update = true; 650 } 651 652 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && 653 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { 654 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; 655 update = true; 656 } 657 658 if (update) { 659 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); 660 if (pre_wait < 30) 661 pre_wait = 30; 662 } 663 664 /* Wait to settle */ 665 if (pre_wait) { 666 emc_seq_update_timing(emc); 667 udelay(pre_wait); 668 } 669 670 /* Program CTT_TERM control */ 671 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { 672 emc_seq_disable_auto_cal(emc); 673 writel(timing->emc_ctt_term_ctrl, 674 emc->regs + EMC_CTT_TERM_CTRL); 675 emc_seq_update_timing(emc); 676 } 677 678 /* Program burst shadow registers */ 679 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) 680 writel(timing->emc_burst_data[i], 681 emc->regs + emc_burst_regs[i]); 682 683 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); 684 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); 685 686 tegra_mc_write_emem_configuration(emc->mc, timing->rate); 687 688 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; 689 emc_ccfifo_writel(emc, val, EMC_CFG); 690 691 /* Program AUTO_CAL_CONFIG */ 692 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) 693 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, 694 EMC_AUTO_CAL_CONFIG2); 695 696 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) 697 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, 698 EMC_AUTO_CAL_CONFIG3); 699 700 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { 701 val = timing->emc_auto_cal_config; 702 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; 703 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); 704 } 705 706 /* DDR3: predict MRS long wait count */ 707 if (emc->dram_type == DRAM_TYPE_DDR3 && 708 dll_change == DLL_CHANGE_ON) { 709 u32 cnt = 512; 710 711 if (timing->emc_zcal_interval != 0 && 712 last->emc_zcal_interval == 0) 713 cnt -= emc->dram_num * 256; 714 715 val = (timing->emc_mrs_wait_cnt 716 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) 717 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; 718 if (cnt < val) 719 cnt = val; 720 721 val = timing->emc_mrs_wait_cnt 722 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 723 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) 724 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 725 726 writel(val, emc->regs + EMC_MRS_WAIT_CNT); 727 } 728 729 val = timing->emc_cfg_2; 730 val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR; 731 emc_ccfifo_writel(emc, val, EMC_CFG_2); 732 733 /* DDR3: Turn off DLL and enter self-refresh */ 734 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) 735 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); 736 737 /* Disable refresh controller */ 738 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), 739 EMC_REFCTRL); 740 if (emc->dram_type == DRAM_TYPE_DDR3) 741 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | 742 EMC_SELF_REF_CMD_ENABLED, 743 EMC_SELF_REF); 744 745 /* Flow control marker */ 746 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); 747 748 /* DDR3: Exit self-refresh */ 749 if (emc->dram_type == DRAM_TYPE_DDR3) 750 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), 751 EMC_SELF_REF); 752 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | 753 EMC_REFCTRL_ENABLE, 754 EMC_REFCTRL); 755 756 /* Set DRAM mode registers */ 757 if (emc->dram_type == DRAM_TYPE_DDR3) { 758 if (timing->emc_mode_1 != last->emc_mode_1) 759 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); 760 if (timing->emc_mode_2 != last->emc_mode_2) 761 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); 762 763 if ((timing->emc_mode_reset != last->emc_mode_reset) || 764 dll_change == DLL_CHANGE_ON) { 765 val = timing->emc_mode_reset; 766 if (dll_change == DLL_CHANGE_ON) { 767 val |= EMC_MODE_SET_DLL_RESET; 768 val |= EMC_MODE_SET_LONG_CNT; 769 } else { 770 val &= ~EMC_MODE_SET_DLL_RESET; 771 } 772 emc_ccfifo_writel(emc, val, EMC_MRS); 773 } 774 } else { 775 if (timing->emc_mode_2 != last->emc_mode_2) 776 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); 777 if (timing->emc_mode_1 != last->emc_mode_1) 778 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); 779 if (timing->emc_mode_4 != last->emc_mode_4) 780 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); 781 } 782 783 /* Issue ZCAL command if turning ZCAL on */ 784 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { 785 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); 786 if (emc->dram_num > 1) 787 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1, 788 EMC_ZQ_CAL); 789 } 790 791 /* Write to RO register to remove stall after change */ 792 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); 793 794 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR) 795 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2); 796 797 /* Disable AUTO_CAL for clock change */ 798 emc_seq_disable_auto_cal(emc); 799 800 /* Read register to wait until programming has settled */ 801 readl(emc->regs + EMC_INTSTATUS); 802 803 return 0; 804 } 805 806 static void tegra124_emc_complete_timing_change(struct tegra_emc *emc, 807 unsigned long rate) 808 { 809 struct emc_timing *timing = tegra124_emc_find_timing(emc, rate); 810 struct emc_timing *last = &emc->last_timing; 811 u32 val; 812 813 if (!timing) 814 return; 815 816 /* Wait until the state machine has settled */ 817 emc_seq_wait_clkchange(emc); 818 819 /* Restore AUTO_CAL */ 820 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) 821 writel(timing->emc_auto_cal_interval, 822 emc->regs + EMC_AUTO_CAL_INTERVAL); 823 824 /* Restore dynamic self-refresh */ 825 if (timing->emc_cfg & EMC_CFG_PWR_MASK) 826 writel(timing->emc_cfg, emc->regs + EMC_CFG); 827 828 /* Set ZCAL wait count */ 829 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); 830 831 /* LPDDR3: Turn off BGBIAS if low frequency */ 832 if (emc->dram_type == DRAM_TYPE_LPDDR3 && 833 timing->emc_bgbias_ctl0 & 834 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) { 835 val = timing->emc_bgbias_ctl0; 836 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN; 837 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD; 838 writel(val, emc->regs + EMC_BGBIAS_CTL0); 839 } else { 840 if (emc->dram_type == DRAM_TYPE_DDR3 && 841 readl(emc->regs + EMC_BGBIAS_CTL0) != 842 timing->emc_bgbias_ctl0) { 843 writel(timing->emc_bgbias_ctl0, 844 emc->regs + EMC_BGBIAS_CTL0); 845 } 846 847 writel(timing->emc_auto_cal_interval, 848 emc->regs + EMC_AUTO_CAL_INTERVAL); 849 } 850 851 /* Wait for timing to settle */ 852 udelay(2); 853 854 /* Reprogram SEL_DPD_CTRL */ 855 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); 856 emc_seq_update_timing(emc); 857 858 emc->last_timing = *timing; 859 } 860 861 /* Initialization and deinitialization */ 862 863 static void emc_read_current_timing(struct tegra_emc *emc, 864 struct emc_timing *timing) 865 { 866 unsigned int i; 867 868 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i) 869 timing->emc_burst_data[i] = 870 readl(emc->regs + emc_burst_regs[i]); 871 872 timing->emc_cfg = readl(emc->regs + EMC_CFG); 873 874 timing->emc_auto_cal_interval = 0; 875 timing->emc_zcal_cnt_long = 0; 876 timing->emc_mode_1 = 0; 877 timing->emc_mode_2 = 0; 878 timing->emc_mode_4 = 0; 879 timing->emc_mode_reset = 0; 880 } 881 882 static void emc_init(struct tegra_emc *emc) 883 { 884 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); 885 886 if (emc->dram_type & EMC_FBIO_CFG5_DRAM_WIDTH_X64) 887 emc->dram_bus_width = 64; 888 else 889 emc->dram_bus_width = 32; 890 891 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); 892 893 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; 894 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; 895 896 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); 897 898 emc_read_current_timing(emc, &emc->last_timing); 899 } 900 901 static int load_one_timing_from_dt(struct tegra_emc *emc, 902 struct emc_timing *timing, 903 struct device_node *node) 904 { 905 u32 value; 906 int err; 907 908 err = of_property_read_u32(node, "clock-frequency", &value); 909 if (err) { 910 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", 911 node, err); 912 return err; 913 } 914 915 timing->rate = value; 916 917 err = of_property_read_u32_array(node, "nvidia,emc-configuration", 918 timing->emc_burst_data, 919 ARRAY_SIZE(timing->emc_burst_data)); 920 if (err) { 921 dev_err(emc->dev, 922 "timing %pOFn: failed to read emc burst data: %d\n", 923 node, err); 924 return err; 925 } 926 927 #define EMC_READ_PROP(prop, dtprop) { \ 928 err = of_property_read_u32(node, dtprop, &timing->prop); \ 929 if (err) { \ 930 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ 931 node, err); \ 932 return err; \ 933 } \ 934 } 935 936 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") 937 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") 938 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") 939 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") 940 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0") 941 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") 942 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2") 943 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") 944 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") 945 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") 946 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") 947 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") 948 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt") 949 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") 950 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") 951 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") 952 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval") 953 954 #undef EMC_READ_PROP 955 956 return 0; 957 } 958 959 static int cmp_timings(const void *_a, const void *_b) 960 { 961 const struct emc_timing *a = _a; 962 const struct emc_timing *b = _b; 963 964 if (a->rate < b->rate) 965 return -1; 966 else if (a->rate == b->rate) 967 return 0; 968 else 969 return 1; 970 } 971 972 static int tegra124_emc_load_timings_from_dt(struct tegra_emc *emc, 973 struct device_node *node) 974 { 975 int child_count = of_get_child_count(node); 976 struct emc_timing *timing; 977 unsigned int i = 0; 978 int err; 979 980 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 981 GFP_KERNEL); 982 if (!emc->timings) 983 return -ENOMEM; 984 985 emc->num_timings = child_count; 986 987 for_each_child_of_node_scoped(node, child) { 988 timing = &emc->timings[i++]; 989 990 err = load_one_timing_from_dt(emc, timing, child); 991 if (err) 992 return err; 993 } 994 995 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 996 NULL); 997 998 return 0; 999 } 1000 1001 static const struct of_device_id tegra124_emc_of_match[] = { 1002 { .compatible = "nvidia,tegra124-emc" }, 1003 { .compatible = "nvidia,tegra132-emc" }, 1004 {} 1005 }; 1006 MODULE_DEVICE_TABLE(of, tegra124_emc_of_match); 1007 1008 static struct device_node * 1009 tegra124_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) 1010 { 1011 struct device_node *np; 1012 int err; 1013 1014 for_each_child_of_node(node, np) { 1015 u32 value; 1016 1017 err = of_property_read_u32(np, "nvidia,ram-code", &value); 1018 if (err || (value != ram_code)) 1019 continue; 1020 1021 return np; 1022 } 1023 1024 return NULL; 1025 } 1026 1027 /* 1028 * debugfs interface 1029 * 1030 * The memory controller driver exposes some files in debugfs that can be used 1031 * to control the EMC frequency. The top-level directory can be found here: 1032 * 1033 * /sys/kernel/debug/emc 1034 * 1035 * It contains the following files: 1036 * 1037 * - available_rates: This file contains a list of valid, space-separated 1038 * EMC frequencies. 1039 * 1040 * - min_rate: Writing a value to this file sets the given frequency as the 1041 * floor of the permitted range. If this is higher than the currently 1042 * configured EMC frequency, this will cause the frequency to be 1043 * increased so that it stays within the valid range. 1044 * 1045 * - max_rate: Similarily to the min_rate file, writing a value to this file 1046 * sets the given frequency as the ceiling of the permitted range. If 1047 * the value is lower than the currently configured EMC frequency, this 1048 * will cause the frequency to be decreased so that it stays within the 1049 * valid range. 1050 */ 1051 1052 static bool tegra124_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 1053 { 1054 unsigned int i; 1055 1056 for (i = 0; i < emc->num_timings; i++) 1057 if (rate == emc->timings[i].rate) 1058 return true; 1059 1060 return false; 1061 } 1062 1063 static int tegra124_emc_debug_available_rates_show(struct seq_file *s, 1064 void *data) 1065 { 1066 struct tegra_emc *emc = s->private; 1067 const char *prefix = ""; 1068 unsigned int i; 1069 1070 for (i = 0; i < emc->num_timings; i++) { 1071 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 1072 prefix = " "; 1073 } 1074 1075 seq_puts(s, "\n"); 1076 1077 return 0; 1078 } 1079 1080 DEFINE_SHOW_ATTRIBUTE(tegra124_emc_debug_available_rates); 1081 1082 static int tegra124_emc_debug_min_rate_get(void *data, u64 *rate) 1083 { 1084 struct tegra_emc *emc = data; 1085 1086 *rate = emc->debugfs.min_rate; 1087 1088 return 0; 1089 } 1090 1091 static int tegra124_emc_debug_min_rate_set(void *data, u64 rate) 1092 { 1093 struct tegra_emc *emc = data; 1094 int err; 1095 1096 if (!tegra124_emc_validate_rate(emc, rate)) 1097 return -EINVAL; 1098 1099 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1100 if (err < 0) 1101 return err; 1102 1103 emc->debugfs.min_rate = rate; 1104 1105 return 0; 1106 } 1107 1108 DEFINE_DEBUGFS_ATTRIBUTE(tegra124_emc_debug_min_rate_fops, 1109 tegra124_emc_debug_min_rate_get, 1110 tegra124_emc_debug_min_rate_set, "%llu\n"); 1111 1112 static int tegra124_emc_debug_max_rate_get(void *data, u64 *rate) 1113 { 1114 struct tegra_emc *emc = data; 1115 1116 *rate = emc->debugfs.max_rate; 1117 1118 return 0; 1119 } 1120 1121 static int tegra124_emc_debug_max_rate_set(void *data, u64 rate) 1122 { 1123 struct tegra_emc *emc = data; 1124 int err; 1125 1126 if (!tegra124_emc_validate_rate(emc, rate)) 1127 return -EINVAL; 1128 1129 err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1130 if (err < 0) 1131 return err; 1132 1133 emc->debugfs.max_rate = rate; 1134 1135 return 0; 1136 } 1137 1138 DEFINE_DEBUGFS_ATTRIBUTE(tegra124_emc_debug_max_rate_fops, 1139 tegra124_emc_debug_max_rate_get, 1140 tegra124_emc_debug_max_rate_set, "%llu\n"); 1141 1142 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) 1143 { 1144 unsigned int i; 1145 int err; 1146 1147 emc->debugfs.min_rate = ULONG_MAX; 1148 emc->debugfs.max_rate = 0; 1149 1150 for (i = 0; i < emc->num_timings; i++) { 1151 if (emc->timings[i].rate < emc->debugfs.min_rate) 1152 emc->debugfs.min_rate = emc->timings[i].rate; 1153 1154 if (emc->timings[i].rate > emc->debugfs.max_rate) 1155 emc->debugfs.max_rate = emc->timings[i].rate; 1156 } 1157 1158 if (!emc->num_timings) { 1159 emc->debugfs.min_rate = clk_get_rate(emc->clk); 1160 emc->debugfs.max_rate = emc->debugfs.min_rate; 1161 } 1162 1163 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 1164 emc->debugfs.max_rate); 1165 if (err < 0) { 1166 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 1167 emc->debugfs.min_rate, emc->debugfs.max_rate, 1168 emc->clk); 1169 return; 1170 } 1171 1172 emc->debugfs.root = debugfs_create_dir("emc", NULL); 1173 1174 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, 1175 &tegra124_emc_debug_available_rates_fops); 1176 debugfs_create_file("min_rate", 0644, emc->debugfs.root, 1177 emc, &tegra124_emc_debug_min_rate_fops); 1178 debugfs_create_file("max_rate", 0644, emc->debugfs.root, 1179 emc, &tegra124_emc_debug_max_rate_fops); 1180 } 1181 1182 static inline struct tegra_emc * 1183 to_tegra_emc_provider(struct icc_provider *provider) 1184 { 1185 return container_of(provider, struct tegra_emc, provider); 1186 } 1187 1188 static struct icc_node_data * 1189 emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) 1190 { 1191 struct icc_provider *provider = data; 1192 struct icc_node_data *ndata; 1193 struct icc_node *node; 1194 1195 /* External Memory is the only possible ICC route */ 1196 list_for_each_entry(node, &provider->nodes, node_list) { 1197 if (node->id != TEGRA_ICC_EMEM) 1198 continue; 1199 1200 ndata = kzalloc_obj(*ndata); 1201 if (!ndata) 1202 return ERR_PTR(-ENOMEM); 1203 1204 /* 1205 * SRC and DST nodes should have matching TAG in order to have 1206 * it set by default for a requested path. 1207 */ 1208 ndata->tag = TEGRA_MC_ICC_TAG_ISO; 1209 ndata->node = node; 1210 1211 return ndata; 1212 } 1213 1214 return ERR_PTR(-EPROBE_DEFER); 1215 } 1216 1217 static int emc_icc_set(struct icc_node *src, struct icc_node *dst) 1218 { 1219 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); 1220 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); 1221 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); 1222 unsigned long long rate = max(avg_bw, peak_bw); 1223 unsigned int dram_data_bus_width_bytes; 1224 const unsigned int ddr = 2; 1225 int err; 1226 1227 /* 1228 * Tegra124 EMC runs on a clock rate of SDRAM bus. This means that 1229 * EMC clock rate is twice smaller than the peak data rate because 1230 * data is sampled on both EMC clock edges. 1231 */ 1232 dram_data_bus_width_bytes = emc->dram_bus_width / 8; 1233 do_div(rate, ddr * dram_data_bus_width_bytes); 1234 rate = min_t(u64, rate, U32_MAX); 1235 1236 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC); 1237 if (err) 1238 return err; 1239 1240 return 0; 1241 } 1242 1243 static int tegra124_emc_interconnect_init(struct tegra_emc *emc) 1244 { 1245 const struct tegra_mc_soc *soc = emc->mc->soc; 1246 struct icc_node *node; 1247 int err; 1248 1249 emc->provider.dev = emc->dev; 1250 emc->provider.set = emc_icc_set; 1251 emc->provider.data = &emc->provider; 1252 emc->provider.aggregate = soc->icc_ops->aggregate; 1253 emc->provider.xlate_extended = emc_of_icc_xlate_extended; 1254 1255 icc_provider_init(&emc->provider); 1256 1257 /* create External Memory Controller node */ 1258 node = icc_node_create(TEGRA_ICC_EMC); 1259 if (IS_ERR(node)) 1260 return PTR_ERR(node); 1261 1262 node->name = "External Memory Controller"; 1263 icc_node_add(node, &emc->provider); 1264 1265 /* link External Memory Controller to External Memory (DRAM) */ 1266 err = icc_link_create(node, TEGRA_ICC_EMEM); 1267 if (err) 1268 goto remove_nodes; 1269 1270 /* create External Memory node */ 1271 node = icc_node_create(TEGRA_ICC_EMEM); 1272 if (IS_ERR(node)) { 1273 err = PTR_ERR(node); 1274 goto remove_nodes; 1275 } 1276 1277 node->name = "External Memory (DRAM)"; 1278 icc_node_add(node, &emc->provider); 1279 1280 err = icc_provider_register(&emc->provider); 1281 if (err) 1282 goto remove_nodes; 1283 1284 return 0; 1285 1286 remove_nodes: 1287 icc_nodes_remove(&emc->provider); 1288 1289 return dev_err_probe(emc->dev, err, "failed to initialize ICC\n"); 1290 } 1291 1292 static int tegra124_emc_opp_table_init(struct tegra_emc *emc) 1293 { 1294 u32 hw_version = BIT(tegra_sku_info.soc_speedo_id); 1295 int opp_token, err; 1296 1297 err = dev_pm_opp_set_supported_hw(emc->dev, &hw_version, 1); 1298 if (err < 0) 1299 return dev_err_probe(emc->dev, err, "failed to set OPP supported HW\n"); 1300 1301 opp_token = err; 1302 1303 err = dev_pm_opp_of_add_table(emc->dev); 1304 if (err) { 1305 if (err == -ENODEV) 1306 dev_err_probe(emc->dev, err, 1307 "OPP table not found, please update your device tree\n"); 1308 else 1309 dev_err_probe(emc->dev, err, "failed to add OPP table\n"); 1310 1311 goto put_hw_table; 1312 } 1313 1314 dev_info_once(emc->dev, "OPP HW ver. 0x%x, current clock rate %lu MHz\n", 1315 hw_version, clk_get_rate(emc->clk) / 1000000); 1316 1317 /* first dummy rate-set initializes voltage state */ 1318 err = dev_pm_opp_set_rate(emc->dev, clk_get_rate(emc->clk)); 1319 if (err) { 1320 dev_err_probe(emc->dev, err, "failed to initialize OPP clock\n"); 1321 goto remove_table; 1322 } 1323 1324 return 0; 1325 1326 remove_table: 1327 dev_pm_opp_of_remove_table(emc->dev); 1328 put_hw_table: 1329 dev_pm_opp_put_supported_hw(opp_token); 1330 1331 return err; 1332 } 1333 1334 static void devm_tegra124_emc_unset_callback(void *data) 1335 { 1336 tegra124_clk_set_emc_callbacks(NULL, NULL); 1337 } 1338 1339 static int tegra124_emc_probe(struct platform_device *pdev) 1340 { 1341 struct device_node *np; 1342 struct tegra_emc *emc; 1343 u32 ram_code; 1344 int err; 1345 1346 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); 1347 if (!emc) 1348 return -ENOMEM; 1349 1350 emc->dev = &pdev->dev; 1351 1352 emc->regs = devm_platform_ioremap_resource(pdev, 0); 1353 if (IS_ERR(emc->regs)) 1354 return PTR_ERR(emc->regs); 1355 1356 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); 1357 if (IS_ERR(emc->mc)) 1358 return PTR_ERR(emc->mc); 1359 1360 ram_code = tegra_read_ram_code(); 1361 1362 np = tegra124_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code); 1363 if (np) { 1364 err = tegra124_emc_load_timings_from_dt(emc, np); 1365 of_node_put(np); 1366 if (err) 1367 return err; 1368 } else { 1369 dev_info_once(&pdev->dev, 1370 "no memory timings for RAM code %u found in DT\n", 1371 ram_code); 1372 } 1373 1374 emc_init(emc); 1375 1376 platform_set_drvdata(pdev, emc); 1377 1378 tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change, 1379 tegra124_emc_complete_timing_change); 1380 1381 err = devm_add_action_or_reset(&pdev->dev, devm_tegra124_emc_unset_callback, 1382 NULL); 1383 if (err) 1384 return err; 1385 1386 emc->clk = devm_clk_get(&pdev->dev, "emc"); 1387 if (IS_ERR(emc->clk)) 1388 return dev_err_probe(&pdev->dev, PTR_ERR(emc->clk), 1389 "failed to get EMC clock\n"); 1390 1391 err = tegra124_emc_opp_table_init(emc); 1392 if (err) 1393 return err; 1394 1395 tegra_emc_rate_requests_init(&emc->reqs, &pdev->dev); 1396 1397 if (IS_ENABLED(CONFIG_DEBUG_FS)) 1398 emc_debugfs_init(&pdev->dev, emc); 1399 1400 tegra124_emc_interconnect_init(emc); 1401 1402 /* 1403 * Don't allow the kernel module to be unloaded. Unloading adds some 1404 * extra complexity which doesn't really worth the effort in a case of 1405 * this driver. 1406 */ 1407 try_module_get(THIS_MODULE); 1408 1409 return 0; 1410 }; 1411 1412 static struct platform_driver tegra124_emc_driver = { 1413 .probe = tegra124_emc_probe, 1414 .driver = { 1415 .name = "tegra-emc", 1416 .of_match_table = tegra124_emc_of_match, 1417 .suppress_bind_attrs = true, 1418 .sync_state = icc_sync_state, 1419 }, 1420 }; 1421 module_platform_driver(tegra124_emc_driver); 1422 1423 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 1424 MODULE_DESCRIPTION("NVIDIA Tegra124 EMC driver"); 1425 MODULE_LICENSE("GPL v2"); 1426