1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra114 External Memory Controller driver 4 * 5 * Based on downstream driver from NVIDIA and tegra124-emc.c 6 * Copyright (C) 2011-2014 NVIDIA Corporation 7 * 8 * Copyright (C) 2024 Svyatoslav Ryhel <clamor95@gmail.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/clk/tegra.h> 13 #include <linux/debugfs.h> 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_opp.h> 23 #include <linux/sort.h> 24 #include <linux/string.h> 25 26 #include <soc/tegra/common.h> 27 #include <soc/tegra/fuse.h> 28 #include <soc/tegra/mc.h> 29 30 #include "mc.h" 31 #include "tegra-emc-common.h" 32 33 #define EMC_INTSTATUS 0x0 34 #define EMC_INTSTATUS_REFRESH_OVERFLOW BIT(3) 35 #define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4) 36 37 #define EMC_INTMASK 0x4 38 39 #define EMC_DBG 0x8 40 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) 41 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) 42 #define EMC_DBG_FORCE_UPDATE BIT(2) 43 #define EMC_DBG_CFG_PRIORITY BIT(24) 44 45 #define EMC_CFG 0xc 46 #define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18) 47 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18)) 48 #define EMC_CFG_DYN_SREF BIT(28) 49 #define EMC_CFG_DRAM_ACPD BIT(29) 50 #define EMC_CFG_DRAM_CLKSTOP_SR BIT(30) 51 #define EMC_CFG_DRAM_CLKSTOP_PD BIT(31) 52 53 #define EMC_ADR_CFG 0x10 54 #define EMC_ADR_CFG_EMEM_NUMDEV BIT(0) 55 56 #define EMC_REFCTRL 0x20 57 #define EMC_REFCTRL_DEV_SEL_SHIFT 0 58 #define EMC_REFCTRL_ENABLE BIT(31) 59 60 #define EMC_TIMING_CONTROL 0x28 61 #define EMC_RC 0x2c 62 #define EMC_RFC 0x30 63 #define EMC_RAS 0x34 64 #define EMC_RP 0x38 65 #define EMC_R2W 0x3c 66 #define EMC_W2R 0x40 67 #define EMC_R2P 0x44 68 #define EMC_W2P 0x48 69 #define EMC_RD_RCD 0x4c 70 #define EMC_WR_RCD 0x50 71 #define EMC_RRD 0x54 72 #define EMC_REXT 0x58 73 #define EMC_WDV 0x5c 74 #define EMC_QUSE 0x60 75 #define EMC_QRST 0x64 76 #define EMC_QSAFE 0x68 77 #define EMC_RDV 0x6c 78 #define EMC_REFRESH 0x70 79 #define EMC_BURST_REFRESH_NUM 0x74 80 #define EMC_PDEX2WR 0x78 81 #define EMC_PDEX2RD 0x7c 82 #define EMC_PCHG2PDEN 0x80 83 #define EMC_ACT2PDEN 0x84 84 #define EMC_AR2PDEN 0x88 85 #define EMC_RW2PDEN 0x8c 86 #define EMC_TXSR 0x90 87 #define EMC_TCKE 0x94 88 #define EMC_TFAW 0x98 89 #define EMC_TRPAB 0x9c 90 #define EMC_TCLKSTABLE 0xa0 91 #define EMC_TCLKSTOP 0xa4 92 #define EMC_TREFBW 0xa8 93 #define EMC_QUSE_EXTRA 0xac 94 #define EMC_ODT_WRITE 0xb0 95 #define EMC_ODT_READ 0xb4 96 #define EMC_WEXT 0xb8 97 #define EMC_CTT 0xbc 98 #define EMC_RFC_SLR 0xc0 99 #define EMC_MRS_WAIT_CNT2 0xc4 100 101 #define EMC_MRS_WAIT_CNT 0xc8 102 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0 103 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \ 104 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT) 105 #define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16 106 #define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \ 107 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) 108 109 #define EMC_MRS 0xcc 110 #define EMC_MODE_SET_DLL_RESET BIT(8) 111 #define EMC_MODE_SET_LONG_CNT BIT(26) 112 #define EMC_EMRS 0xd0 113 #define EMC_REF 0xd4 114 #define EMC_PRE 0xd8 115 116 #define EMC_SELF_REF 0xe0 117 #define EMC_SELF_REF_CMD_ENABLED BIT(0) 118 #define EMC_SELF_REF_DEV_SEL_SHIFT 30 119 120 #define EMC_MRW 0xe8 121 122 #define EMC_MRR 0xec 123 #define EMC_MRR_MA_SHIFT 16 124 #define LPDDR2_MR4_TEMP_SHIFT 0 125 126 #define EMC_XM2DQSPADCTRL3 0xf8 127 #define EMC_FBIO_SPARE 0x100 128 129 #define EMC_FBIO_CFG5 0x104 130 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3 131 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0 132 133 #define EMC_FBIO_CFG6 0x114 134 #define EMC_EMRS2 0x12c 135 #define EMC_MRW2 0x134 136 #define EMC_MRW4 0x13c 137 #define EMC_EINPUT 0x14c 138 #define EMC_EINPUT_DURATION 0x150 139 #define EMC_PUTERM_EXTRA 0x154 140 #define EMC_TCKESR 0x158 141 #define EMC_TPD 0x15c 142 143 #define EMC_AUTO_CAL_CONFIG 0x2a4 144 #define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31) 145 #define EMC_AUTO_CAL_INTERVAL 0x2a8 146 #define EMC_AUTO_CAL_STATUS 0x2ac 147 #define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31) 148 #define EMC_STATUS 0x2b4 149 #define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23) 150 151 #define EMC_CFG_2 0x2b8 152 #define EMC_CFG_2_CLKCHANGE_REQ_ENABLE BIT(0) 153 #define EMC_CFG_2_CLKCHANGE_PD_ENABLE BIT(1) 154 #define EMC_CFG_2_CLKCHANGE_SR_ENABLE BIT(2) 155 156 #define EMC_CFG_DIG_DLL 0x2bc 157 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0 158 #define EMC_RDV_MASK 0x2cc 159 #define EMC_WDV_MASK 0x2d0 160 #define EMC_CTT_DURATION 0x2d8 161 #define EMC_CTT_TERM_CTRL 0x2dc 162 #define EMC_ZCAL_INTERVAL 0x2e0 163 #define EMC_ZCAL_WAIT_CNT 0x2e4 164 165 #define EMC_ZQ_CAL 0x2ec 166 #define EMC_ZQ_CAL_CMD BIT(0) 167 #define EMC_ZQ_CAL_LONG BIT(4) 168 #define EMC_ZQ_CAL_LONG_CMD_DEV0 \ 169 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 170 #define EMC_ZQ_CAL_LONG_CMD_DEV1 \ 171 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD) 172 173 #define EMC_XM2CMDPADCTRL 0x2f0 174 #define EMC_XM2DQSPADCTRL 0x2f8 175 #define EMC_XM2DQSPADCTRL2 0x2fc 176 #define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0) 177 #define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5) 178 #define EMC_XM2DQPADCTRL 0x300 179 #define EMC_XM2DQPADCTRL2 0x304 180 #define EMC_XM2CLKPADCTRL 0x308 181 #define EMC_XM2COMPPADCTRL 0x30c 182 #define EMC_XM2VTTGENPADCTRL 0x310 183 #define EMC_XM2VTTGENPADCTRL2 0x314 184 #define EMC_XM2QUSEPADCTRL 0x318 185 #define EMC_XM2DQSPADCTRL4 0x320 186 #define EMC_DLL_XFORM_DQS0 0x328 187 #define EMC_DLL_XFORM_DQS1 0x32c 188 #define EMC_DLL_XFORM_DQS2 0x330 189 #define EMC_DLL_XFORM_DQS3 0x334 190 #define EMC_DLL_XFORM_DQS4 0x338 191 #define EMC_DLL_XFORM_DQS5 0x33c 192 #define EMC_DLL_XFORM_DQS6 0x340 193 #define EMC_DLL_XFORM_DQS7 0x344 194 #define EMC_DLL_XFORM_QUSE0 0x348 195 #define EMC_DLL_XFORM_QUSE1 0x34c 196 #define EMC_DLL_XFORM_QUSE2 0x350 197 #define EMC_DLL_XFORM_QUSE3 0x354 198 #define EMC_DLL_XFORM_QUSE4 0x358 199 #define EMC_DLL_XFORM_QUSE5 0x35c 200 #define EMC_DLL_XFORM_QUSE6 0x360 201 #define EMC_DLL_XFORM_QUSE7 0x364 202 #define EMC_DLL_XFORM_DQ0 0x368 203 #define EMC_DLL_XFORM_DQ1 0x36c 204 #define EMC_DLL_XFORM_DQ2 0x370 205 #define EMC_DLL_XFORM_DQ3 0x374 206 #define EMC_DLI_TRIM_TXDQS0 0x3a8 207 #define EMC_DLI_TRIM_TXDQS1 0x3ac 208 #define EMC_DLI_TRIM_TXDQS2 0x3b0 209 #define EMC_DLI_TRIM_TXDQS3 0x3b4 210 #define EMC_DLI_TRIM_TXDQS4 0x3b8 211 #define EMC_DLI_TRIM_TXDQS5 0x3bc 212 #define EMC_DLI_TRIM_TXDQS6 0x3c0 213 #define EMC_DLI_TRIM_TXDQS7 0x3c4 214 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc 215 #define EMC_SEL_DPD_CTRL 0x3d8 216 #define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8) 217 #define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5) 218 #define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4) 219 #define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3) 220 #define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2) 221 #define EMC_SEL_DPD_CTRL_DDR3_MASK \ 222 ((0xf << 2) | BIT(8)) 223 #define EMC_SEL_DPD_CTRL_MASK \ 224 ((0x3 << 2) | BIT(5) | BIT(8)) 225 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc 226 #define EMC_DYN_SELF_REF_CONTROL 0x3e0 227 #define EMC_TXSRDLL 0x3e4 228 #define EMC_CCFIFO_ADDR 0x3e8 229 #define EMC_CCFIFO_DATA 0x3ec 230 #define EMC_CCFIFO_STATUS 0x3f0 231 #define EMC_CDB_CNTL_1 0x3f4 232 #define EMC_CDB_CNTL_2 0x3f8 233 #define EMC_XM2CLKPADCTRL2 0x3fc 234 #define EMC_AUTO_CAL_CONFIG2 0x458 235 #define EMC_AUTO_CAL_CONFIG3 0x45c 236 #define EMC_IBDLY 0x468 237 #define EMC_DLL_XFORM_ADDR0 0x46c 238 #define EMC_DLL_XFORM_ADDR1 0x470 239 #define EMC_DLL_XFORM_ADDR2 0x474 240 #define EMC_DSR_VTTGEN_DRV 0x47c 241 #define EMC_TXDSRVTTGEN 0x480 242 #define EMC_XM2CMDPADCTRL4 0x484 243 244 #define DRAM_DEV_SEL_ALL 0 245 #define DRAM_DEV_SEL_0 BIT(31) 246 #define DRAM_DEV_SEL_1 BIT(30) 247 248 #define EMC_CFG_POWER_FEATURES_MASK \ 249 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \ 250 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN) 251 #define EMC_REFCTRL_DEV_SEL(n) ((((n) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) 252 #define EMC_DRAM_DEV_SEL(n) (((n) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0) 253 254 /* Maximum amount of time in us. to wait for changes to become effective */ 255 #define EMC_STATUS_UPDATE_TIMEOUT 1000 256 257 enum emc_dram_type { 258 DRAM_TYPE_DDR3, 259 DRAM_TYPE_DDR1, 260 DRAM_TYPE_LPDDR2, 261 DRAM_TYPE_DDR2 262 }; 263 264 enum emc_dll_change { 265 DLL_CHANGE_NONE, 266 DLL_CHANGE_ON, 267 DLL_CHANGE_OFF 268 }; 269 270 static const unsigned long emc_burst_regs[] = { 271 EMC_RC, 272 EMC_RFC, 273 EMC_RAS, 274 EMC_RP, 275 EMC_R2W, 276 EMC_W2R, 277 EMC_R2P, 278 EMC_W2P, 279 EMC_RD_RCD, 280 EMC_WR_RCD, 281 EMC_RRD, 282 EMC_REXT, 283 EMC_WEXT, 284 EMC_WDV, 285 EMC_WDV_MASK, 286 EMC_QUSE, 287 EMC_IBDLY, 288 EMC_EINPUT, 289 EMC_EINPUT_DURATION, 290 EMC_PUTERM_EXTRA, 291 EMC_CDB_CNTL_1, 292 EMC_CDB_CNTL_2, 293 EMC_QRST, 294 EMC_QSAFE, 295 EMC_RDV, 296 EMC_RDV_MASK, 297 EMC_REFRESH, 298 EMC_BURST_REFRESH_NUM, 299 EMC_PRE_REFRESH_REQ_CNT, 300 EMC_PDEX2WR, 301 EMC_PDEX2RD, 302 EMC_PCHG2PDEN, 303 EMC_ACT2PDEN, 304 EMC_AR2PDEN, 305 EMC_RW2PDEN, 306 EMC_TXSR, 307 EMC_TXSRDLL, 308 EMC_TCKE, 309 EMC_TCKESR, 310 EMC_TPD, 311 EMC_TFAW, 312 EMC_TRPAB, 313 EMC_TCLKSTABLE, 314 EMC_TCLKSTOP, 315 EMC_TREFBW, 316 EMC_QUSE_EXTRA, 317 EMC_FBIO_CFG6, 318 EMC_ODT_WRITE, 319 EMC_ODT_READ, 320 EMC_FBIO_CFG5, 321 EMC_CFG_DIG_DLL, 322 EMC_CFG_DIG_DLL_PERIOD, 323 EMC_DLL_XFORM_DQS0, 324 EMC_DLL_XFORM_DQS1, 325 EMC_DLL_XFORM_DQS2, 326 EMC_DLL_XFORM_DQS3, 327 EMC_DLL_XFORM_DQS4, 328 EMC_DLL_XFORM_DQS5, 329 EMC_DLL_XFORM_DQS6, 330 EMC_DLL_XFORM_DQS7, 331 EMC_DLL_XFORM_QUSE0, 332 EMC_DLL_XFORM_QUSE1, 333 EMC_DLL_XFORM_QUSE2, 334 EMC_DLL_XFORM_QUSE3, 335 EMC_DLL_XFORM_QUSE4, 336 EMC_DLL_XFORM_QUSE5, 337 EMC_DLL_XFORM_QUSE6, 338 EMC_DLL_XFORM_QUSE7, 339 EMC_DLI_TRIM_TXDQS0, 340 EMC_DLI_TRIM_TXDQS1, 341 EMC_DLI_TRIM_TXDQS2, 342 EMC_DLI_TRIM_TXDQS3, 343 EMC_DLI_TRIM_TXDQS4, 344 EMC_DLI_TRIM_TXDQS5, 345 EMC_DLI_TRIM_TXDQS6, 346 EMC_DLI_TRIM_TXDQS7, 347 EMC_DLL_XFORM_DQ0, 348 EMC_DLL_XFORM_DQ1, 349 EMC_DLL_XFORM_DQ2, 350 EMC_DLL_XFORM_DQ3, 351 EMC_XM2CMDPADCTRL, 352 EMC_XM2CMDPADCTRL4, 353 EMC_XM2DQPADCTRL2, 354 EMC_XM2CLKPADCTRL, 355 EMC_XM2COMPPADCTRL, 356 EMC_XM2VTTGENPADCTRL, 357 EMC_XM2VTTGENPADCTRL2, 358 EMC_XM2DQSPADCTRL3, 359 EMC_XM2DQSPADCTRL4, 360 EMC_DSR_VTTGEN_DRV, 361 EMC_TXDSRVTTGEN, 362 EMC_FBIO_SPARE, 363 EMC_ZCAL_WAIT_CNT, 364 EMC_MRS_WAIT_CNT2, 365 EMC_CTT, 366 EMC_CTT_DURATION, 367 EMC_DYN_SELF_REF_CONTROL, 368 }; 369 370 struct emc_timing { 371 unsigned long rate; 372 373 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)]; 374 375 u32 emc_auto_cal_config; 376 u32 emc_auto_cal_config2; 377 u32 emc_auto_cal_config3; 378 u32 emc_auto_cal_interval; 379 u32 emc_cfg; 380 u32 emc_ctt_term_ctrl; 381 u32 emc_mode_1; 382 u32 emc_mode_2; 383 u32 emc_mode_4; 384 u32 emc_mode_reset; 385 u32 emc_mrs_wait_cnt; 386 u32 emc_sel_dpd_ctrl; 387 u32 emc_xm2dqspadctrl2; 388 u32 emc_zcal_cnt_long; 389 u32 emc_zcal_interval; 390 }; 391 392 struct tegra_emc { 393 struct device *dev; 394 struct tegra_mc *mc; 395 void __iomem *regs; 396 unsigned int irq; 397 struct clk *clk; 398 399 enum emc_dram_type dram_type; 400 unsigned int dram_num; 401 402 struct emc_timing last_timing; 403 struct emc_timing *timings; 404 unsigned int num_timings; 405 406 struct { 407 struct dentry *root; 408 unsigned long min_rate; 409 unsigned long max_rate; 410 } debugfs; 411 412 struct icc_provider provider; 413 struct tegra_emc_rate_requests reqs; 414 }; 415 416 static irqreturn_t tegra114_emc_isr(int irq, void *data) 417 { 418 struct tegra_emc *emc = data; 419 u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW; 420 u32 status; 421 422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; 423 if (!status) 424 return IRQ_NONE; 425 426 /* notify about HW problem */ 427 if (status & EMC_INTSTATUS_REFRESH_OVERFLOW) 428 dev_err_ratelimited(emc->dev, 429 "refresh request overflow timeout\n"); 430 431 /* clear interrupts */ 432 writel_relaxed(status, emc->regs + EMC_INTSTATUS); 433 434 return IRQ_HANDLED; 435 } 436 437 /* Timing change sequence functions */ 438 439 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, 440 unsigned long offset) 441 { 442 writel(value, emc->regs + EMC_CCFIFO_DATA); 443 writel(offset, emc->regs + EMC_CCFIFO_ADDR); 444 } 445 446 static void emc_seq_update_timing(struct tegra_emc *emc) 447 { 448 int ret; 449 u32 value; 450 451 writel(1, emc->regs + EMC_TIMING_CONTROL); 452 453 ret = readl_poll_timeout_atomic(emc->regs + EMC_STATUS, value, 454 !(value & EMC_STATUS_TIMING_UPDATE_STALLED), 455 1, EMC_STATUS_UPDATE_TIMEOUT); 456 if (ret) 457 dev_err(emc->dev, "timing update timed out\n"); 458 } 459 460 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) 461 { 462 int ret; 463 u32 value; 464 465 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL); 466 467 ret = readl_poll_timeout_atomic(emc->regs + EMC_AUTO_CAL_STATUS, value, 468 !(value & EMC_AUTO_CAL_STATUS_ACTIVE), 469 1, EMC_STATUS_UPDATE_TIMEOUT); 470 if (ret) 471 dev_err(emc->dev, "auto cal disable timed out\n"); 472 } 473 474 static void emc_seq_wait_clkchange(struct tegra_emc *emc) 475 { 476 int ret; 477 u32 value; 478 479 ret = readl_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, value, 480 value & EMC_INTSTATUS_CLKCHANGE_COMPLETE, 481 1, EMC_STATUS_UPDATE_TIMEOUT); 482 if (ret) 483 dev_err(emc->dev, "clock change timed out\n"); 484 } 485 486 static struct emc_timing *tegra114_emc_find_timing(struct tegra_emc *emc, 487 unsigned long rate) 488 { 489 struct emc_timing *timing = NULL; 490 unsigned int i; 491 492 for (i = 0; i < emc->num_timings; i++) { 493 if (emc->timings[i].rate == rate) { 494 timing = &emc->timings[i]; 495 break; 496 } 497 } 498 499 if (!timing) { 500 dev_err(emc->dev, "no timing for rate %lu\n", rate); 501 return NULL; 502 } 503 504 return timing; 505 } 506 507 static int tegra114_emc_prepare_timing_change(struct tegra_emc *emc, 508 unsigned long rate) 509 { 510 struct emc_timing *timing = tegra114_emc_find_timing(emc, rate); 511 struct emc_timing *last = &emc->last_timing; 512 enum emc_dll_change dll_change; 513 unsigned int pre_wait = 0; 514 u32 val, mask; 515 bool next_dll_enabled = !(timing->emc_mode_1 & 0x1); 516 bool last_dll_enabled = !(last->emc_mode_1 & 0x1); 517 bool update = false; 518 unsigned int i; 519 520 if (!timing) 521 return -ENOENT; 522 523 if (next_dll_enabled == last_dll_enabled) 524 dll_change = DLL_CHANGE_NONE; 525 else if (next_dll_enabled) 526 dll_change = DLL_CHANGE_ON; 527 else 528 dll_change = DLL_CHANGE_OFF; 529 530 /* Clear CLKCHANGE_COMPLETE interrupts */ 531 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS); 532 533 /* Disable dynamic self-refresh */ 534 val = readl(emc->regs + EMC_CFG); 535 if (val & EMC_CFG_PWR_MASK) { 536 val &= ~EMC_CFG_POWER_FEATURES_MASK; 537 writel(val, emc->regs + EMC_CFG); 538 539 pre_wait = 5; 540 } 541 542 /* Disable SEL_DPD_CTRL for clock change */ 543 if (emc->dram_type == DRAM_TYPE_DDR3) 544 mask = EMC_SEL_DPD_CTRL_DDR3_MASK; 545 else 546 mask = EMC_SEL_DPD_CTRL_MASK; 547 548 val = readl(emc->regs + EMC_SEL_DPD_CTRL); 549 if (val & mask) { 550 val &= ~mask; 551 writel(val, emc->regs + EMC_SEL_DPD_CTRL); 552 } 553 554 /* Prepare DQ/DQS for clock change */ 555 val = readl(emc->regs + EMC_XM2DQSPADCTRL2); 556 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE && 557 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) { 558 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE; 559 update = true; 560 } 561 562 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE && 563 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) { 564 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE; 565 update = true; 566 } 567 568 if (update) { 569 writel(val, emc->regs + EMC_XM2DQSPADCTRL2); 570 if (pre_wait < 30) 571 pre_wait = 30; 572 } 573 574 /* Wait to settle */ 575 if (pre_wait) { 576 emc_seq_update_timing(emc); 577 udelay(pre_wait); 578 } 579 580 /* Program CTT_TERM control */ 581 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) { 582 emc_seq_disable_auto_cal(emc); 583 writel(timing->emc_ctt_term_ctrl, 584 emc->regs + EMC_CTT_TERM_CTRL); 585 emc_seq_update_timing(emc); 586 } 587 588 /* Program burst shadow registers */ 589 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i) 590 writel(timing->emc_burst_data[i], 591 emc->regs + emc_burst_regs[i]); 592 593 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2); 594 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL); 595 596 tegra_mc_write_emem_configuration(emc->mc, timing->rate); 597 598 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK; 599 emc_ccfifo_writel(emc, val, EMC_CFG); 600 601 /* Program AUTO_CAL_CONFIG */ 602 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2) 603 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2, 604 EMC_AUTO_CAL_CONFIG2); 605 606 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3) 607 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3, 608 EMC_AUTO_CAL_CONFIG3); 609 610 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) { 611 val = timing->emc_auto_cal_config; 612 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START; 613 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG); 614 } 615 616 /* DDR3: predict MRS long wait count */ 617 if (emc->dram_type == DRAM_TYPE_DDR3 && 618 dll_change == DLL_CHANGE_ON) { 619 u32 cnt = 512; 620 621 if (timing->emc_zcal_interval != 0 && 622 last->emc_zcal_interval == 0) 623 cnt -= emc->dram_num * 256; 624 625 val = (timing->emc_mrs_wait_cnt 626 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK) 627 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT; 628 if (cnt < val) 629 cnt = val; 630 631 val = timing->emc_mrs_wait_cnt 632 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 633 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT) 634 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; 635 636 writel(val, emc->regs + EMC_MRS_WAIT_CNT); 637 } 638 639 /* DDR3: Turn off DLL and enter self-refresh */ 640 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) 641 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); 642 643 /* Disable refresh controller */ 644 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num), 645 EMC_REFCTRL); 646 if (emc->dram_type == DRAM_TYPE_DDR3) 647 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) | 648 EMC_SELF_REF_CMD_ENABLED, 649 EMC_SELF_REF); 650 651 /* Flow control marker */ 652 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); 653 654 /* DDR3: Exit self-refresh */ 655 if (emc->dram_type == DRAM_TYPE_DDR3) 656 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num), 657 EMC_SELF_REF); 658 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) | 659 EMC_REFCTRL_ENABLE, 660 EMC_REFCTRL); 661 662 /* Set DRAM mode registers */ 663 if (emc->dram_type == DRAM_TYPE_DDR3) { 664 if (timing->emc_mode_1 != last->emc_mode_1) 665 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS); 666 if (timing->emc_mode_2 != last->emc_mode_2) 667 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2); 668 669 if (timing->emc_mode_reset != last->emc_mode_reset || 670 dll_change == DLL_CHANGE_ON) { 671 val = timing->emc_mode_reset; 672 if (dll_change == DLL_CHANGE_ON) { 673 val |= EMC_MODE_SET_DLL_RESET; 674 val |= EMC_MODE_SET_LONG_CNT; 675 } else { 676 val &= ~EMC_MODE_SET_DLL_RESET; 677 } 678 emc_ccfifo_writel(emc, val, EMC_MRS); 679 } 680 } else { 681 if (timing->emc_mode_2 != last->emc_mode_2) 682 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2); 683 if (timing->emc_mode_1 != last->emc_mode_1) 684 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW); 685 if (timing->emc_mode_4 != last->emc_mode_4) 686 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4); 687 } 688 689 /* Issue ZCAL command if turning ZCAL on */ 690 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) { 691 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL); 692 if (emc->dram_num > 1) 693 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1, 694 EMC_ZQ_CAL); 695 } 696 697 /* Write to RO register to remove stall after change */ 698 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS); 699 700 /* Disable AUTO_CAL for clock change */ 701 emc_seq_disable_auto_cal(emc); 702 703 /* Read register to wait until programming has settled */ 704 mc_readl(emc->mc, MC_EMEM_ADR_CFG); 705 706 return 0; 707 } 708 709 static void tegra114_emc_complete_timing_change(struct tegra_emc *emc, 710 unsigned long rate) 711 { 712 struct emc_timing *timing = tegra114_emc_find_timing(emc, rate); 713 struct emc_timing *last = &emc->last_timing; 714 715 if (!timing) 716 return; 717 718 /* Wait until the state machine has settled */ 719 emc_seq_wait_clkchange(emc); 720 721 /* Restore AUTO_CAL */ 722 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl) 723 writel(timing->emc_auto_cal_interval, 724 emc->regs + EMC_AUTO_CAL_INTERVAL); 725 726 /* Restore dynamic self-refresh */ 727 if (timing->emc_cfg & EMC_CFG_PWR_MASK) 728 writel(timing->emc_cfg, emc->regs + EMC_CFG); 729 730 /* Set ZCAL wait count */ 731 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT); 732 733 /* Wait for timing to settle */ 734 udelay(2); 735 736 /* Reprogram SEL_DPD_CTRL */ 737 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL); 738 emc_seq_update_timing(emc); 739 740 emc->last_timing = *timing; 741 } 742 743 /* Initialization and deinitialization */ 744 745 static void emc_read_current_timing(struct tegra_emc *emc, 746 struct emc_timing *timing) 747 { 748 unsigned int i; 749 750 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i) 751 timing->emc_burst_data[i] = 752 readl(emc->regs + emc_burst_regs[i]); 753 754 timing->emc_cfg = readl(emc->regs + EMC_CFG); 755 756 timing->emc_auto_cal_interval = 0; 757 timing->emc_zcal_cnt_long = 0; 758 timing->emc_mode_1 = 0; 759 timing->emc_mode_2 = 0; 760 timing->emc_mode_4 = 0; 761 timing->emc_mode_reset = 0; 762 } 763 764 static void emc_init(struct tegra_emc *emc) 765 { 766 u32 emc_cfg, emc_dbg; 767 u32 intmask = EMC_INTSTATUS_REFRESH_OVERFLOW; 768 const char *dram_type_str; 769 770 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); 771 772 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK; 773 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; 774 775 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc); 776 777 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); 778 779 /* enable EMC and CAR to handshake on PLL divider/source changes */ 780 emc_cfg |= EMC_CFG_2_CLKCHANGE_REQ_ENABLE; 781 782 /* configure clock change mode accordingly to DRAM type */ 783 if (emc->dram_type == DRAM_TYPE_LPDDR2) 784 emc_cfg |= EMC_CFG_2_CLKCHANGE_PD_ENABLE; 785 else 786 emc_cfg &= ~EMC_CFG_2_CLKCHANGE_PD_ENABLE; 787 788 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); 789 790 /* initialize interrupt */ 791 writel_relaxed(intmask, emc->regs + EMC_INTMASK); 792 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); 793 794 /* ensure that unwanted debug features are disabled */ 795 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); 796 emc_dbg |= EMC_DBG_CFG_PRIORITY; 797 emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY; 798 emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE; 799 emc_dbg &= ~EMC_DBG_FORCE_UPDATE; 800 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); 801 802 switch (emc->dram_type) { 803 case DRAM_TYPE_DDR1: 804 dram_type_str = "DDR1"; 805 break; 806 case DRAM_TYPE_LPDDR2: 807 dram_type_str = "LPDDR2"; 808 break; 809 case DRAM_TYPE_DDR2: 810 dram_type_str = "DDR2"; 811 break; 812 case DRAM_TYPE_DDR3: 813 dram_type_str = "DDR3"; 814 break; 815 } 816 817 dev_info_once(emc->dev, "%u %s %s attached\n", emc->dram_num, 818 dram_type_str, emc->dram_num == 2 ? "devices" : "device"); 819 820 emc_read_current_timing(emc, &emc->last_timing); 821 } 822 823 static int load_one_timing_from_dt(struct tegra_emc *emc, 824 struct emc_timing *timing, 825 struct device_node *node) 826 { 827 u32 value; 828 int err; 829 830 err = of_property_read_u32(node, "clock-frequency", &value); 831 if (err) { 832 dev_err(emc->dev, "timing %pOFn: failed to read rate: %d\n", 833 node, err); 834 return err; 835 } 836 837 timing->rate = value; 838 839 err = of_property_read_u32_array(node, "nvidia,emc-configuration", 840 timing->emc_burst_data, 841 ARRAY_SIZE(timing->emc_burst_data)); 842 if (err) { 843 dev_err(emc->dev, 844 "timing %pOFn: failed to read emc burst data: %d\n", 845 node, err); 846 return err; 847 } 848 849 #define EMC_READ_PROP(prop, dtprop) { \ 850 err = of_property_read_u32(node, dtprop, &timing->prop); \ 851 if (err) { \ 852 dev_err(emc->dev, "timing %pOFn: failed to read " #prop ": %d\n", \ 853 node, err); \ 854 return err; \ 855 } \ 856 } 857 858 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config") 859 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2") 860 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3") 861 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") 862 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg") 863 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl") 864 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1") 865 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2") 866 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4") 867 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset") 868 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt") 869 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl") 870 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2") 871 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") 872 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval") 873 874 #undef EMC_READ_PROP 875 876 return 0; 877 } 878 879 static int cmp_timings(const void *_a, const void *_b) 880 { 881 const struct emc_timing *a = _a; 882 const struct emc_timing *b = _b; 883 884 if (a->rate < b->rate) 885 return -1; 886 else if (a->rate == b->rate) 887 return 0; 888 else 889 return 1; 890 } 891 892 static int emc_check_mc_timings(struct tegra_emc *emc) 893 { 894 struct tegra_mc *mc = emc->mc; 895 unsigned int i; 896 897 if (emc->num_timings != mc->num_timings) { 898 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", 899 emc->num_timings, mc->num_timings); 900 return -EINVAL; 901 } 902 903 for (i = 0; i < mc->num_timings; i++) { 904 if (emc->timings[i].rate != mc->timings[i].rate) { 905 dev_err(emc->dev, 906 "emc/mc timing rate mismatch: %lu %lu\n", 907 emc->timings[i].rate, mc->timings[i].rate); 908 return -EINVAL; 909 } 910 } 911 912 return 0; 913 } 914 915 static int tegra114_emc_load_timings_from_dt(struct tegra_emc *emc, 916 struct device_node *node) 917 { 918 int child_count = of_get_child_count(node); 919 struct emc_timing *timing; 920 unsigned int i = 0; 921 int err; 922 923 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), 924 GFP_KERNEL); 925 if (!emc->timings) 926 return -ENOMEM; 927 928 emc->num_timings = child_count; 929 930 for_each_child_of_node_scoped(node, child) { 931 timing = &emc->timings[i++]; 932 933 err = load_one_timing_from_dt(emc, timing, child); 934 if (err) 935 return err; 936 } 937 938 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, 939 NULL); 940 941 err = emc_check_mc_timings(emc); 942 if (err) 943 return err; 944 945 dev_info_once(emc->dev, 946 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", 947 emc->num_timings, 948 tegra_read_ram_code(), 949 emc->timings[0].rate / 1000000, 950 emc->timings[emc->num_timings - 1].rate / 1000000); 951 952 return 0; 953 } 954 955 static struct device_node * 956 tegra114_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code) 957 { 958 struct device_node *np; 959 int err; 960 961 for_each_child_of_node(node, np) { 962 u32 value; 963 964 err = of_property_read_u32(np, "nvidia,ram-code", &value); 965 if (err || value != ram_code) 966 continue; 967 968 return np; 969 } 970 971 return NULL; 972 } 973 974 /* 975 * debugfs interface 976 * 977 * The memory controller driver exposes some files in debugfs that can be used 978 * to control the EMC frequency. The top-level directory can be found here: 979 * 980 * /sys/kernel/debug/emc 981 * 982 * It contains the following files: 983 * 984 * - available_rates: This file contains a list of valid, space-separated 985 * EMC frequencies. 986 * 987 * - min_rate: Writing a value to this file sets the given frequency as the 988 * floor of the permitted range. If this is higher than the currently 989 * configured EMC frequency, this will cause the frequency to be 990 * increased so that it stays within the valid range. 991 * 992 * - max_rate: Similarly to the min_rate file, writing a value to this file 993 * sets the given frequency as the ceiling of the permitted range. If 994 * the value is lower than the currently configured EMC frequency, this 995 * will cause the frequency to be decreased so that it stays within the 996 * valid range. 997 */ 998 999 static bool tegra114_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) 1000 { 1001 unsigned int i; 1002 1003 for (i = 0; i < emc->num_timings; i++) 1004 if (rate == emc->timings[i].rate) 1005 return true; 1006 1007 return false; 1008 } 1009 1010 static int tegra114_emc_debug_available_rates_show(struct seq_file *s, 1011 void *data) 1012 { 1013 struct tegra_emc *emc = s->private; 1014 const char *prefix = ""; 1015 unsigned int i; 1016 1017 for (i = 0; i < emc->num_timings; i++) { 1018 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); 1019 prefix = " "; 1020 } 1021 1022 seq_puts(s, "\n"); 1023 1024 return 0; 1025 } 1026 1027 DEFINE_SHOW_ATTRIBUTE(tegra114_emc_debug_available_rates); 1028 1029 static int tegra114_emc_debug_min_rate_get(void *data, u64 *rate) 1030 { 1031 struct tegra_emc *emc = data; 1032 1033 *rate = emc->debugfs.min_rate; 1034 1035 return 0; 1036 } 1037 1038 static int tegra114_emc_debug_min_rate_set(void *data, u64 rate) 1039 { 1040 struct tegra_emc *emc = data; 1041 int err; 1042 1043 if (!tegra114_emc_validate_rate(emc, rate)) 1044 return -EINVAL; 1045 1046 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1047 if (err < 0) 1048 return err; 1049 1050 emc->debugfs.min_rate = rate; 1051 1052 return 0; 1053 } 1054 1055 DEFINE_DEBUGFS_ATTRIBUTE(tegra114_emc_debug_min_rate_fops, 1056 tegra114_emc_debug_min_rate_get, 1057 tegra114_emc_debug_min_rate_set, "%llu\n"); 1058 1059 static int tegra114_emc_debug_max_rate_get(void *data, u64 *rate) 1060 { 1061 struct tegra_emc *emc = data; 1062 1063 *rate = emc->debugfs.max_rate; 1064 1065 return 0; 1066 } 1067 1068 static int tegra114_emc_debug_max_rate_set(void *data, u64 rate) 1069 { 1070 struct tegra_emc *emc = data; 1071 int err; 1072 1073 if (!tegra114_emc_validate_rate(emc, rate)) 1074 return -EINVAL; 1075 1076 err = tegra_emc_set_max_rate(&emc->reqs, rate, TEGRA_EMC_RATE_DEBUG); 1077 if (err < 0) 1078 return err; 1079 1080 emc->debugfs.max_rate = rate; 1081 1082 return 0; 1083 } 1084 1085 DEFINE_DEBUGFS_ATTRIBUTE(tegra114_emc_debug_max_rate_fops, 1086 tegra114_emc_debug_max_rate_get, 1087 tegra114_emc_debug_max_rate_set, "%llu\n"); 1088 1089 static void emc_debugfs_init(struct device *dev, struct tegra_emc *emc) 1090 { 1091 unsigned int i; 1092 int err; 1093 1094 emc->debugfs.min_rate = ULONG_MAX; 1095 emc->debugfs.max_rate = 0; 1096 1097 for (i = 0; i < emc->num_timings; i++) { 1098 if (emc->timings[i].rate < emc->debugfs.min_rate) 1099 emc->debugfs.min_rate = emc->timings[i].rate; 1100 1101 if (emc->timings[i].rate > emc->debugfs.max_rate) 1102 emc->debugfs.max_rate = emc->timings[i].rate; 1103 } 1104 1105 if (!emc->num_timings) { 1106 emc->debugfs.min_rate = clk_get_rate(emc->clk); 1107 emc->debugfs.max_rate = emc->debugfs.min_rate; 1108 } 1109 1110 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, 1111 emc->debugfs.max_rate); 1112 if (err < 0) { 1113 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", 1114 emc->debugfs.min_rate, emc->debugfs.max_rate, 1115 emc->clk); 1116 return; 1117 } 1118 1119 emc->debugfs.root = debugfs_create_dir("emc", NULL); 1120 1121 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, 1122 &tegra114_emc_debug_available_rates_fops); 1123 debugfs_create_file("min_rate", 0644, emc->debugfs.root, 1124 emc, &tegra114_emc_debug_min_rate_fops); 1125 debugfs_create_file("max_rate", 0644, emc->debugfs.root, 1126 emc, &tegra114_emc_debug_max_rate_fops); 1127 } 1128 1129 static inline struct tegra_emc * 1130 to_tegra_emc_provider(struct icc_provider *provider) 1131 { 1132 return container_of(provider, struct tegra_emc, provider); 1133 } 1134 1135 static struct icc_node_data * 1136 emc_of_icc_xlate_extended(const struct of_phandle_args *spec, void *data) 1137 { 1138 struct icc_provider *provider = data; 1139 struct icc_node_data *ndata; 1140 struct icc_node *node; 1141 1142 /* External Memory is the only possible ICC route */ 1143 list_for_each_entry(node, &provider->nodes, node_list) { 1144 if (node->id != TEGRA_ICC_EMEM) 1145 continue; 1146 1147 ndata = kzalloc_obj(*ndata); 1148 if (!ndata) 1149 return ERR_PTR(-ENOMEM); 1150 1151 /* 1152 * SRC and DST nodes should have matching TAG in order to have 1153 * it set by default for a requested path. 1154 */ 1155 ndata->tag = TEGRA_MC_ICC_TAG_ISO; 1156 ndata->node = node; 1157 1158 return ndata; 1159 } 1160 1161 return ERR_PTR(-EPROBE_DEFER); 1162 } 1163 1164 static int emc_icc_set(struct icc_node *src, struct icc_node *dst) 1165 { 1166 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); 1167 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); 1168 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); 1169 unsigned long long rate = max(avg_bw, peak_bw); 1170 unsigned int dram_data_bus_width_bytes = 4; 1171 const unsigned int ddr = 2; 1172 int err; 1173 1174 /* 1175 * Tegra114 EMC runs on a clock rate of SDRAM bus. This means that 1176 * EMC clock rate is twice smaller than the peak data rate because 1177 * data is sampled on both EMC clock edges. 1178 */ 1179 do_div(rate, ddr * dram_data_bus_width_bytes); 1180 rate = min_t(u64, rate, U32_MAX); 1181 1182 err = tegra_emc_set_min_rate(&emc->reqs, rate, TEGRA_EMC_RATE_ICC); 1183 if (err) 1184 return err; 1185 1186 return 0; 1187 } 1188 1189 static int tegra114_emc_interconnect_init(struct tegra_emc *emc) 1190 { 1191 const struct tegra_mc_soc *soc = emc->mc->soc; 1192 struct icc_node *node; 1193 int err; 1194 1195 emc->provider.dev = emc->dev; 1196 emc->provider.set = emc_icc_set; 1197 emc->provider.data = &emc->provider; 1198 emc->provider.aggregate = soc->icc_ops->aggregate; 1199 emc->provider.xlate_extended = emc_of_icc_xlate_extended; 1200 1201 icc_provider_init(&emc->provider); 1202 1203 /* create External Memory Controller node */ 1204 node = icc_node_create(TEGRA_ICC_EMC); 1205 if (IS_ERR(node)) { 1206 err = PTR_ERR(node); 1207 goto err_msg; 1208 } 1209 1210 node->name = "External Memory Controller"; 1211 icc_node_add(node, &emc->provider); 1212 1213 /* link External Memory Controller to External Memory (DRAM) */ 1214 err = icc_link_create(node, TEGRA_ICC_EMEM); 1215 if (err) 1216 goto remove_nodes; 1217 1218 /* create External Memory node */ 1219 node = icc_node_create(TEGRA_ICC_EMEM); 1220 if (IS_ERR(node)) { 1221 err = PTR_ERR(node); 1222 goto remove_nodes; 1223 } 1224 1225 node->name = "External Memory (DRAM)"; 1226 icc_node_add(node, &emc->provider); 1227 1228 err = icc_provider_register(&emc->provider); 1229 if (err) 1230 goto remove_nodes; 1231 1232 return 0; 1233 1234 remove_nodes: 1235 icc_nodes_remove(&emc->provider); 1236 err_msg: 1237 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); 1238 1239 return err; 1240 } 1241 1242 static void devm_tegra114_emc_unset_callback(void *data) 1243 { 1244 tegra124_clk_set_emc_callbacks(NULL, NULL); 1245 } 1246 1247 static int tegra114_emc_probe(struct platform_device *pdev) 1248 { 1249 struct tegra_core_opp_params opp_params = {}; 1250 struct device *dev = &pdev->dev; 1251 struct device_node *np; 1252 struct tegra_emc *emc; 1253 u32 ram_code; 1254 int err; 1255 1256 emc = devm_kzalloc(dev, sizeof(*emc), GFP_KERNEL); 1257 if (!emc) 1258 return -ENOMEM; 1259 1260 emc->dev = dev; 1261 1262 emc->regs = devm_platform_ioremap_resource(pdev, 0); 1263 if (IS_ERR(emc->regs)) 1264 return PTR_ERR(emc->regs); 1265 1266 emc->mc = devm_tegra_memory_controller_get(dev); 1267 if (IS_ERR(emc->mc)) 1268 return PTR_ERR(emc->mc); 1269 1270 ram_code = tegra_read_ram_code(); 1271 1272 np = tegra114_emc_find_node_by_ram_code(dev->of_node, ram_code); 1273 if (np) { 1274 err = tegra114_emc_load_timings_from_dt(emc, np); 1275 of_node_put(np); 1276 if (err) 1277 return err; 1278 } else { 1279 dev_info_once(dev, "no memory timings for RAM code %u found in DT\n", 1280 ram_code); 1281 } 1282 1283 emc_init(emc); 1284 1285 platform_set_drvdata(pdev, emc); 1286 1287 tegra124_clk_set_emc_callbacks(tegra114_emc_prepare_timing_change, 1288 tegra114_emc_complete_timing_change); 1289 1290 err = devm_add_action_or_reset(dev, devm_tegra114_emc_unset_callback, 1291 NULL); 1292 if (err) 1293 return err; 1294 1295 err = platform_get_irq(pdev, 0); 1296 if (err < 0) 1297 return err; 1298 1299 emc->irq = err; 1300 1301 err = devm_request_irq(dev, emc->irq, tegra114_emc_isr, 0, 1302 dev_name(dev), emc); 1303 if (err) 1304 return dev_err_probe(dev, err, "failed to request irq\n"); 1305 1306 emc->clk = devm_clk_get(dev, "emc"); 1307 if (IS_ERR(emc->clk)) 1308 return dev_err_probe(dev, PTR_ERR(emc->clk), 1309 "failed to get EMC clock\n"); 1310 1311 opp_params.init_state = true; 1312 1313 err = devm_tegra_core_dev_init_opp_table(dev, &opp_params); 1314 if (err) 1315 return err; 1316 1317 tegra_emc_rate_requests_init(&emc->reqs, dev); 1318 1319 if (IS_ENABLED(CONFIG_DEBUG_FS)) 1320 emc_debugfs_init(dev, emc); 1321 1322 tegra114_emc_interconnect_init(emc); 1323 1324 /* 1325 * Don't allow the kernel module to be unloaded. Unloading adds some 1326 * extra complexity which doesn't really worth the effort in a case of 1327 * this driver. 1328 */ 1329 try_module_get(THIS_MODULE); 1330 1331 return 0; 1332 }; 1333 1334 static const struct of_device_id tegra114_emc_of_match[] = { 1335 { .compatible = "nvidia,tegra114-emc" }, 1336 { } 1337 }; 1338 MODULE_DEVICE_TABLE(of, tegra114_emc_of_match); 1339 1340 static struct platform_driver tegra114_emc_driver = { 1341 .probe = tegra114_emc_probe, 1342 .driver = { 1343 .name = "tegra114-emc", 1344 .of_match_table = tegra114_emc_of_match, 1345 .suppress_bind_attrs = true, 1346 .sync_state = icc_sync_state, 1347 }, 1348 }; 1349 module_platform_driver(tegra114_emc_driver); 1350 1351 MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>"); 1352 MODULE_DESCRIPTION("NVIDIA Tegra114 EMC driver"); 1353 MODULE_LICENSE("GPL"); 1354