1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #ifndef MEMORY_TEGRA_MC_H 7 #define MEMORY_TEGRA_MC_H 8 9 #include <linux/bits.h> 10 #include <linux/io.h> 11 #include <linux/numa.h> 12 #include <linux/types.h> 13 14 #include <soc/tegra/mc.h> 15 16 #define MC_INTSTATUS 0x00 17 /* Bit field of MC_INTSTATUS register */ 18 #define MC_INT_DECERR_EMEM BIT(6) 19 #define MC_INT_INVALID_GART_PAGE BIT(7) 20 #define MC_INT_SECURITY_VIOLATION BIT(8) 21 #define MC_INT_ARBITRATION_EMEM BIT(9) 22 #define MC_INT_INVALID_SMMU_PAGE BIT(10) 23 #define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) 24 #define MC_INT_DECERR_VPR BIT(12) 25 #define MC_INT_SECERR_SEC BIT(13) 26 #define MC_INT_DECERR_MTS BIT(16) 27 #define MC_INT_DECERR_GENERALIZED_CARVEOUT BIT(17) 28 #define MC_INT_DECERR_ROUTE_SANITY BIT(20) 29 #define MC_INT_DECERR_ROUTE_SANITY_GIC_MSI BIT(21) 30 31 #define MC_INTMASK 0x04 32 #define MC_GART_ERROR_REQ 0x30 33 #define MC_EMEM_ADR_CFG 0x54 34 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) 35 36 #define MC_DECERR_EMEM_OTHERS_STATUS 0x58 37 #define MC_SECURITY_VIOLATION_STATUS 0x74 38 #define MC_EMEM_ARB_CFG 0x90 39 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff) 40 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 41 42 #define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 43 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) 44 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) 45 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff 46 47 #define MC_EMEM_ARB_TIMING_RCD 0x98 48 #define MC_EMEM_ARB_TIMING_RP 0x9c 49 #define MC_EMEM_ARB_TIMING_RC 0xa0 50 #define MC_EMEM_ARB_TIMING_RAS 0xa4 51 #define MC_EMEM_ARB_TIMING_FAW 0xa8 52 #define MC_EMEM_ARB_TIMING_RRD 0xac 53 #define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 54 #define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 55 #define MC_EMEM_ARB_TIMING_R2R 0xb8 56 #define MC_EMEM_ARB_TIMING_W2W 0xbc 57 #define MC_EMEM_ARB_TIMING_R2W 0xc0 58 #define MC_EMEM_ARB_TIMING_W2R 0xc4 59 #define MC_EMEM_ARB_MISC2 0xc8 60 #define MC_EMEM_ARB_DA_TURNS 0xd0 61 #define MC_EMEM_ARB_DA_COVERS 0xd4 62 #define MC_EMEM_ARB_MISC0 0xd8 63 #define MC_EMEM_ARB_MISC1 0xdc 64 #define MC_EMEM_ARB_RING1_THROTTLE 0xe0 65 #define MC_EMEM_ARB_OVERRIDE 0xe8 66 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 67 68 #define MC_TIMING_CONTROL_DBG 0xf8 69 #define MC_TIMING_CONTROL 0xfc 70 #define MC_TIMING_UPDATE BIT(0) 71 72 #define MC_GLOBAL_INTSTATUS 0xf24 73 74 /* Bit field of MC_ERR_STATUS_0 register */ 75 #define MC_ERR_STATUS_RW BIT(16) 76 #define MC_ERR_STATUS_SECURITY BIT(17) 77 #define MC_ERR_STATUS_NONSECURE BIT(25) 78 #define MC_ERR_STATUS_WRITABLE BIT(26) 79 #define MC_ERR_STATUS_READABLE BIT(27) 80 81 #define MC_ERR_STATUS_GSC_ADR_HI_MASK 0xffff 82 #define MC_ERR_STATUS_GSC_ADR_HI_SHIFT 16 83 #define MC_ERR_STATUS_RT_ADR_HI_SHIFT 15 84 85 #define MC_ERR_STATUS_TYPE_SHIFT 28 86 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28) 87 #define MC_ERR_STATUS_RT_TYPE_MASK (0xf << 28) 88 #define MC_ERR_STATUS_RT_TYPE_SHIFT 28 89 90 #define MC_ERR_STATUS_ADR_HI_SHIFT 20 91 92 #define MC_BROADCAST_CHANNEL ~0 93 94 /* Tegra264 specific registers */ 95 96 /* Registers for MSS HUB */ 97 #define MSS_HUB_GLOBAL_INTSTATUS_0 0x6000 98 #define MSS_HUBC_INTR BIT(0) 99 #define MSS_HUB_GLOBAL_MASK 0x7F00 100 #define MSS_HUB_GLOBAL_SHIFT 8 101 102 #define MSS_HUB_HUBC_INTSTATUS_0 0x6008 103 #define MSS_HUB_INTRSTATUS_0 0x600c 104 #define MSS_HUB_HUBC_INTMASK_0 0x6010 105 #define MSS_HUB_HUBC_SCRUB_DONE_INTMASK BIT(0) 106 107 #define MSS_HUB_HUBC_INTPRIORITY_0 0x6014 108 #define MSS_HUB_INTRMASK_0 0x6018 109 #define MSS_HUB_COALESCER_ERR_INTMASK BIT(0) 110 #define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_INTMASK BIT(1) 111 #define MSS_HUB_ILLEGAL_TBUGRP_ID_INTMASK BIT(2) 112 #define MSS_HUB_MSI_ERR_INTMASK BIT(3) 113 #define MSS_HUB_POISON_RSP_INTMASK BIT(4) 114 #define MSS_HUB_RESTRICTED_ACCESS_ERR_INTMASK BIT(5) 115 #define MSS_HUB_RESERVED_PA_ERR_INTMASK BIT(6) 116 117 #define MSS_HUB_INTRPRIORITY_0 0x601c 118 #define MSS_HUB_SMMU_BYPASS_ALLOW_ERR_STATUS_0 0x6020 119 #define MSS_HUB_MSI_ERR_STATUS_0 0x6024 120 #define MSS_HUB_POISON_RSP_STATUS_0 0x6028 121 #define MSS_HUB_COALESCE_ERR_STATUS_0 0x60e0 122 #define MSS_HUB_COALESCE_ERR_ADR_HI_0 0x60e4 123 #define MSS_HUB_COALESCE_ERR_ADR_0 0x60e8 124 #define MSS_HUB_RESTRICTED_ACCESS_ERR_STATUS_0 0x638c 125 #define MSS_HUB_RESERVED_PA_ERR_STATUS_0 0x6390 126 #define MSS_HUB_ILLEGAL_TBUGRP_ID_ERR_STATUS_0 0x63b0 127 128 /* Registers for channels */ 129 #define MC_CH_INTSTATUS_0 0x82d4 130 #define MC_CH_INTMASK_0 0x82d8 131 #define WCAM_ERR_INTMASK BIT(19) 132 133 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1_0 0xbc74 134 135 /* Registers for MCF */ 136 #define MCF_COMMON_INTSTATUS0_0_0 0xce04 137 #define MCF_INTSTATUS_0 0xce2c 138 #define MCF_INTMASK_0 0xce30 139 #define MCF_INTPRIORITY_0 0xce34 140 141 /* Registers for SBS */ 142 #define MSS_SBS_INTSTATUS_0 0xec08 143 #define MSS_SBS_INTMASK_0 0xec0c 144 #define MSS_SBS_FILL_FIFO_ISO_OVERFLOW_INTMASK BIT(0) 145 #define MSS_SBS_FILL_FIFO_SISO_OVERFLOW_INTMASK BIT(1) 146 #define MSS_SBS_FILL_FIFO_NISO_OVERFLOW_INTMASK BIT(2) 147 148 /* Bit field of MC_ERR_ROUTE_SANITY_STATUS_0 register */ 149 #define MC_ERR_ROUTE_SANITY_RW BIT(12) 150 #define MC_ERR_ROUTE_SANITY_SEC BIT(13) 151 152 #define ERR_GENERALIZED_APERTURE_ID_SHIFT 0 153 #define ERR_GENERALIZED_APERTURE_ID_MASK 0x1F 154 #define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_SHIFT 5 155 #define ERR_GENERALIZED_CARVEOUT_APERTURE_ID_MASK 0x1F 156 157 static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents) 158 { 159 val = val * percents; 160 do_div(val, 100); 161 162 return min_t(u64, val, U32_MAX); 163 } 164 165 static inline struct tegra_mc * 166 icc_provider_to_tegra_mc(struct icc_provider *provider) 167 { 168 return container_of(provider, struct tegra_mc, provider); 169 } 170 171 /* 172 * Compose a globally-unique ICC node ID. On single-socket 173 * systems (NUMA_NO_NODE), the SoC client ID is returned unchanged. 174 * On multi-socket systems, the NUMA node ID is encoded in the 175 * upper bits of the returned ID. 176 * 177 * The client ID field is sized to keep composed IDs below 178 * ICC_DYN_ID_START (the start of the ICC core's dynamic-ID range). 179 */ 180 #define TEGRA_MC_CLIENT_ID_BITS 12 181 #define TEGRA_MC_CLIENT_ID_MASK ((1U << TEGRA_MC_CLIENT_ID_BITS) - 1) 182 183 static inline u32 tegra_mc_get_client_id(int node_id, int id) 184 { 185 if (node_id == NUMA_NO_NODE) 186 return id; 187 188 return ((node_id + 1) << TEGRA_MC_CLIENT_ID_BITS) | id; 189 } 190 191 static inline struct icc_node *tegra_mc_icc_node_create(int node_id, int id) 192 { 193 return icc_node_create(tegra_mc_get_client_id(node_id, id)); 194 } 195 196 static inline int tegra_mc_icc_link_create(struct icc_node *node, int node_id, int id) 197 { 198 return icc_link_create(node, tegra_mc_get_client_id(node_id, id)); 199 } 200 201 /* Return the SoC client ID encoded in an ICC node ID. */ 202 static inline u32 tegra_mc_client_id_from_node(const struct icc_node *node) 203 { 204 return node->id & TEGRA_MC_CLIENT_ID_MASK; 205 } 206 207 static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch, 208 unsigned long offset) 209 { 210 if (!mc->bcast_ch_regs) 211 return 0; 212 213 if (ch == MC_BROADCAST_CHANNEL) 214 return readl_relaxed(mc->bcast_ch_regs + offset); 215 216 return readl_relaxed(mc->ch_regs[ch] + offset); 217 } 218 219 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch, 220 u32 value, unsigned long offset) 221 { 222 if (!mc->bcast_ch_regs) 223 return; 224 225 if (ch == MC_BROADCAST_CHANNEL) 226 writel_relaxed(value, mc->bcast_ch_regs + offset); 227 else 228 writel_relaxed(value, mc->ch_regs[ch] + offset); 229 } 230 231 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset) 232 { 233 return readl_relaxed(mc->regs + offset); 234 } 235 236 static inline void mc_writel(const struct tegra_mc *mc, u32 value, 237 unsigned long offset) 238 { 239 writel_relaxed(value, mc->regs + offset); 240 } 241 242 extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common; 243 244 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 245 extern const struct tegra_mc_soc tegra20_mc_soc; 246 #endif 247 248 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 249 extern const struct tegra_mc_soc tegra30_mc_soc; 250 #endif 251 252 #ifdef CONFIG_ARCH_TEGRA_114_SOC 253 extern const struct tegra_mc_soc tegra114_mc_soc; 254 #endif 255 256 #ifdef CONFIG_ARCH_TEGRA_124_SOC 257 extern const struct tegra_mc_soc tegra124_mc_soc; 258 #endif 259 260 #ifdef CONFIG_ARCH_TEGRA_132_SOC 261 extern const struct tegra_mc_soc tegra132_mc_soc; 262 #endif 263 264 #ifdef CONFIG_ARCH_TEGRA_210_SOC 265 extern const struct tegra_mc_soc tegra210_mc_soc; 266 #endif 267 268 #ifdef CONFIG_ARCH_TEGRA_186_SOC 269 extern const struct tegra_mc_soc tegra186_mc_soc; 270 #endif 271 272 #ifdef CONFIG_ARCH_TEGRA_194_SOC 273 extern const struct tegra_mc_soc tegra194_mc_soc; 274 #endif 275 276 #ifdef CONFIG_ARCH_TEGRA_234_SOC 277 extern const struct tegra_mc_soc tegra234_mc_soc; 278 #endif 279 280 #if defined(CONFIG_ARCH_TEGRA_234_SOC) || defined(CONFIG_ARCH_TEGRA_238_SOC) 281 extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops; 282 #endif 283 284 #ifdef CONFIG_ARCH_TEGRA_238_SOC 285 extern const struct tegra_mc_soc tegra238_mc_soc; 286 #endif 287 288 #ifdef CONFIG_ARCH_TEGRA_264_SOC 289 extern const struct tegra_mc_soc tegra264_mc_soc; 290 #endif 291 292 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 293 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 294 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 295 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 296 defined(CONFIG_ARCH_TEGRA_210_SOC) 297 int tegra30_mc_probe(struct tegra_mc *mc); 298 extern const struct tegra_mc_ops tegra30_mc_ops; 299 #endif 300 301 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ 302 defined(CONFIG_ARCH_TEGRA_194_SOC) || \ 303 defined(CONFIG_ARCH_TEGRA_234_SOC) || \ 304 defined(CONFIG_ARCH_TEGRA_238_SOC) || \ 305 defined(CONFIG_ARCH_TEGRA_264_SOC) 306 extern const struct tegra_mc_ops tegra186_mc_ops; 307 #endif 308 309 irqreturn_t tegra30_mc_handle_irq(int irq, void *data); 310 extern const irq_handler_t tegra30_mc_irq_handlers[1]; 311 extern const char * const tegra_mc_status_names[32]; 312 extern const char * const tegra20_mc_error_names[8]; 313 314 /* 315 * These IDs are for internal use of Tegra ICC drivers. The ID numbers are 316 * chosen such that they don't conflict with the device-tree ICC node IDs. 317 */ 318 #define TEGRA_ICC_MC 1000 319 #define TEGRA_ICC_EMC 1001 320 #define TEGRA_ICC_EMEM 1002 321 322 #endif /* MEMORY_TEGRA_MC_H */ 323