1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/slab.h> 20 #include <linux/sort.h> 21 #include <linux/tegra-icc.h> 22 23 #include <soc/tegra/fuse.h> 24 25 #include "mc.h" 26 27 static DEFINE_MUTEX(tegra_mc_debugfs_root_lock); 28 static struct dentry *tegra_mc_debugfs_root; 29 30 static const struct of_device_id tegra_mc_of_match[] = { 31 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 32 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 33 #endif 34 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 35 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 36 #endif 37 #ifdef CONFIG_ARCH_TEGRA_114_SOC 38 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 39 #endif 40 #ifdef CONFIG_ARCH_TEGRA_124_SOC 41 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 42 #endif 43 #ifdef CONFIG_ARCH_TEGRA_132_SOC 44 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 45 #endif 46 #ifdef CONFIG_ARCH_TEGRA_210_SOC 47 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 48 #endif 49 #ifdef CONFIG_ARCH_TEGRA_186_SOC 50 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, 51 #endif 52 #ifdef CONFIG_ARCH_TEGRA_194_SOC 53 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, 54 #endif 55 #ifdef CONFIG_ARCH_TEGRA_234_SOC 56 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc }, 57 #endif 58 #ifdef CONFIG_ARCH_TEGRA_238_SOC 59 { .compatible = "nvidia,tegra238-mc", .data = &tegra238_mc_soc }, 60 #endif 61 #ifdef CONFIG_ARCH_TEGRA_264_SOC 62 { .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc }, 63 #endif 64 { /* sentinel */ } 65 }; 66 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 67 68 const struct tegra_mc_regs tegra20_mc_regs = { 69 .cfg_channel_enable = 0xdf8, 70 .err_status = 0x08, 71 .err_add = 0x0c, 72 .err_add_hi = 0x11fc, 73 .err_vpr_status = 0x654, 74 .err_vpr_add = 0x658, 75 .err_sec_status = 0x67c, 76 .err_sec_add = 0x680, 77 .err_mts_status = 0x9b0, 78 .err_mts_add = 0x9b4, 79 .err_gen_co_status = 0xc00, 80 .err_gen_co_add = 0xc04, 81 .err_route_status = 0x9c0, 82 .err_route_add = 0x9c4, 83 }; 84 85 static void tegra_mc_devm_action_put_device(void *data) 86 { 87 struct tegra_mc *mc = data; 88 89 put_device(mc->dev); 90 } 91 92 /** 93 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle 94 * @dev: device pointer for the consumer device 95 * 96 * This function will search for the Memory Controller node in a device-tree 97 * and retrieve the Memory Controller handle. 98 * 99 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. 100 */ 101 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) 102 { 103 struct platform_device *pdev; 104 struct device_node *np; 105 struct tegra_mc *mc; 106 int err; 107 108 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); 109 if (!np) 110 return ERR_PTR(-ENOENT); 111 112 pdev = of_find_device_by_node(np); 113 of_node_put(np); 114 if (!pdev) 115 return ERR_PTR(-ENODEV); 116 117 mc = platform_get_drvdata(pdev); 118 if (!mc) { 119 put_device(&pdev->dev); 120 return ERR_PTR(-EPROBE_DEFER); 121 } 122 123 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); 124 if (err) 125 return ERR_PTR(err); 126 127 return mc; 128 } 129 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); 130 131 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) 132 { 133 if (mc->soc->ops && mc->soc->ops->probe_device) 134 return mc->soc->ops->probe_device(mc, dev); 135 136 return 0; 137 } 138 EXPORT_SYMBOL_GPL(tegra_mc_probe_device); 139 140 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, 141 phys_addr_t *base, u64 *size) 142 { 143 u32 offset; 144 145 if (id < 1 || id >= mc->soc->num_carveouts) 146 return -EINVAL; 147 148 if (id < 6) 149 offset = 0xc0c + 0x50 * (id - 1); 150 else 151 offset = 0x2004 + 0x50 * (id - 6); 152 153 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0); 154 #ifdef CONFIG_PHYS_ADDR_T_64BIT 155 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32; 156 #endif 157 158 if (size) 159 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17; 160 161 return 0; 162 } 163 EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info); 164 165 static int tegra_mc_block_dma_common(struct tegra_mc *mc, 166 const struct tegra_mc_reset *rst) 167 { 168 unsigned long flags; 169 u32 value; 170 171 spin_lock_irqsave(&mc->lock, flags); 172 173 value = mc_readl(mc, rst->control) | BIT(rst->bit); 174 mc_writel(mc, value, rst->control); 175 176 spin_unlock_irqrestore(&mc->lock, flags); 177 178 return 0; 179 } 180 181 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, 182 const struct tegra_mc_reset *rst) 183 { 184 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 185 } 186 187 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, 188 const struct tegra_mc_reset *rst) 189 { 190 unsigned long flags; 191 u32 value; 192 193 spin_lock_irqsave(&mc->lock, flags); 194 195 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 196 mc_writel(mc, value, rst->control); 197 198 spin_unlock_irqrestore(&mc->lock, flags); 199 200 return 0; 201 } 202 203 static int tegra_mc_reset_status_common(struct tegra_mc *mc, 204 const struct tegra_mc_reset *rst) 205 { 206 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 207 } 208 209 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { 210 .block_dma = tegra_mc_block_dma_common, 211 .dma_idling = tegra_mc_dma_idling_common, 212 .unblock_dma = tegra_mc_unblock_dma_common, 213 .reset_status = tegra_mc_reset_status_common, 214 }; 215 216 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 217 { 218 return container_of(rcdev, struct tegra_mc, reset); 219 } 220 221 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 222 unsigned long id) 223 { 224 unsigned int i; 225 226 for (i = 0; i < mc->soc->num_resets; i++) 227 if (mc->soc->resets[i].id == id) 228 return &mc->soc->resets[i]; 229 230 return NULL; 231 } 232 233 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 234 unsigned long id) 235 { 236 struct tegra_mc *mc = reset_to_mc(rcdev); 237 const struct tegra_mc_reset_ops *rst_ops; 238 const struct tegra_mc_reset *rst; 239 int retries = 500; 240 int err; 241 242 rst = tegra_mc_reset_find(mc, id); 243 if (!rst) 244 return -ENODEV; 245 246 rst_ops = mc->soc->reset_ops; 247 if (!rst_ops) 248 return -ENODEV; 249 250 /* DMA flushing will fail if reset is already asserted */ 251 if (rst_ops->reset_status) { 252 /* check whether reset is asserted */ 253 if (rst_ops->reset_status(mc, rst)) 254 return 0; 255 } 256 257 if (rst_ops->block_dma) { 258 /* block clients DMA requests */ 259 err = rst_ops->block_dma(mc, rst); 260 if (err) { 261 dev_err(mc->dev, "failed to block %s DMA: %d\n", 262 rst->name, err); 263 return err; 264 } 265 } 266 267 if (rst_ops->dma_idling) { 268 /* wait for completion of the outstanding DMA requests */ 269 while (!rst_ops->dma_idling(mc, rst)) { 270 if (!retries--) { 271 dev_err(mc->dev, "failed to flush %s DMA\n", 272 rst->name); 273 return -EBUSY; 274 } 275 276 usleep_range(10, 100); 277 } 278 } 279 280 if (rst_ops->hotreset_assert) { 281 /* clear clients DMA requests sitting before arbitration */ 282 err = rst_ops->hotreset_assert(mc, rst); 283 if (err) { 284 dev_err(mc->dev, "failed to hot reset %s: %d\n", 285 rst->name, err); 286 return err; 287 } 288 } 289 290 return 0; 291 } 292 293 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 294 unsigned long id) 295 { 296 struct tegra_mc *mc = reset_to_mc(rcdev); 297 const struct tegra_mc_reset_ops *rst_ops; 298 const struct tegra_mc_reset *rst; 299 int err; 300 301 rst = tegra_mc_reset_find(mc, id); 302 if (!rst) 303 return -ENODEV; 304 305 rst_ops = mc->soc->reset_ops; 306 if (!rst_ops) 307 return -ENODEV; 308 309 if (rst_ops->hotreset_deassert) { 310 /* take out client from hot reset */ 311 err = rst_ops->hotreset_deassert(mc, rst); 312 if (err) { 313 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", 314 rst->name, err); 315 return err; 316 } 317 } 318 319 if (rst_ops->unblock_dma) { 320 /* allow new DMA requests to proceed to arbitration */ 321 err = rst_ops->unblock_dma(mc, rst); 322 if (err) { 323 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", 324 rst->name, err); 325 return err; 326 } 327 } 328 329 return 0; 330 } 331 332 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 333 unsigned long id) 334 { 335 struct tegra_mc *mc = reset_to_mc(rcdev); 336 const struct tegra_mc_reset_ops *rst_ops; 337 const struct tegra_mc_reset *rst; 338 339 rst = tegra_mc_reset_find(mc, id); 340 if (!rst) 341 return -ENODEV; 342 343 rst_ops = mc->soc->reset_ops; 344 if (!rst_ops) 345 return -ENODEV; 346 347 return rst_ops->reset_status(mc, rst); 348 } 349 350 static const struct reset_control_ops tegra_mc_reset_ops = { 351 .assert = tegra_mc_hotreset_assert, 352 .deassert = tegra_mc_hotreset_deassert, 353 .status = tegra_mc_hotreset_status, 354 }; 355 356 static int tegra_mc_reset_setup(struct tegra_mc *mc) 357 { 358 int err; 359 360 mc->reset.ops = &tegra_mc_reset_ops; 361 mc->reset.owner = THIS_MODULE; 362 mc->reset.of_node = mc->dev->of_node; 363 mc->reset.of_reset_n_cells = 1; 364 mc->reset.nr_resets = mc->soc->num_resets; 365 366 err = reset_controller_register(&mc->reset); 367 if (err < 0) 368 return err; 369 370 return 0; 371 } 372 373 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 374 { 375 unsigned int i; 376 struct tegra_mc_timing *timing = NULL; 377 378 for (i = 0; i < mc->num_timings; i++) { 379 if (mc->timings[i].rate == rate) { 380 timing = &mc->timings[i]; 381 break; 382 } 383 } 384 385 if (!timing) { 386 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 387 rate); 388 return -EINVAL; 389 } 390 391 for (i = 0; i < mc->soc->num_emem_regs; ++i) 392 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 393 394 return 0; 395 } 396 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); 397 398 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 399 { 400 u8 dram_count; 401 402 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 403 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 404 dram_count++; 405 406 return dram_count; 407 } 408 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); 409 410 const irq_handler_t tegra30_mc_irq_handlers[] = { 411 tegra30_mc_handle_irq 412 }; 413 414 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 415 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 416 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 417 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 418 defined(CONFIG_ARCH_TEGRA_210_SOC) 419 static void tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 420 { 421 unsigned long long tick; 422 unsigned int i; 423 u32 value; 424 425 /* compute the number of MC clock cycles per tick */ 426 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); 427 do_div(tick, NSEC_PER_SEC); 428 429 value = mc_readl(mc, MC_EMEM_ARB_CFG); 430 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 431 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 432 mc_writel(mc, value, MC_EMEM_ARB_CFG); 433 434 /* write latency allowance defaults */ 435 for (i = 0; i < mc->soc->num_clients; i++) { 436 const struct tegra_mc_client *client = &mc->soc->clients[i]; 437 u32 value; 438 439 value = mc_readl(mc, client->regs.la.reg); 440 value &= ~(client->regs.la.mask << client->regs.la.shift); 441 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; 442 mc_writel(mc, value, client->regs.la.reg); 443 } 444 445 /* latch new values */ 446 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 447 } 448 449 static int load_one_timing(struct tegra_mc *mc, 450 struct tegra_mc_timing *timing, 451 struct device_node *node) 452 { 453 int err; 454 u32 tmp; 455 456 err = of_property_read_u32(node, "clock-frequency", &tmp); 457 if (err) { 458 dev_err(mc->dev, 459 "timing %pOFn: failed to read rate\n", node); 460 return err; 461 } 462 463 timing->rate = tmp; 464 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 465 sizeof(u32), GFP_KERNEL); 466 if (!timing->emem_data) 467 return -ENOMEM; 468 469 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 470 timing->emem_data, 471 mc->soc->num_emem_regs); 472 if (err) { 473 dev_err(mc->dev, 474 "timing %pOFn: failed to read EMEM configuration\n", 475 node); 476 return err; 477 } 478 479 return 0; 480 } 481 482 static int load_timings(struct tegra_mc *mc, struct device_node *node) 483 { 484 struct tegra_mc_timing *timing; 485 int child_count = of_get_child_count(node); 486 int i = 0, err; 487 488 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 489 GFP_KERNEL); 490 if (!mc->timings) 491 return -ENOMEM; 492 493 mc->num_timings = child_count; 494 495 for_each_child_of_node_scoped(node, child) { 496 timing = &mc->timings[i++]; 497 498 err = load_one_timing(mc, timing, child); 499 if (err) 500 return err; 501 } 502 503 return 0; 504 } 505 506 static int tegra_mc_setup_timings(struct tegra_mc *mc) 507 { 508 u32 ram_code, node_ram_code; 509 int err; 510 511 ram_code = tegra_read_ram_code(); 512 513 mc->num_timings = 0; 514 515 for_each_child_of_node_scoped(mc->dev->of_node, node) { 516 err = of_property_read_u32(node, "nvidia,ram-code", 517 &node_ram_code); 518 if (err || (node_ram_code != ram_code)) 519 continue; 520 521 err = load_timings(mc, node); 522 if (err) 523 return err; 524 break; 525 } 526 527 if (mc->num_timings == 0) 528 dev_warn(mc->dev, 529 "no memory timings for RAM code %u registered\n", 530 ram_code); 531 532 return 0; 533 } 534 535 int tegra30_mc_probe(struct tegra_mc *mc) 536 { 537 int err; 538 539 mc->clk = devm_clk_get_optional(mc->dev, "mc"); 540 if (IS_ERR(mc->clk)) 541 return dev_err_probe(mc->dev, PTR_ERR(mc->clk), 542 "failed to get MC clock\n"); 543 544 /* ensure that debug features are disabled */ 545 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); 546 547 tegra_mc_setup_latency_allowance(mc); 548 549 err = tegra_mc_setup_timings(mc); 550 if (err < 0) 551 return dev_err_probe(mc->dev, err, "failed to setup timings\n"); 552 553 return 0; 554 } 555 556 const struct tegra_mc_ops tegra30_mc_ops = { 557 .probe = tegra30_mc_probe, 558 }; 559 #endif 560 561 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, 562 unsigned int *mc_channel) 563 { 564 if ((status & mc->soc->ch_intmask) == 0) 565 return -EINVAL; 566 567 *mc_channel = __ffs((status & mc->soc->ch_intmask) >> 568 mc->soc->global_intstatus_channel_shift); 569 570 return 0; 571 } 572 573 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, 574 unsigned int channel) 575 { 576 return BIT(channel) << mc->soc->global_intstatus_channel_shift; 577 } 578 579 irqreturn_t tegra30_mc_handle_irq(int irq, void *data) 580 { 581 struct tegra_mc *mc = data; 582 unsigned int bit, channel; 583 unsigned long status; 584 585 if (mc->soc->num_channels) { 586 u32 global_status; 587 int err; 588 589 global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); 590 err = mc_global_intstatus_to_channel(mc, global_status, &channel); 591 if (err < 0) { 592 dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", 593 global_status); 594 return IRQ_NONE; 595 } 596 597 /* mask all interrupts to avoid flooding */ 598 status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 599 } else { 600 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 601 } 602 603 if (!status) 604 return IRQ_NONE; 605 606 if (!mc->soc->regs) { 607 dev_err_ratelimited(mc->dev, 608 "MC error interrupt 0x%08lx with no error register map, Clearing.\n", 609 status); 610 goto clear; 611 } 612 613 for_each_set_bit(bit, &status, 32) { 614 const char *error = tegra_mc_status_names[bit] ?: "unknown"; 615 const char *client = "unknown", *desc; 616 const char *direction, *secure; 617 u32 status_reg, addr_reg; 618 u32 intmask = BIT(bit); 619 phys_addr_t addr = 0; 620 #ifdef CONFIG_PHYS_ADDR_T_64BIT 621 u32 addr_hi_reg = 0; 622 #endif 623 unsigned int i; 624 char perm[7]; 625 u8 id, type; 626 u32 value; 627 628 switch (intmask) { 629 case MC_INT_DECERR_VPR: 630 status_reg = mc->soc->regs->err_vpr_status; 631 addr_reg = mc->soc->regs->err_vpr_add; 632 break; 633 634 case MC_INT_SECERR_SEC: 635 status_reg = mc->soc->regs->err_sec_status; 636 addr_reg = mc->soc->regs->err_sec_add; 637 break; 638 639 case MC_INT_DECERR_MTS: 640 status_reg = mc->soc->regs->err_mts_status; 641 addr_reg = mc->soc->regs->err_mts_add; 642 break; 643 644 case MC_INT_DECERR_GENERALIZED_CARVEOUT: 645 status_reg = mc->soc->regs->err_gen_co_status; 646 addr_reg = mc->soc->regs->err_gen_co_add; 647 break; 648 649 case MC_INT_DECERR_ROUTE_SANITY: 650 status_reg = mc->soc->regs->err_route_status; 651 addr_reg = mc->soc->regs->err_route_add; 652 break; 653 654 default: 655 status_reg = mc->soc->regs->err_status; 656 addr_reg = mc->soc->regs->err_add; 657 658 #ifdef CONFIG_PHYS_ADDR_T_64BIT 659 if (mc->soc->has_addr_hi_reg) 660 addr_hi_reg = mc->soc->regs->err_add_hi; 661 #endif 662 break; 663 } 664 665 if (mc->soc->num_channels) 666 value = mc_ch_readl(mc, channel, status_reg); 667 else 668 value = mc_readl(mc, status_reg); 669 670 #ifdef CONFIG_PHYS_ADDR_T_64BIT 671 if (mc->soc->num_address_bits > 32) { 672 if (addr_hi_reg) { 673 if (mc->soc->num_channels) 674 addr = mc_ch_readl(mc, channel, addr_hi_reg); 675 else 676 addr = mc_readl(mc, addr_hi_reg); 677 } else if (mc->soc->mc_addr_hi_mask) { 678 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 679 mc->soc->mc_addr_hi_mask); 680 } else { 681 dev_err_ratelimited(mc->dev, "Unable to determine high address!"); 682 return IRQ_NONE; 683 } 684 addr <<= 32; 685 } 686 #endif 687 688 if (value & MC_ERR_STATUS_RW) 689 direction = "write"; 690 else 691 direction = "read"; 692 693 if (value & MC_ERR_STATUS_SECURITY) 694 secure = "secure "; 695 else 696 secure = ""; 697 698 id = value & mc->soc->client_id_mask; 699 700 for (i = 0; i < mc->soc->num_clients; i++) { 701 if (mc->soc->clients[i].id == id) { 702 client = mc->soc->clients[i].name; 703 break; 704 } 705 } 706 707 type = (value & mc->soc->mc_err_status_type_mask) >> 708 MC_ERR_STATUS_TYPE_SHIFT; 709 desc = tegra20_mc_error_names[type]; 710 711 switch (value & mc->soc->mc_err_status_type_mask) { 712 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 713 perm[0] = ' '; 714 perm[1] = '['; 715 716 if (value & MC_ERR_STATUS_READABLE) 717 perm[2] = 'R'; 718 else 719 perm[2] = '-'; 720 721 if (value & MC_ERR_STATUS_WRITABLE) 722 perm[3] = 'W'; 723 else 724 perm[3] = '-'; 725 726 if (value & MC_ERR_STATUS_NONSECURE) 727 perm[4] = '-'; 728 else 729 perm[4] = 'S'; 730 731 perm[5] = ']'; 732 perm[6] = '\0'; 733 break; 734 735 default: 736 perm[0] = '\0'; 737 break; 738 } 739 740 if (mc->soc->num_channels) 741 value = mc_ch_readl(mc, channel, addr_reg); 742 else 743 value = mc_readl(mc, addr_reg); 744 addr |= value; 745 746 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 747 client, secure, direction, &addr, error, 748 desc, perm); 749 } 750 751 clear: 752 /* clear interrupts */ 753 if (mc->soc->num_channels) { 754 mc_ch_writel(mc, channel, status, MC_INTSTATUS); 755 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, 756 mc_channel_to_global_intstatus(mc, channel), 757 MC_GLOBAL_INTSTATUS); 758 } else { 759 mc_writel(mc, status, MC_INTSTATUS); 760 } 761 762 return IRQ_HANDLED; 763 } 764 765 const char *const tegra_mc_status_names[32] = { 766 [ 1] = "External interrupt", 767 [ 6] = "EMEM address decode error", 768 [ 7] = "GART page fault", 769 [ 8] = "Security violation", 770 [ 9] = "EMEM arbitration error", 771 [10] = "Page fault", 772 [11] = "Invalid APB ASID update", 773 [12] = "VPR violation", 774 [13] = "Secure carveout violation", 775 [16] = "MTS carveout violation", 776 [17] = "Generalized carveout violation", 777 [20] = "Route Sanity error", 778 [21] = "GIC_MSI error", 779 }; 780 781 const char *const tegra20_mc_error_names[8] = { 782 [2] = "EMEM decode error", 783 [3] = "TrustZone violation", 784 [4] = "Carveout violation", 785 [6] = "SMMU translation error", 786 }; 787 788 struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data) 789 { 790 struct tegra_mc *mc = icc_provider_to_tegra_mc(data); 791 struct icc_node *node; 792 793 list_for_each_entry(node, &mc->provider.nodes, node_list) { 794 if (tegra_mc_client_id_from_node(node) == spec->args[0]) 795 return node; 796 } 797 798 /* 799 * If a client driver calls devm_of_icc_get() before the MC driver 800 * is probed, then return EPROBE_DEFER to the client driver. 801 */ 802 return ERR_PTR(-EPROBE_DEFER); 803 } 804 805 static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak) 806 { 807 *average = 0; 808 *peak = 0; 809 810 return 0; 811 } 812 813 static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) 814 { 815 return 0; 816 } 817 818 const struct tegra_mc_icc_ops tegra_mc_icc_ops = { 819 .xlate = tegra_mc_icc_xlate, 820 .aggregate = icc_std_aggregate, 821 .get_bw = tegra_mc_icc_get, 822 .set = tegra_mc_icc_set, 823 }; 824 825 /* 826 * Memory Controller (MC) has few Memory Clients that are issuing memory 827 * bandwidth allocation requests to the MC interconnect provider. The MC 828 * provider aggregates the requests and then sends the aggregated request 829 * up to the External Memory Controller (EMC) interconnect provider which 830 * re-configures hardware interface to External Memory (EMEM) in accordance 831 * to the required bandwidth. Each MC interconnect node represents an 832 * individual Memory Client. 833 * 834 * Memory interconnect topology: 835 * 836 * +----+ 837 * +--------+ | | 838 * | TEXSRD +--->+ | 839 * +--------+ | | 840 * | | +-----+ +------+ 841 * ... | MC +--->+ EMC +--->+ EMEM | 842 * | | +-----+ +------+ 843 * +--------+ | | 844 * | DISP.. +--->+ | 845 * +--------+ | | 846 * +----+ 847 */ 848 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) 849 { 850 int node_id = dev_to_node(mc->dev); 851 struct icc_node *node; 852 unsigned int i; 853 int err; 854 855 /* older device-trees don't have interconnect properties */ 856 if (!device_property_present(mc->dev, "#interconnect-cells") || 857 !mc->soc->icc_ops) 858 return 0; 859 860 mc->provider.dev = mc->dev; 861 mc->provider.data = &mc->provider; 862 mc->provider.set = mc->soc->icc_ops->set; 863 mc->provider.aggregate = mc->soc->icc_ops->aggregate; 864 mc->provider.get_bw = mc->soc->icc_ops->get_bw; 865 mc->provider.xlate = mc->soc->icc_ops->xlate; 866 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; 867 868 icc_provider_init(&mc->provider); 869 870 /* create Memory Controller node */ 871 node = tegra_mc_icc_node_create(node_id, TEGRA_ICC_MC); 872 if (IS_ERR(node)) 873 return PTR_ERR(node); 874 875 if (node_id == NUMA_NO_NODE) 876 node->name = "Memory Controller"; 877 else 878 node->name = dev_name(mc->dev); 879 880 icc_node_add(node, &mc->provider); 881 882 /* link Memory Controller to External Memory Controller */ 883 err = tegra_mc_icc_link_create(node, node_id, TEGRA_ICC_EMC); 884 if (err) 885 goto remove_nodes; 886 887 for (i = 0; i < mc->soc->num_clients; i++) { 888 /* create MC client node */ 889 node = tegra_mc_icc_node_create(node_id, mc->soc->clients[i].id); 890 if (IS_ERR(node)) { 891 err = PTR_ERR(node); 892 goto remove_nodes; 893 } 894 895 if (node_id == NUMA_NO_NODE) 896 node->name = mc->soc->clients[i].name; 897 else 898 node->name = devm_kasprintf(mc->dev, GFP_KERNEL, "%d-%s", 899 node_id, mc->soc->clients[i].name); 900 901 icc_node_add(node, &mc->provider); 902 903 /* link Memory Client to Memory Controller */ 904 err = tegra_mc_icc_link_create(node, node_id, TEGRA_ICC_MC); 905 if (err) 906 goto remove_nodes; 907 908 node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); 909 } 910 911 err = icc_provider_register(&mc->provider); 912 if (err) 913 goto remove_nodes; 914 915 return 0; 916 917 remove_nodes: 918 icc_nodes_remove(&mc->provider); 919 920 return err; 921 } 922 923 static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) 924 { 925 unsigned int i; 926 u32 value; 927 928 value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable); 929 if (value <= 0) { 930 mc->num_channels = mc->soc->num_channels; 931 return; 932 } 933 934 for (i = 0; i < 32; i++) { 935 if (value & BIT(i)) 936 mc->num_channels++; 937 } 938 } 939 940 static void tegra_mc_setup_intmask(struct tegra_mc *mc) 941 { 942 unsigned int i; 943 944 for (i = 0; i < mc->soc->num_intmasks; i++) { 945 if (mc->soc->num_channels) 946 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, 947 mc->soc->intmasks[i].reg); 948 else 949 mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); 950 } 951 } 952 953 static int tegra_mc_probe(struct platform_device *pdev) 954 { 955 struct tegra_mc *mc; 956 u64 mask; 957 int err; 958 959 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 960 if (!mc) 961 return -ENOMEM; 962 963 platform_set_drvdata(pdev, mc); 964 spin_lock_init(&mc->lock); 965 mc->soc = of_device_get_match_data(&pdev->dev); 966 mc->dev = &pdev->dev; 967 968 mask = DMA_BIT_MASK(mc->soc->num_address_bits); 969 970 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); 971 if (err < 0) { 972 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 973 return err; 974 } 975 976 /* length of MC tick in nanoseconds */ 977 mc->tick = 30; 978 979 mc->regs = devm_platform_ioremap_resource(pdev, 0); 980 if (IS_ERR(mc->regs)) 981 return PTR_ERR(mc->regs); 982 983 scoped_guard(mutex, &tegra_mc_debugfs_root_lock) { 984 if (!tegra_mc_debugfs_root) 985 tegra_mc_debugfs_root = debugfs_create_dir("mc", NULL); 986 987 if (dev_to_node(mc->dev) == NUMA_NO_NODE) 988 mc->debugfs.root = tegra_mc_debugfs_root; 989 else 990 mc->debugfs.root = debugfs_create_dir(dev_name(mc->dev), 991 tegra_mc_debugfs_root); 992 } 993 994 if (mc->soc->ops && mc->soc->ops->probe) { 995 err = mc->soc->ops->probe(mc); 996 if (err < 0) 997 return err; 998 } 999 1000 tegra_mc_num_channel_enabled(mc); 1001 1002 if (mc->soc->handle_irq) { 1003 unsigned int i; 1004 1005 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); 1006 1007 for (i = 0; i < mc->soc->num_interrupts; i++) { 1008 int irq; 1009 1010 irq = platform_get_irq(pdev, i); 1011 if (irq < 0) 1012 return irq; 1013 1014 err = devm_request_irq(&pdev->dev, irq, mc->soc->handle_irq[i], 0, 1015 dev_name(&pdev->dev), mc); 1016 if (err < 0) { 1017 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 1018 return err; 1019 } 1020 } 1021 1022 tegra_mc_setup_intmask(mc); 1023 } 1024 1025 if (mc->soc->reset_ops) { 1026 err = tegra_mc_reset_setup(mc); 1027 if (err < 0) 1028 dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); 1029 } 1030 1031 err = tegra_mc_interconnect_setup(mc); 1032 if (err < 0) 1033 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", 1034 err); 1035 1036 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 1037 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 1038 if (IS_ERR(mc->smmu)) { 1039 dev_err(&pdev->dev, "failed to probe SMMU: %pe\n", mc->smmu); 1040 mc->smmu = NULL; 1041 } 1042 } 1043 1044 return 0; 1045 } 1046 1047 static void tegra_mc_sync_state(struct device *dev) 1048 { 1049 struct tegra_mc *mc = dev_get_drvdata(dev); 1050 1051 /* check whether ICC provider is registered */ 1052 if (mc->provider.dev == dev) 1053 icc_sync_state(dev); 1054 } 1055 1056 static int tegra_mc_resume(struct device *dev) 1057 { 1058 struct tegra_mc *mc = dev_get_drvdata(dev); 1059 1060 if (mc->soc->ops && mc->soc->ops->resume) 1061 mc->soc->ops->resume(mc); 1062 1063 tegra_mc_setup_intmask(mc); 1064 1065 return 0; 1066 } 1067 1068 static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume); 1069 1070 static struct platform_driver tegra_mc_driver = { 1071 .driver = { 1072 .name = "tegra-mc", 1073 .of_match_table = tegra_mc_of_match, 1074 .pm = pm_sleep_ptr(&tegra_mc_pm_ops), 1075 .suppress_bind_attrs = true, 1076 .sync_state = tegra_mc_sync_state, 1077 }, 1078 .prevent_deferred_probe = true, 1079 .probe = tegra_mc_probe, 1080 }; 1081 1082 static int tegra_mc_init(void) 1083 { 1084 return platform_driver_register(&tegra_mc_driver); 1085 } 1086 arch_initcall(tegra_mc_init); 1087 1088 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1089 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 1090