1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/export.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm.h> 17 #include <linux/slab.h> 18 #include <linux/sort.h> 19 #include <linux/tegra-icc.h> 20 21 #include <soc/tegra/fuse.h> 22 23 #include "mc.h" 24 25 static const struct of_device_id tegra_mc_of_match[] = { 26 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 27 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 28 #endif 29 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 30 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 31 #endif 32 #ifdef CONFIG_ARCH_TEGRA_114_SOC 33 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 34 #endif 35 #ifdef CONFIG_ARCH_TEGRA_124_SOC 36 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 37 #endif 38 #ifdef CONFIG_ARCH_TEGRA_132_SOC 39 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 40 #endif 41 #ifdef CONFIG_ARCH_TEGRA_210_SOC 42 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 43 #endif 44 #ifdef CONFIG_ARCH_TEGRA_186_SOC 45 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, 46 #endif 47 #ifdef CONFIG_ARCH_TEGRA_194_SOC 48 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, 49 #endif 50 #ifdef CONFIG_ARCH_TEGRA_234_SOC 51 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc }, 52 #endif 53 #ifdef CONFIG_ARCH_TEGRA_238_SOC 54 { .compatible = "nvidia,tegra238-mc", .data = &tegra238_mc_soc }, 55 #endif 56 #ifdef CONFIG_ARCH_TEGRA_264_SOC 57 { .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc }, 58 #endif 59 { /* sentinel */ } 60 }; 61 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 62 63 const struct tegra_mc_regs tegra20_mc_regs = { 64 .cfg_channel_enable = 0xdf8, 65 .err_status = 0x08, 66 .err_add = 0x0c, 67 .err_add_hi = 0x11fc, 68 .err_vpr_status = 0x654, 69 .err_vpr_add = 0x658, 70 .err_sec_status = 0x67c, 71 .err_sec_add = 0x680, 72 .err_mts_status = 0x9b0, 73 .err_mts_add = 0x9b4, 74 .err_gen_co_status = 0xc00, 75 .err_gen_co_add = 0xc04, 76 .err_route_status = 0x9c0, 77 .err_route_add = 0x9c4, 78 }; 79 80 static void tegra_mc_devm_action_put_device(void *data) 81 { 82 struct tegra_mc *mc = data; 83 84 put_device(mc->dev); 85 } 86 87 /** 88 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle 89 * @dev: device pointer for the consumer device 90 * 91 * This function will search for the Memory Controller node in a device-tree 92 * and retrieve the Memory Controller handle. 93 * 94 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. 95 */ 96 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) 97 { 98 struct platform_device *pdev; 99 struct device_node *np; 100 struct tegra_mc *mc; 101 int err; 102 103 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); 104 if (!np) 105 return ERR_PTR(-ENOENT); 106 107 pdev = of_find_device_by_node(np); 108 of_node_put(np); 109 if (!pdev) 110 return ERR_PTR(-ENODEV); 111 112 mc = platform_get_drvdata(pdev); 113 if (!mc) { 114 put_device(&pdev->dev); 115 return ERR_PTR(-EPROBE_DEFER); 116 } 117 118 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); 119 if (err) 120 return ERR_PTR(err); 121 122 return mc; 123 } 124 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); 125 126 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) 127 { 128 if (mc->soc->ops && mc->soc->ops->probe_device) 129 return mc->soc->ops->probe_device(mc, dev); 130 131 return 0; 132 } 133 EXPORT_SYMBOL_GPL(tegra_mc_probe_device); 134 135 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, 136 phys_addr_t *base, u64 *size) 137 { 138 u32 offset; 139 140 if (id < 1 || id >= mc->soc->num_carveouts) 141 return -EINVAL; 142 143 if (id < 6) 144 offset = 0xc0c + 0x50 * (id - 1); 145 else 146 offset = 0x2004 + 0x50 * (id - 6); 147 148 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0); 149 #ifdef CONFIG_PHYS_ADDR_T_64BIT 150 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32; 151 #endif 152 153 if (size) 154 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17; 155 156 return 0; 157 } 158 EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info); 159 160 static int tegra_mc_block_dma_common(struct tegra_mc *mc, 161 const struct tegra_mc_reset *rst) 162 { 163 unsigned long flags; 164 u32 value; 165 166 spin_lock_irqsave(&mc->lock, flags); 167 168 value = mc_readl(mc, rst->control) | BIT(rst->bit); 169 mc_writel(mc, value, rst->control); 170 171 spin_unlock_irqrestore(&mc->lock, flags); 172 173 return 0; 174 } 175 176 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, 177 const struct tegra_mc_reset *rst) 178 { 179 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 180 } 181 182 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, 183 const struct tegra_mc_reset *rst) 184 { 185 unsigned long flags; 186 u32 value; 187 188 spin_lock_irqsave(&mc->lock, flags); 189 190 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 191 mc_writel(mc, value, rst->control); 192 193 spin_unlock_irqrestore(&mc->lock, flags); 194 195 return 0; 196 } 197 198 static int tegra_mc_reset_status_common(struct tegra_mc *mc, 199 const struct tegra_mc_reset *rst) 200 { 201 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 202 } 203 204 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { 205 .block_dma = tegra_mc_block_dma_common, 206 .dma_idling = tegra_mc_dma_idling_common, 207 .unblock_dma = tegra_mc_unblock_dma_common, 208 .reset_status = tegra_mc_reset_status_common, 209 }; 210 211 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 212 { 213 return container_of(rcdev, struct tegra_mc, reset); 214 } 215 216 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 217 unsigned long id) 218 { 219 unsigned int i; 220 221 for (i = 0; i < mc->soc->num_resets; i++) 222 if (mc->soc->resets[i].id == id) 223 return &mc->soc->resets[i]; 224 225 return NULL; 226 } 227 228 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 229 unsigned long id) 230 { 231 struct tegra_mc *mc = reset_to_mc(rcdev); 232 const struct tegra_mc_reset_ops *rst_ops; 233 const struct tegra_mc_reset *rst; 234 int retries = 500; 235 int err; 236 237 rst = tegra_mc_reset_find(mc, id); 238 if (!rst) 239 return -ENODEV; 240 241 rst_ops = mc->soc->reset_ops; 242 if (!rst_ops) 243 return -ENODEV; 244 245 /* DMA flushing will fail if reset is already asserted */ 246 if (rst_ops->reset_status) { 247 /* check whether reset is asserted */ 248 if (rst_ops->reset_status(mc, rst)) 249 return 0; 250 } 251 252 if (rst_ops->block_dma) { 253 /* block clients DMA requests */ 254 err = rst_ops->block_dma(mc, rst); 255 if (err) { 256 dev_err(mc->dev, "failed to block %s DMA: %d\n", 257 rst->name, err); 258 return err; 259 } 260 } 261 262 if (rst_ops->dma_idling) { 263 /* wait for completion of the outstanding DMA requests */ 264 while (!rst_ops->dma_idling(mc, rst)) { 265 if (!retries--) { 266 dev_err(mc->dev, "failed to flush %s DMA\n", 267 rst->name); 268 return -EBUSY; 269 } 270 271 usleep_range(10, 100); 272 } 273 } 274 275 if (rst_ops->hotreset_assert) { 276 /* clear clients DMA requests sitting before arbitration */ 277 err = rst_ops->hotreset_assert(mc, rst); 278 if (err) { 279 dev_err(mc->dev, "failed to hot reset %s: %d\n", 280 rst->name, err); 281 return err; 282 } 283 } 284 285 return 0; 286 } 287 288 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 289 unsigned long id) 290 { 291 struct tegra_mc *mc = reset_to_mc(rcdev); 292 const struct tegra_mc_reset_ops *rst_ops; 293 const struct tegra_mc_reset *rst; 294 int err; 295 296 rst = tegra_mc_reset_find(mc, id); 297 if (!rst) 298 return -ENODEV; 299 300 rst_ops = mc->soc->reset_ops; 301 if (!rst_ops) 302 return -ENODEV; 303 304 if (rst_ops->hotreset_deassert) { 305 /* take out client from hot reset */ 306 err = rst_ops->hotreset_deassert(mc, rst); 307 if (err) { 308 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", 309 rst->name, err); 310 return err; 311 } 312 } 313 314 if (rst_ops->unblock_dma) { 315 /* allow new DMA requests to proceed to arbitration */ 316 err = rst_ops->unblock_dma(mc, rst); 317 if (err) { 318 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", 319 rst->name, err); 320 return err; 321 } 322 } 323 324 return 0; 325 } 326 327 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 328 unsigned long id) 329 { 330 struct tegra_mc *mc = reset_to_mc(rcdev); 331 const struct tegra_mc_reset_ops *rst_ops; 332 const struct tegra_mc_reset *rst; 333 334 rst = tegra_mc_reset_find(mc, id); 335 if (!rst) 336 return -ENODEV; 337 338 rst_ops = mc->soc->reset_ops; 339 if (!rst_ops) 340 return -ENODEV; 341 342 return rst_ops->reset_status(mc, rst); 343 } 344 345 static const struct reset_control_ops tegra_mc_reset_ops = { 346 .assert = tegra_mc_hotreset_assert, 347 .deassert = tegra_mc_hotreset_deassert, 348 .status = tegra_mc_hotreset_status, 349 }; 350 351 static int tegra_mc_reset_setup(struct tegra_mc *mc) 352 { 353 int err; 354 355 mc->reset.ops = &tegra_mc_reset_ops; 356 mc->reset.owner = THIS_MODULE; 357 mc->reset.of_node = mc->dev->of_node; 358 mc->reset.of_reset_n_cells = 1; 359 mc->reset.nr_resets = mc->soc->num_resets; 360 361 err = reset_controller_register(&mc->reset); 362 if (err < 0) 363 return err; 364 365 return 0; 366 } 367 368 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 369 { 370 unsigned int i; 371 struct tegra_mc_timing *timing = NULL; 372 373 for (i = 0; i < mc->num_timings; i++) { 374 if (mc->timings[i].rate == rate) { 375 timing = &mc->timings[i]; 376 break; 377 } 378 } 379 380 if (!timing) { 381 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 382 rate); 383 return -EINVAL; 384 } 385 386 for (i = 0; i < mc->soc->num_emem_regs; ++i) 387 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 388 389 return 0; 390 } 391 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); 392 393 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 394 { 395 u8 dram_count; 396 397 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 398 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 399 dram_count++; 400 401 return dram_count; 402 } 403 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); 404 405 const irq_handler_t tegra30_mc_irq_handlers[] = { 406 tegra30_mc_handle_irq 407 }; 408 409 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 410 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 411 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 412 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 413 defined(CONFIG_ARCH_TEGRA_210_SOC) 414 static void tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 415 { 416 unsigned long long tick; 417 unsigned int i; 418 u32 value; 419 420 /* compute the number of MC clock cycles per tick */ 421 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); 422 do_div(tick, NSEC_PER_SEC); 423 424 value = mc_readl(mc, MC_EMEM_ARB_CFG); 425 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 426 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 427 mc_writel(mc, value, MC_EMEM_ARB_CFG); 428 429 /* write latency allowance defaults */ 430 for (i = 0; i < mc->soc->num_clients; i++) { 431 const struct tegra_mc_client *client = &mc->soc->clients[i]; 432 u32 value; 433 434 value = mc_readl(mc, client->regs.la.reg); 435 value &= ~(client->regs.la.mask << client->regs.la.shift); 436 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; 437 mc_writel(mc, value, client->regs.la.reg); 438 } 439 440 /* latch new values */ 441 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 442 } 443 444 static int load_one_timing(struct tegra_mc *mc, 445 struct tegra_mc_timing *timing, 446 struct device_node *node) 447 { 448 int err; 449 u32 tmp; 450 451 err = of_property_read_u32(node, "clock-frequency", &tmp); 452 if (err) { 453 dev_err(mc->dev, 454 "timing %pOFn: failed to read rate\n", node); 455 return err; 456 } 457 458 timing->rate = tmp; 459 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 460 sizeof(u32), GFP_KERNEL); 461 if (!timing->emem_data) 462 return -ENOMEM; 463 464 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 465 timing->emem_data, 466 mc->soc->num_emem_regs); 467 if (err) { 468 dev_err(mc->dev, 469 "timing %pOFn: failed to read EMEM configuration\n", 470 node); 471 return err; 472 } 473 474 return 0; 475 } 476 477 static int load_timings(struct tegra_mc *mc, struct device_node *node) 478 { 479 struct tegra_mc_timing *timing; 480 int child_count = of_get_child_count(node); 481 int i = 0, err; 482 483 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing), 484 GFP_KERNEL); 485 if (!mc->timings) 486 return -ENOMEM; 487 488 mc->num_timings = child_count; 489 490 for_each_child_of_node_scoped(node, child) { 491 timing = &mc->timings[i++]; 492 493 err = load_one_timing(mc, timing, child); 494 if (err) 495 return err; 496 } 497 498 return 0; 499 } 500 501 static int tegra_mc_setup_timings(struct tegra_mc *mc) 502 { 503 u32 ram_code, node_ram_code; 504 int err; 505 506 ram_code = tegra_read_ram_code(); 507 508 mc->num_timings = 0; 509 510 for_each_child_of_node_scoped(mc->dev->of_node, node) { 511 err = of_property_read_u32(node, "nvidia,ram-code", 512 &node_ram_code); 513 if (err || (node_ram_code != ram_code)) 514 continue; 515 516 err = load_timings(mc, node); 517 if (err) 518 return err; 519 break; 520 } 521 522 if (mc->num_timings == 0) 523 dev_warn(mc->dev, 524 "no memory timings for RAM code %u registered\n", 525 ram_code); 526 527 return 0; 528 } 529 530 int tegra30_mc_probe(struct tegra_mc *mc) 531 { 532 int err; 533 534 mc->clk = devm_clk_get_optional(mc->dev, "mc"); 535 if (IS_ERR(mc->clk)) 536 return dev_err_probe(mc->dev, PTR_ERR(mc->clk), 537 "failed to get MC clock\n"); 538 539 /* ensure that debug features are disabled */ 540 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); 541 542 tegra_mc_setup_latency_allowance(mc); 543 544 err = tegra_mc_setup_timings(mc); 545 if (err < 0) 546 return dev_err_probe(mc->dev, err, "failed to setup timings\n"); 547 548 return 0; 549 } 550 551 const struct tegra_mc_ops tegra30_mc_ops = { 552 .probe = tegra30_mc_probe, 553 }; 554 #endif 555 556 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, 557 unsigned int *mc_channel) 558 { 559 if ((status & mc->soc->ch_intmask) == 0) 560 return -EINVAL; 561 562 *mc_channel = __ffs((status & mc->soc->ch_intmask) >> 563 mc->soc->global_intstatus_channel_shift); 564 565 return 0; 566 } 567 568 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, 569 unsigned int channel) 570 { 571 return BIT(channel) << mc->soc->global_intstatus_channel_shift; 572 } 573 574 irqreturn_t tegra30_mc_handle_irq(int irq, void *data) 575 { 576 struct tegra_mc *mc = data; 577 unsigned int bit, channel; 578 unsigned long status; 579 580 if (mc->soc->num_channels) { 581 u32 global_status; 582 int err; 583 584 global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); 585 err = mc_global_intstatus_to_channel(mc, global_status, &channel); 586 if (err < 0) { 587 dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", 588 global_status); 589 return IRQ_NONE; 590 } 591 592 /* mask all interrupts to avoid flooding */ 593 status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 594 } else { 595 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 596 } 597 598 if (!status) 599 return IRQ_NONE; 600 601 for_each_set_bit(bit, &status, 32) { 602 const char *error = tegra_mc_status_names[bit] ?: "unknown"; 603 const char *client = "unknown", *desc; 604 const char *direction, *secure; 605 u32 status_reg, addr_reg; 606 u32 intmask = BIT(bit); 607 phys_addr_t addr = 0; 608 #ifdef CONFIG_PHYS_ADDR_T_64BIT 609 u32 addr_hi_reg = 0; 610 #endif 611 unsigned int i; 612 char perm[7]; 613 u8 id, type; 614 u32 value; 615 616 switch (intmask) { 617 case MC_INT_DECERR_VPR: 618 status_reg = mc->soc->regs->err_vpr_status; 619 addr_reg = mc->soc->regs->err_vpr_add; 620 break; 621 622 case MC_INT_SECERR_SEC: 623 status_reg = mc->soc->regs->err_sec_status; 624 addr_reg = mc->soc->regs->err_sec_add; 625 break; 626 627 case MC_INT_DECERR_MTS: 628 status_reg = mc->soc->regs->err_mts_status; 629 addr_reg = mc->soc->regs->err_mts_add; 630 break; 631 632 case MC_INT_DECERR_GENERALIZED_CARVEOUT: 633 status_reg = mc->soc->regs->err_gen_co_status; 634 addr_reg = mc->soc->regs->err_gen_co_add; 635 break; 636 637 case MC_INT_DECERR_ROUTE_SANITY: 638 status_reg = mc->soc->regs->err_route_status; 639 addr_reg = mc->soc->regs->err_route_add; 640 break; 641 642 default: 643 status_reg = mc->soc->regs->err_status; 644 addr_reg = mc->soc->regs->err_add; 645 646 #ifdef CONFIG_PHYS_ADDR_T_64BIT 647 if (mc->soc->has_addr_hi_reg) 648 addr_hi_reg = mc->soc->regs->err_add_hi; 649 #endif 650 break; 651 } 652 653 if (mc->soc->num_channels) 654 value = mc_ch_readl(mc, channel, status_reg); 655 else 656 value = mc_readl(mc, status_reg); 657 658 #ifdef CONFIG_PHYS_ADDR_T_64BIT 659 if (mc->soc->num_address_bits > 32) { 660 if (addr_hi_reg) { 661 if (mc->soc->num_channels) 662 addr = mc_ch_readl(mc, channel, addr_hi_reg); 663 else 664 addr = mc_readl(mc, addr_hi_reg); 665 } else if (mc->soc->mc_addr_hi_mask) { 666 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 667 mc->soc->mc_addr_hi_mask); 668 } else { 669 dev_err_ratelimited(mc->dev, "Unable to determine high address!"); 670 return IRQ_NONE; 671 } 672 addr <<= 32; 673 } 674 #endif 675 676 if (value & MC_ERR_STATUS_RW) 677 direction = "write"; 678 else 679 direction = "read"; 680 681 if (value & MC_ERR_STATUS_SECURITY) 682 secure = "secure "; 683 else 684 secure = ""; 685 686 id = value & mc->soc->client_id_mask; 687 688 for (i = 0; i < mc->soc->num_clients; i++) { 689 if (mc->soc->clients[i].id == id) { 690 client = mc->soc->clients[i].name; 691 break; 692 } 693 } 694 695 type = (value & mc->soc->mc_err_status_type_mask) >> 696 MC_ERR_STATUS_TYPE_SHIFT; 697 desc = tegra20_mc_error_names[type]; 698 699 switch (value & mc->soc->mc_err_status_type_mask) { 700 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 701 perm[0] = ' '; 702 perm[1] = '['; 703 704 if (value & MC_ERR_STATUS_READABLE) 705 perm[2] = 'R'; 706 else 707 perm[2] = '-'; 708 709 if (value & MC_ERR_STATUS_WRITABLE) 710 perm[3] = 'W'; 711 else 712 perm[3] = '-'; 713 714 if (value & MC_ERR_STATUS_NONSECURE) 715 perm[4] = '-'; 716 else 717 perm[4] = 'S'; 718 719 perm[5] = ']'; 720 perm[6] = '\0'; 721 break; 722 723 default: 724 perm[0] = '\0'; 725 break; 726 } 727 728 if (mc->soc->num_channels) 729 value = mc_ch_readl(mc, channel, addr_reg); 730 else 731 value = mc_readl(mc, addr_reg); 732 addr |= value; 733 734 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 735 client, secure, direction, &addr, error, 736 desc, perm); 737 } 738 739 /* clear interrupts */ 740 if (mc->soc->num_channels) { 741 mc_ch_writel(mc, channel, status, MC_INTSTATUS); 742 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, 743 mc_channel_to_global_intstatus(mc, channel), 744 MC_GLOBAL_INTSTATUS); 745 } else { 746 mc_writel(mc, status, MC_INTSTATUS); 747 } 748 749 return IRQ_HANDLED; 750 } 751 752 const char *const tegra_mc_status_names[32] = { 753 [ 1] = "External interrupt", 754 [ 6] = "EMEM address decode error", 755 [ 7] = "GART page fault", 756 [ 8] = "Security violation", 757 [ 9] = "EMEM arbitration error", 758 [10] = "Page fault", 759 [11] = "Invalid APB ASID update", 760 [12] = "VPR violation", 761 [13] = "Secure carveout violation", 762 [16] = "MTS carveout violation", 763 [17] = "Generalized carveout violation", 764 [20] = "Route Sanity error", 765 [21] = "GIC_MSI error", 766 }; 767 768 const char *const tegra20_mc_error_names[8] = { 769 [2] = "EMEM decode error", 770 [3] = "TrustZone violation", 771 [4] = "Carveout violation", 772 [6] = "SMMU translation error", 773 }; 774 775 struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data) 776 { 777 struct tegra_mc *mc = icc_provider_to_tegra_mc(data); 778 struct icc_node *node; 779 780 list_for_each_entry(node, &mc->provider.nodes, node_list) { 781 if (node->id == spec->args[0]) 782 return node; 783 } 784 785 /* 786 * If a client driver calls devm_of_icc_get() before the MC driver 787 * is probed, then return EPROBE_DEFER to the client driver. 788 */ 789 return ERR_PTR(-EPROBE_DEFER); 790 } 791 792 static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak) 793 { 794 *average = 0; 795 *peak = 0; 796 797 return 0; 798 } 799 800 static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) 801 { 802 return 0; 803 } 804 805 const struct tegra_mc_icc_ops tegra_mc_icc_ops = { 806 .xlate = tegra_mc_icc_xlate, 807 .aggregate = icc_std_aggregate, 808 .get_bw = tegra_mc_icc_get, 809 .set = tegra_mc_icc_set, 810 }; 811 812 /* 813 * Memory Controller (MC) has few Memory Clients that are issuing memory 814 * bandwidth allocation requests to the MC interconnect provider. The MC 815 * provider aggregates the requests and then sends the aggregated request 816 * up to the External Memory Controller (EMC) interconnect provider which 817 * re-configures hardware interface to External Memory (EMEM) in accordance 818 * to the required bandwidth. Each MC interconnect node represents an 819 * individual Memory Client. 820 * 821 * Memory interconnect topology: 822 * 823 * +----+ 824 * +--------+ | | 825 * | TEXSRD +--->+ | 826 * +--------+ | | 827 * | | +-----+ +------+ 828 * ... | MC +--->+ EMC +--->+ EMEM | 829 * | | +-----+ +------+ 830 * +--------+ | | 831 * | DISP.. +--->+ | 832 * +--------+ | | 833 * +----+ 834 */ 835 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) 836 { 837 struct icc_node *node; 838 unsigned int i; 839 int err; 840 841 /* older device-trees don't have interconnect properties */ 842 if (!device_property_present(mc->dev, "#interconnect-cells") || 843 !mc->soc->icc_ops) 844 return 0; 845 846 mc->provider.dev = mc->dev; 847 mc->provider.data = &mc->provider; 848 mc->provider.set = mc->soc->icc_ops->set; 849 mc->provider.aggregate = mc->soc->icc_ops->aggregate; 850 mc->provider.get_bw = mc->soc->icc_ops->get_bw; 851 mc->provider.xlate = mc->soc->icc_ops->xlate; 852 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; 853 854 icc_provider_init(&mc->provider); 855 856 /* create Memory Controller node */ 857 node = icc_node_create(TEGRA_ICC_MC); 858 if (IS_ERR(node)) 859 return PTR_ERR(node); 860 861 node->name = "Memory Controller"; 862 icc_node_add(node, &mc->provider); 863 864 /* link Memory Controller to External Memory Controller */ 865 err = icc_link_create(node, TEGRA_ICC_EMC); 866 if (err) 867 goto remove_nodes; 868 869 for (i = 0; i < mc->soc->num_clients; i++) { 870 /* create MC client node */ 871 node = icc_node_create(mc->soc->clients[i].id); 872 if (IS_ERR(node)) { 873 err = PTR_ERR(node); 874 goto remove_nodes; 875 } 876 877 node->name = mc->soc->clients[i].name; 878 icc_node_add(node, &mc->provider); 879 880 /* link Memory Client to Memory Controller */ 881 err = icc_link_create(node, TEGRA_ICC_MC); 882 if (err) 883 goto remove_nodes; 884 885 node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); 886 } 887 888 err = icc_provider_register(&mc->provider); 889 if (err) 890 goto remove_nodes; 891 892 return 0; 893 894 remove_nodes: 895 icc_nodes_remove(&mc->provider); 896 897 return err; 898 } 899 900 static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) 901 { 902 unsigned int i; 903 u32 value; 904 905 value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable); 906 if (value <= 0) { 907 mc->num_channels = mc->soc->num_channels; 908 return; 909 } 910 911 for (i = 0; i < 32; i++) { 912 if (value & BIT(i)) 913 mc->num_channels++; 914 } 915 } 916 917 static void tegra_mc_setup_intmask(struct tegra_mc *mc) 918 { 919 unsigned int i; 920 921 for (i = 0; i < mc->soc->num_intmasks; i++) { 922 if (mc->soc->num_channels) 923 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, 924 mc->soc->intmasks[i].reg); 925 else 926 mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); 927 } 928 } 929 930 static int tegra_mc_probe(struct platform_device *pdev) 931 { 932 struct tegra_mc *mc; 933 u64 mask; 934 int err; 935 936 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL); 937 if (!mc) 938 return -ENOMEM; 939 940 platform_set_drvdata(pdev, mc); 941 spin_lock_init(&mc->lock); 942 mc->soc = of_device_get_match_data(&pdev->dev); 943 mc->dev = &pdev->dev; 944 945 mask = DMA_BIT_MASK(mc->soc->num_address_bits); 946 947 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); 948 if (err < 0) { 949 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 950 return err; 951 } 952 953 /* length of MC tick in nanoseconds */ 954 mc->tick = 30; 955 956 mc->regs = devm_platform_ioremap_resource(pdev, 0); 957 if (IS_ERR(mc->regs)) 958 return PTR_ERR(mc->regs); 959 960 mc->debugfs.root = debugfs_create_dir("mc", NULL); 961 962 if (mc->soc->ops && mc->soc->ops->probe) { 963 err = mc->soc->ops->probe(mc); 964 if (err < 0) 965 return err; 966 } 967 968 tegra_mc_num_channel_enabled(mc); 969 970 if (mc->soc->handle_irq) { 971 unsigned int i; 972 973 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); 974 975 for (i = 0; i < mc->soc->num_interrupts; i++) { 976 int irq; 977 978 irq = platform_get_irq(pdev, i); 979 if (irq < 0) 980 return irq; 981 982 err = devm_request_irq(&pdev->dev, irq, mc->soc->handle_irq[i], 0, 983 dev_name(&pdev->dev), mc); 984 if (err < 0) { 985 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 986 return err; 987 } 988 } 989 990 tegra_mc_setup_intmask(mc); 991 } 992 993 if (mc->soc->reset_ops) { 994 err = tegra_mc_reset_setup(mc); 995 if (err < 0) 996 dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); 997 } 998 999 err = tegra_mc_interconnect_setup(mc); 1000 if (err < 0) 1001 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", 1002 err); 1003 1004 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 1005 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 1006 if (IS_ERR(mc->smmu)) { 1007 dev_err(&pdev->dev, "failed to probe SMMU: %pe\n", mc->smmu); 1008 mc->smmu = NULL; 1009 } 1010 } 1011 1012 return 0; 1013 } 1014 1015 static void tegra_mc_sync_state(struct device *dev) 1016 { 1017 struct tegra_mc *mc = dev_get_drvdata(dev); 1018 1019 /* check whether ICC provider is registered */ 1020 if (mc->provider.dev == dev) 1021 icc_sync_state(dev); 1022 } 1023 1024 static int tegra_mc_resume(struct device *dev) 1025 { 1026 struct tegra_mc *mc = dev_get_drvdata(dev); 1027 1028 if (mc->soc->ops && mc->soc->ops->resume) 1029 mc->soc->ops->resume(mc); 1030 1031 tegra_mc_setup_intmask(mc); 1032 1033 return 0; 1034 } 1035 1036 static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume); 1037 1038 static struct platform_driver tegra_mc_driver = { 1039 .driver = { 1040 .name = "tegra-mc", 1041 .of_match_table = tegra_mc_of_match, 1042 .pm = pm_sleep_ptr(&tegra_mc_pm_ops), 1043 .suppress_bind_attrs = true, 1044 .sync_state = tegra_mc_sync_state, 1045 }, 1046 .prevent_deferred_probe = true, 1047 .probe = tegra_mc_probe, 1048 }; 1049 1050 static int tegra_mc_init(void) 1051 { 1052 return platform_driver_register(&tegra_mc_driver); 1053 } 1054 arch_initcall(tegra_mc_init); 1055 1056 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1057 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 1058