1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2014-2026 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6 #include <linux/cleanup.h> 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/export.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/of.h> 16 #include <linux/of_platform.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm.h> 19 #include <linux/slab.h> 20 #include <linux/sort.h> 21 #include <linux/tegra-icc.h> 22 23 #include <soc/tegra/fuse.h> 24 25 #include "mc.h" 26 27 static DEFINE_MUTEX(tegra_mc_debugfs_root_lock); 28 static struct dentry *tegra_mc_debugfs_root; 29 30 static const struct of_device_id tegra_mc_of_match[] = { 31 #ifdef CONFIG_ARCH_TEGRA_2x_SOC 32 { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc }, 33 #endif 34 #ifdef CONFIG_ARCH_TEGRA_3x_SOC 35 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 36 #endif 37 #ifdef CONFIG_ARCH_TEGRA_114_SOC 38 { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc }, 39 #endif 40 #ifdef CONFIG_ARCH_TEGRA_124_SOC 41 { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc }, 42 #endif 43 #ifdef CONFIG_ARCH_TEGRA_132_SOC 44 { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc }, 45 #endif 46 #ifdef CONFIG_ARCH_TEGRA_210_SOC 47 { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc }, 48 #endif 49 #ifdef CONFIG_ARCH_TEGRA_186_SOC 50 { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc }, 51 #endif 52 #ifdef CONFIG_ARCH_TEGRA_194_SOC 53 { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc }, 54 #endif 55 #ifdef CONFIG_ARCH_TEGRA_234_SOC 56 { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc }, 57 #endif 58 #ifdef CONFIG_ARCH_TEGRA_238_SOC 59 { .compatible = "nvidia,tegra238-mc", .data = &tegra238_mc_soc }, 60 #endif 61 #ifdef CONFIG_ARCH_TEGRA_264_SOC 62 { .compatible = "nvidia,tegra264-mc", .data = &tegra264_mc_soc }, 63 #endif 64 { /* sentinel */ } 65 }; 66 MODULE_DEVICE_TABLE(of, tegra_mc_of_match); 67 68 const struct tegra_mc_regs tegra20_mc_regs = { 69 .cfg_channel_enable = 0xdf8, 70 .err_status = 0x08, 71 .err_add = 0x0c, 72 .err_add_hi = 0x11fc, 73 .err_vpr_status = 0x654, 74 .err_vpr_add = 0x658, 75 .err_sec_status = 0x67c, 76 .err_sec_add = 0x680, 77 .err_mts_status = 0x9b0, 78 .err_mts_add = 0x9b4, 79 .err_gen_co_status = 0xc00, 80 .err_gen_co_add = 0xc04, 81 .err_route_status = 0x9c0, 82 .err_route_add = 0x9c4, 83 }; 84 85 static void tegra_mc_devm_action_put_device(void *data) 86 { 87 struct tegra_mc *mc = data; 88 89 put_device(mc->dev); 90 } 91 92 /** 93 * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle 94 * @dev: device pointer for the consumer device 95 * 96 * This function will search for the Memory Controller node in a device-tree 97 * and retrieve the Memory Controller handle. 98 * 99 * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc. 100 */ 101 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev) 102 { 103 struct platform_device *pdev; 104 struct device_node *np; 105 struct tegra_mc *mc; 106 int err; 107 108 np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0); 109 if (!np) 110 return ERR_PTR(-ENOENT); 111 112 pdev = of_find_device_by_node(np); 113 of_node_put(np); 114 if (!pdev) 115 return ERR_PTR(-ENODEV); 116 117 mc = platform_get_drvdata(pdev); 118 if (!mc) { 119 put_device(&pdev->dev); 120 return ERR_PTR(-EPROBE_DEFER); 121 } 122 123 err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc); 124 if (err) 125 return ERR_PTR(err); 126 127 return mc; 128 } 129 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get); 130 131 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev) 132 { 133 if (mc->soc->ops && mc->soc->ops->probe_device) 134 return mc->soc->ops->probe_device(mc, dev); 135 136 return 0; 137 } 138 EXPORT_SYMBOL_GPL(tegra_mc_probe_device); 139 140 int tegra_mc_get_carveout_info(struct tegra_mc *mc, unsigned int id, 141 phys_addr_t *base, u64 *size) 142 { 143 u32 offset; 144 145 if (id < 1 || id >= mc->soc->num_carveouts) 146 return -EINVAL; 147 148 if (id < 6) 149 offset = 0xc0c + 0x50 * (id - 1); 150 else 151 offset = 0x2004 + 0x50 * (id - 6); 152 153 *base = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x0); 154 #ifdef CONFIG_PHYS_ADDR_T_64BIT 155 *base |= (phys_addr_t)mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x4) << 32; 156 #endif 157 158 if (size) 159 *size = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, offset + 0x8) << 17; 160 161 return 0; 162 } 163 EXPORT_SYMBOL_GPL(tegra_mc_get_carveout_info); 164 165 static int tegra_mc_block_dma_common(struct tegra_mc *mc, 166 const struct tegra_mc_reset *rst) 167 { 168 unsigned long flags; 169 u32 value; 170 171 spin_lock_irqsave(&mc->lock, flags); 172 173 value = mc_readl(mc, rst->control) | BIT(rst->bit); 174 mc_writel(mc, value, rst->control); 175 176 spin_unlock_irqrestore(&mc->lock, flags); 177 178 return 0; 179 } 180 181 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc, 182 const struct tegra_mc_reset *rst) 183 { 184 return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0; 185 } 186 187 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc, 188 const struct tegra_mc_reset *rst) 189 { 190 unsigned long flags; 191 u32 value; 192 193 spin_lock_irqsave(&mc->lock, flags); 194 195 value = mc_readl(mc, rst->control) & ~BIT(rst->bit); 196 mc_writel(mc, value, rst->control); 197 198 spin_unlock_irqrestore(&mc->lock, flags); 199 200 return 0; 201 } 202 203 static int tegra_mc_reset_status_common(struct tegra_mc *mc, 204 const struct tegra_mc_reset *rst) 205 { 206 return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0; 207 } 208 209 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = { 210 .block_dma = tegra_mc_block_dma_common, 211 .dma_idling = tegra_mc_dma_idling_common, 212 .unblock_dma = tegra_mc_unblock_dma_common, 213 .reset_status = tegra_mc_reset_status_common, 214 }; 215 216 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev) 217 { 218 return container_of(rcdev, struct tegra_mc, reset); 219 } 220 221 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc, 222 unsigned long id) 223 { 224 unsigned int i; 225 226 for (i = 0; i < mc->soc->num_resets; i++) 227 if (mc->soc->resets[i].id == id) 228 return &mc->soc->resets[i]; 229 230 return NULL; 231 } 232 233 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev, 234 unsigned long id) 235 { 236 struct tegra_mc *mc = reset_to_mc(rcdev); 237 const struct tegra_mc_reset_ops *rst_ops; 238 const struct tegra_mc_reset *rst; 239 int retries = 500; 240 int err; 241 242 rst = tegra_mc_reset_find(mc, id); 243 if (!rst) 244 return -ENODEV; 245 246 rst_ops = mc->soc->reset_ops; 247 if (!rst_ops) 248 return -ENODEV; 249 250 /* DMA flushing will fail if reset is already asserted */ 251 if (rst_ops->reset_status) { 252 /* check whether reset is asserted */ 253 if (rst_ops->reset_status(mc, rst)) 254 return 0; 255 } 256 257 if (rst_ops->block_dma) { 258 /* block clients DMA requests */ 259 err = rst_ops->block_dma(mc, rst); 260 if (err) { 261 dev_err(mc->dev, "failed to block %s DMA: %d\n", 262 rst->name, err); 263 return err; 264 } 265 } 266 267 if (rst_ops->dma_idling) { 268 /* wait for completion of the outstanding DMA requests */ 269 while (!rst_ops->dma_idling(mc, rst)) { 270 if (!retries--) { 271 dev_err(mc->dev, "failed to flush %s DMA\n", 272 rst->name); 273 return -EBUSY; 274 } 275 276 usleep_range(10, 100); 277 } 278 } 279 280 if (rst_ops->hotreset_assert) { 281 /* clear clients DMA requests sitting before arbitration */ 282 err = rst_ops->hotreset_assert(mc, rst); 283 if (err) { 284 dev_err(mc->dev, "failed to hot reset %s: %d\n", 285 rst->name, err); 286 return err; 287 } 288 } 289 290 return 0; 291 } 292 293 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev, 294 unsigned long id) 295 { 296 struct tegra_mc *mc = reset_to_mc(rcdev); 297 const struct tegra_mc_reset_ops *rst_ops; 298 const struct tegra_mc_reset *rst; 299 int err; 300 301 rst = tegra_mc_reset_find(mc, id); 302 if (!rst) 303 return -ENODEV; 304 305 rst_ops = mc->soc->reset_ops; 306 if (!rst_ops) 307 return -ENODEV; 308 309 if (rst_ops->hotreset_deassert) { 310 /* take out client from hot reset */ 311 err = rst_ops->hotreset_deassert(mc, rst); 312 if (err) { 313 dev_err(mc->dev, "failed to deassert hot reset %s: %d\n", 314 rst->name, err); 315 return err; 316 } 317 } 318 319 if (rst_ops->unblock_dma) { 320 /* allow new DMA requests to proceed to arbitration */ 321 err = rst_ops->unblock_dma(mc, rst); 322 if (err) { 323 dev_err(mc->dev, "failed to unblock %s DMA : %d\n", 324 rst->name, err); 325 return err; 326 } 327 } 328 329 return 0; 330 } 331 332 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev, 333 unsigned long id) 334 { 335 struct tegra_mc *mc = reset_to_mc(rcdev); 336 const struct tegra_mc_reset_ops *rst_ops; 337 const struct tegra_mc_reset *rst; 338 339 rst = tegra_mc_reset_find(mc, id); 340 if (!rst) 341 return -ENODEV; 342 343 rst_ops = mc->soc->reset_ops; 344 if (!rst_ops) 345 return -ENODEV; 346 347 return rst_ops->reset_status(mc, rst); 348 } 349 350 static const struct reset_control_ops tegra_mc_reset_ops = { 351 .assert = tegra_mc_hotreset_assert, 352 .deassert = tegra_mc_hotreset_deassert, 353 .status = tegra_mc_hotreset_status, 354 }; 355 356 static int tegra_mc_reset_setup(struct tegra_mc *mc) 357 { 358 int err; 359 360 mc->reset.ops = &tegra_mc_reset_ops; 361 mc->reset.owner = THIS_MODULE; 362 mc->reset.of_node = mc->dev->of_node; 363 mc->reset.of_reset_n_cells = 1; 364 mc->reset.nr_resets = mc->soc->num_resets; 365 366 err = reset_controller_register(&mc->reset); 367 if (err < 0) 368 return err; 369 370 return 0; 371 } 372 373 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate) 374 { 375 unsigned int i; 376 struct tegra_mc_timing *timing = NULL; 377 378 for (i = 0; i < mc->num_timings; i++) { 379 if (mc->timings[i].rate == rate) { 380 timing = &mc->timings[i]; 381 break; 382 } 383 } 384 385 if (!timing) { 386 dev_err(mc->dev, "no memory timing registered for rate %lu\n", 387 rate); 388 return -EINVAL; 389 } 390 391 for (i = 0; i < mc->soc->num_emem_regs; ++i) 392 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]); 393 394 return 0; 395 } 396 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration); 397 398 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc) 399 { 400 u8 dram_count; 401 402 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG); 403 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV; 404 dram_count++; 405 406 return dram_count; 407 } 408 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count); 409 410 const irq_handler_t tegra30_mc_irq_handlers[] = { 411 tegra30_mc_handle_irq 412 }; 413 414 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \ 415 defined(CONFIG_ARCH_TEGRA_114_SOC) || \ 416 defined(CONFIG_ARCH_TEGRA_124_SOC) || \ 417 defined(CONFIG_ARCH_TEGRA_132_SOC) || \ 418 defined(CONFIG_ARCH_TEGRA_210_SOC) 419 static void tegra_mc_setup_latency_allowance(struct tegra_mc *mc) 420 { 421 unsigned long long tick; 422 unsigned int i; 423 u32 value; 424 425 /* compute the number of MC clock cycles per tick */ 426 tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk); 427 do_div(tick, NSEC_PER_SEC); 428 429 value = mc_readl(mc, MC_EMEM_ARB_CFG); 430 value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK; 431 value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick); 432 mc_writel(mc, value, MC_EMEM_ARB_CFG); 433 434 /* write latency allowance defaults */ 435 for (i = 0; i < mc->soc->num_clients; i++) { 436 const struct tegra_mc_client *client = &mc->soc->clients[i]; 437 u32 value; 438 439 value = mc_readl(mc, client->regs.la.reg); 440 value &= ~(client->regs.la.mask << client->regs.la.shift); 441 value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift; 442 mc_writel(mc, value, client->regs.la.reg); 443 } 444 445 /* latch new values */ 446 mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); 447 } 448 449 static int load_one_timing(struct tegra_mc *mc, 450 struct tegra_mc_timing *timing, 451 struct device_node *node) 452 { 453 int err; 454 u32 tmp; 455 456 err = of_property_read_u32(node, "clock-frequency", &tmp); 457 if (err) { 458 dev_err(mc->dev, 459 "timing %pOFn: failed to read rate\n", node); 460 return err; 461 } 462 463 timing->rate = tmp; 464 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs, 465 sizeof(u32), GFP_KERNEL); 466 if (!timing->emem_data) 467 return -ENOMEM; 468 469 err = of_property_read_u32_array(node, "nvidia,emem-configuration", 470 timing->emem_data, 471 mc->soc->num_emem_regs); 472 if (err) { 473 dev_err(mc->dev, 474 "timing %pOFn: failed to read EMEM configuration\n", 475 node); 476 return err; 477 } 478 479 return 0; 480 } 481 482 static int load_timings(struct tegra_mc *mc, struct device_node *node) 483 { 484 struct tegra_mc_timing *timing; 485 int child_count = of_get_child_count(node); 486 int i = 0, err; 487 488 mc->timings = devm_kzalloc_objs(mc->dev, *timing, child_count); 489 if (!mc->timings) 490 return -ENOMEM; 491 492 mc->num_timings = child_count; 493 494 for_each_child_of_node_scoped(node, child) { 495 timing = &mc->timings[i++]; 496 497 err = load_one_timing(mc, timing, child); 498 if (err) 499 return err; 500 } 501 502 return 0; 503 } 504 505 static int tegra_mc_setup_timings(struct tegra_mc *mc) 506 { 507 u32 ram_code, node_ram_code; 508 int err; 509 510 ram_code = tegra_read_ram_code(); 511 512 mc->num_timings = 0; 513 514 for_each_child_of_node_scoped(mc->dev->of_node, node) { 515 err = of_property_read_u32(node, "nvidia,ram-code", 516 &node_ram_code); 517 if (err || (node_ram_code != ram_code)) 518 continue; 519 520 err = load_timings(mc, node); 521 if (err) 522 return err; 523 break; 524 } 525 526 if (mc->num_timings == 0) 527 dev_warn(mc->dev, 528 "no memory timings for RAM code %u registered\n", 529 ram_code); 530 531 return 0; 532 } 533 534 int tegra30_mc_probe(struct tegra_mc *mc) 535 { 536 int err; 537 538 mc->clk = devm_clk_get_optional(mc->dev, "mc"); 539 if (IS_ERR(mc->clk)) 540 return dev_err_probe(mc->dev, PTR_ERR(mc->clk), 541 "failed to get MC clock\n"); 542 543 /* ensure that debug features are disabled */ 544 mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG); 545 546 tegra_mc_setup_latency_allowance(mc); 547 548 err = tegra_mc_setup_timings(mc); 549 if (err < 0) 550 return dev_err_probe(mc->dev, err, "failed to setup timings\n"); 551 552 return 0; 553 } 554 555 const struct tegra_mc_ops tegra30_mc_ops = { 556 .probe = tegra30_mc_probe, 557 }; 558 #endif 559 560 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status, 561 unsigned int *mc_channel) 562 { 563 if ((status & mc->soc->ch_intmask) == 0) 564 return -EINVAL; 565 566 *mc_channel = __ffs((status & mc->soc->ch_intmask) >> 567 mc->soc->global_intstatus_channel_shift); 568 569 return 0; 570 } 571 572 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc, 573 unsigned int channel) 574 { 575 return BIT(channel) << mc->soc->global_intstatus_channel_shift; 576 } 577 578 irqreturn_t tegra30_mc_handle_irq(int irq, void *data) 579 { 580 struct tegra_mc *mc = data; 581 unsigned int bit, channel; 582 unsigned long status; 583 584 if (mc->soc->num_channels) { 585 u32 global_status; 586 int err; 587 588 global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS); 589 err = mc_global_intstatus_to_channel(mc, global_status, &channel); 590 if (err < 0) { 591 dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n", 592 global_status); 593 return IRQ_NONE; 594 } 595 596 /* mask all interrupts to avoid flooding */ 597 status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 598 } else { 599 status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmasks[0].mask; 600 } 601 602 if (!status) 603 return IRQ_NONE; 604 605 if (!mc->soc->regs) { 606 dev_err_ratelimited(mc->dev, 607 "MC error interrupt 0x%08lx with no error register map, Clearing.\n", 608 status); 609 goto clear; 610 } 611 612 for_each_set_bit(bit, &status, 32) { 613 const char *error = tegra_mc_status_names[bit] ?: "unknown"; 614 const char *client = "unknown", *desc; 615 const char *direction, *secure; 616 u32 status_reg, addr_reg; 617 u32 intmask = BIT(bit); 618 phys_addr_t addr = 0; 619 #ifdef CONFIG_PHYS_ADDR_T_64BIT 620 u32 addr_hi_reg = 0; 621 #endif 622 unsigned int i; 623 char perm[7]; 624 u8 id, type; 625 u32 value; 626 627 switch (intmask) { 628 case MC_INT_DECERR_VPR: 629 status_reg = mc->soc->regs->err_vpr_status; 630 addr_reg = mc->soc->regs->err_vpr_add; 631 break; 632 633 case MC_INT_SECERR_SEC: 634 status_reg = mc->soc->regs->err_sec_status; 635 addr_reg = mc->soc->regs->err_sec_add; 636 break; 637 638 case MC_INT_DECERR_MTS: 639 status_reg = mc->soc->regs->err_mts_status; 640 addr_reg = mc->soc->regs->err_mts_add; 641 break; 642 643 case MC_INT_DECERR_GENERALIZED_CARVEOUT: 644 status_reg = mc->soc->regs->err_gen_co_status; 645 addr_reg = mc->soc->regs->err_gen_co_add; 646 break; 647 648 case MC_INT_DECERR_ROUTE_SANITY: 649 status_reg = mc->soc->regs->err_route_status; 650 addr_reg = mc->soc->regs->err_route_add; 651 break; 652 653 default: 654 status_reg = mc->soc->regs->err_status; 655 addr_reg = mc->soc->regs->err_add; 656 657 #ifdef CONFIG_PHYS_ADDR_T_64BIT 658 if (mc->soc->has_addr_hi_reg) 659 addr_hi_reg = mc->soc->regs->err_add_hi; 660 #endif 661 break; 662 } 663 664 if (mc->soc->num_channels) 665 value = mc_ch_readl(mc, channel, status_reg); 666 else 667 value = mc_readl(mc, status_reg); 668 669 #ifdef CONFIG_PHYS_ADDR_T_64BIT 670 if (mc->soc->num_address_bits > 32) { 671 if (addr_hi_reg) { 672 if (mc->soc->num_channels) 673 addr = mc_ch_readl(mc, channel, addr_hi_reg); 674 else 675 addr = mc_readl(mc, addr_hi_reg); 676 } else if (mc->soc->mc_addr_hi_mask) { 677 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) & 678 mc->soc->mc_addr_hi_mask); 679 } else { 680 dev_err_ratelimited(mc->dev, "Unable to determine high address!"); 681 return IRQ_NONE; 682 } 683 addr <<= 32; 684 } 685 #endif 686 687 if (value & MC_ERR_STATUS_RW) 688 direction = "write"; 689 else 690 direction = "read"; 691 692 if (value & MC_ERR_STATUS_SECURITY) 693 secure = "secure "; 694 else 695 secure = ""; 696 697 id = value & mc->soc->client_id_mask; 698 699 for (i = 0; i < mc->soc->num_clients; i++) { 700 if (mc->soc->clients[i].id == id) { 701 client = mc->soc->clients[i].name; 702 break; 703 } 704 } 705 706 type = (value & mc->soc->mc_err_status_type_mask) >> 707 MC_ERR_STATUS_TYPE_SHIFT; 708 desc = tegra20_mc_error_names[type]; 709 710 switch (value & mc->soc->mc_err_status_type_mask) { 711 case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE: 712 perm[0] = ' '; 713 perm[1] = '['; 714 715 if (value & MC_ERR_STATUS_READABLE) 716 perm[2] = 'R'; 717 else 718 perm[2] = '-'; 719 720 if (value & MC_ERR_STATUS_WRITABLE) 721 perm[3] = 'W'; 722 else 723 perm[3] = '-'; 724 725 if (value & MC_ERR_STATUS_NONSECURE) 726 perm[4] = '-'; 727 else 728 perm[4] = 'S'; 729 730 perm[5] = ']'; 731 perm[6] = '\0'; 732 break; 733 734 default: 735 perm[0] = '\0'; 736 break; 737 } 738 739 if (mc->soc->num_channels) 740 value = mc_ch_readl(mc, channel, addr_reg); 741 else 742 value = mc_readl(mc, addr_reg); 743 addr |= value; 744 745 dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n", 746 client, secure, direction, &addr, error, 747 desc, perm); 748 } 749 750 clear: 751 /* clear interrupts */ 752 if (mc->soc->num_channels) { 753 mc_ch_writel(mc, channel, status, MC_INTSTATUS); 754 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, 755 mc_channel_to_global_intstatus(mc, channel), 756 MC_GLOBAL_INTSTATUS); 757 } else { 758 mc_writel(mc, status, MC_INTSTATUS); 759 } 760 761 return IRQ_HANDLED; 762 } 763 764 const char *const tegra_mc_status_names[32] = { 765 [ 1] = "External interrupt", 766 [ 6] = "EMEM address decode error", 767 [ 7] = "GART page fault", 768 [ 8] = "Security violation", 769 [ 9] = "EMEM arbitration error", 770 [10] = "Page fault", 771 [11] = "Invalid APB ASID update", 772 [12] = "VPR violation", 773 [13] = "Secure carveout violation", 774 [16] = "MTS carveout violation", 775 [17] = "Generalized carveout violation", 776 [20] = "Route Sanity error", 777 [21] = "GIC_MSI error", 778 }; 779 780 const char *const tegra20_mc_error_names[8] = { 781 [2] = "EMEM decode error", 782 [3] = "TrustZone violation", 783 [4] = "Carveout violation", 784 [6] = "SMMU translation error", 785 }; 786 787 struct icc_node *tegra_mc_icc_xlate(const struct of_phandle_args *spec, void *data) 788 { 789 struct tegra_mc *mc = icc_provider_to_tegra_mc(data); 790 struct icc_node *node; 791 792 list_for_each_entry(node, &mc->provider.nodes, node_list) { 793 if (tegra_mc_client_id_from_node(node) == spec->args[0]) 794 return node; 795 } 796 797 /* 798 * If a client driver calls devm_of_icc_get() before the MC driver 799 * is probed, then return EPROBE_DEFER to the client driver. 800 */ 801 return ERR_PTR(-EPROBE_DEFER); 802 } 803 804 static int tegra_mc_icc_get(struct icc_node *node, u32 *average, u32 *peak) 805 { 806 *average = 0; 807 *peak = 0; 808 809 return 0; 810 } 811 812 static int tegra_mc_icc_set(struct icc_node *src, struct icc_node *dst) 813 { 814 return 0; 815 } 816 817 const struct tegra_mc_icc_ops tegra_mc_icc_ops = { 818 .xlate = tegra_mc_icc_xlate, 819 .aggregate = icc_std_aggregate, 820 .get_bw = tegra_mc_icc_get, 821 .set = tegra_mc_icc_set, 822 }; 823 824 /* 825 * Memory Controller (MC) has few Memory Clients that are issuing memory 826 * bandwidth allocation requests to the MC interconnect provider. The MC 827 * provider aggregates the requests and then sends the aggregated request 828 * up to the External Memory Controller (EMC) interconnect provider which 829 * re-configures hardware interface to External Memory (EMEM) in accordance 830 * to the required bandwidth. Each MC interconnect node represents an 831 * individual Memory Client. 832 * 833 * Memory interconnect topology: 834 * 835 * +----+ 836 * +--------+ | | 837 * | TEXSRD +--->+ | 838 * +--------+ | | 839 * | | +-----+ +------+ 840 * ... | MC +--->+ EMC +--->+ EMEM | 841 * | | +-----+ +------+ 842 * +--------+ | | 843 * | DISP.. +--->+ | 844 * +--------+ | | 845 * +----+ 846 */ 847 static int tegra_mc_interconnect_setup(struct tegra_mc *mc) 848 { 849 int node_id = dev_to_node(mc->dev); 850 struct icc_node *node; 851 unsigned int i; 852 int err; 853 854 /* older device-trees don't have interconnect properties */ 855 if (!device_property_present(mc->dev, "#interconnect-cells") || 856 !mc->soc->icc_ops) 857 return 0; 858 859 mc->provider.dev = mc->dev; 860 mc->provider.data = &mc->provider; 861 mc->provider.set = mc->soc->icc_ops->set; 862 mc->provider.aggregate = mc->soc->icc_ops->aggregate; 863 mc->provider.get_bw = mc->soc->icc_ops->get_bw; 864 mc->provider.xlate = mc->soc->icc_ops->xlate; 865 mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended; 866 867 icc_provider_init(&mc->provider); 868 869 /* create Memory Controller node */ 870 node = tegra_mc_icc_node_create(node_id, TEGRA_ICC_MC); 871 if (IS_ERR(node)) 872 return PTR_ERR(node); 873 874 if (node_id == NUMA_NO_NODE) 875 node->name = "Memory Controller"; 876 else 877 node->name = dev_name(mc->dev); 878 879 icc_node_add(node, &mc->provider); 880 881 /* link Memory Controller to External Memory Controller */ 882 err = tegra_mc_icc_link_create(node, node_id, TEGRA_ICC_EMC); 883 if (err) 884 goto remove_nodes; 885 886 for (i = 0; i < mc->soc->num_clients; i++) { 887 /* create MC client node */ 888 node = tegra_mc_icc_node_create(node_id, mc->soc->clients[i].id); 889 if (IS_ERR(node)) { 890 err = PTR_ERR(node); 891 goto remove_nodes; 892 } 893 894 if (node_id == NUMA_NO_NODE) 895 node->name = mc->soc->clients[i].name; 896 else 897 node->name = devm_kasprintf(mc->dev, GFP_KERNEL, "%d-%s", 898 node_id, mc->soc->clients[i].name); 899 900 icc_node_add(node, &mc->provider); 901 902 /* link Memory Client to Memory Controller */ 903 err = tegra_mc_icc_link_create(node, node_id, TEGRA_ICC_MC); 904 if (err) 905 goto remove_nodes; 906 907 node->data = (struct tegra_mc_client *)&(mc->soc->clients[i]); 908 } 909 910 err = icc_provider_register(&mc->provider); 911 if (err) 912 goto remove_nodes; 913 914 return 0; 915 916 remove_nodes: 917 icc_nodes_remove(&mc->provider); 918 919 return err; 920 } 921 922 static void tegra_mc_num_channel_enabled(struct tegra_mc *mc) 923 { 924 unsigned int i; 925 u32 value; 926 927 value = mc_ch_readl(mc, 0, mc->soc->regs->cfg_channel_enable); 928 if (value <= 0) { 929 mc->num_channels = mc->soc->num_channels; 930 return; 931 } 932 933 for (i = 0; i < 32; i++) { 934 if (value & BIT(i)) 935 mc->num_channels++; 936 } 937 } 938 939 static void tegra_mc_setup_intmask(struct tegra_mc *mc) 940 { 941 unsigned int i; 942 943 for (i = 0; i < mc->soc->num_intmasks; i++) { 944 if (mc->soc->num_channels) 945 mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmasks[i].mask, 946 mc->soc->intmasks[i].reg); 947 else 948 mc_writel(mc, mc->soc->intmasks[i].mask, mc->soc->intmasks[i].reg); 949 } 950 } 951 952 static int tegra_mc_probe(struct platform_device *pdev) 953 { 954 struct tegra_mc *mc; 955 u64 mask; 956 int err; 957 958 mc = devm_kzalloc_obj(&pdev->dev, *mc); 959 if (!mc) 960 return -ENOMEM; 961 962 platform_set_drvdata(pdev, mc); 963 spin_lock_init(&mc->lock); 964 mc->soc = of_device_get_match_data(&pdev->dev); 965 mc->dev = &pdev->dev; 966 967 mask = DMA_BIT_MASK(mc->soc->num_address_bits); 968 969 err = dma_coerce_mask_and_coherent(&pdev->dev, mask); 970 if (err < 0) { 971 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 972 return err; 973 } 974 975 /* length of MC tick in nanoseconds */ 976 mc->tick = 30; 977 978 mc->regs = devm_platform_ioremap_resource(pdev, 0); 979 if (IS_ERR(mc->regs)) 980 return PTR_ERR(mc->regs); 981 982 scoped_guard(mutex, &tegra_mc_debugfs_root_lock) { 983 if (!tegra_mc_debugfs_root) 984 tegra_mc_debugfs_root = debugfs_create_dir("mc", NULL); 985 986 if (dev_to_node(mc->dev) == NUMA_NO_NODE) 987 mc->debugfs.root = tegra_mc_debugfs_root; 988 else 989 mc->debugfs.root = debugfs_create_dir(dev_name(mc->dev), 990 tegra_mc_debugfs_root); 991 } 992 993 if (mc->soc->ops && mc->soc->ops->probe) { 994 err = mc->soc->ops->probe(mc); 995 if (err < 0) 996 return err; 997 } 998 999 tegra_mc_num_channel_enabled(mc); 1000 1001 if (mc->soc->handle_irq) { 1002 unsigned int i; 1003 1004 WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n"); 1005 1006 for (i = 0; i < mc->soc->num_interrupts; i++) { 1007 int irq; 1008 1009 irq = platform_get_irq(pdev, i); 1010 if (irq < 0) 1011 return irq; 1012 1013 err = devm_request_irq(&pdev->dev, irq, mc->soc->handle_irq[i], 0, 1014 dev_name(&pdev->dev), mc); 1015 if (err < 0) { 1016 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", irq, err); 1017 return err; 1018 } 1019 } 1020 1021 tegra_mc_setup_intmask(mc); 1022 } 1023 1024 if (mc->soc->reset_ops) { 1025 err = tegra_mc_reset_setup(mc); 1026 if (err < 0) 1027 dev_err(&pdev->dev, "failed to register reset controller: %d\n", err); 1028 } 1029 1030 err = tegra_mc_interconnect_setup(mc); 1031 if (err < 0) 1032 dev_err(&pdev->dev, "failed to initialize interconnect: %d\n", 1033 err); 1034 1035 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) { 1036 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 1037 if (IS_ERR(mc->smmu)) { 1038 dev_err(&pdev->dev, "failed to probe SMMU: %pe\n", mc->smmu); 1039 mc->smmu = NULL; 1040 } 1041 } 1042 1043 return 0; 1044 } 1045 1046 static void tegra_mc_sync_state(struct device *dev) 1047 { 1048 struct tegra_mc *mc = dev_get_drvdata(dev); 1049 1050 /* check whether ICC provider is registered */ 1051 if (mc->provider.dev == dev) 1052 icc_sync_state(dev); 1053 } 1054 1055 static int tegra_mc_resume(struct device *dev) 1056 { 1057 struct tegra_mc *mc = dev_get_drvdata(dev); 1058 1059 if (mc->soc->ops && mc->soc->ops->resume) 1060 mc->soc->ops->resume(mc); 1061 1062 tegra_mc_setup_intmask(mc); 1063 1064 return 0; 1065 } 1066 1067 static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume); 1068 1069 static struct platform_driver tegra_mc_driver = { 1070 .driver = { 1071 .name = "tegra-mc", 1072 .of_match_table = tegra_mc_of_match, 1073 .pm = pm_sleep_ptr(&tegra_mc_pm_ops), 1074 .suppress_bind_attrs = true, 1075 .sync_state = tegra_mc_sync_state, 1076 }, 1077 .prevent_deferred_probe = true, 1078 .probe = tegra_mc_probe, 1079 }; 1080 1081 static int tegra_mc_init(void) 1082 { 1083 return platform_driver_register(&tegra_mc_driver); 1084 } 1085 arch_initcall(tegra_mc_init); 1086 1087 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>"); 1088 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver"); 1089