1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bus/stm32_firewall_device.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of_address.h> 14 #include <linux/of_platform.h> 15 #include <linux/pinctrl/consumer.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 #include <linux/reset.h> 19 20 #define OMM_CR 0 21 #define CR_MUXEN BIT(0) 22 #define CR_MUXENMODE_MASK GENMASK(1, 0) 23 #define CR_CSSEL_OVR_EN BIT(4) 24 #define CR_CSSEL_OVR_MASK GENMASK(6, 5) 25 #define CR_REQ2ACK_MASK GENMASK(23, 16) 26 27 #define OMM_CHILD_NB 2 28 #define OMM_CLK_NB 3 29 30 struct stm32_omm { 31 struct resource *mm_res; 32 struct clk_bulk_data clk_bulk[OMM_CLK_NB]; 33 struct reset_control *child_reset[OMM_CHILD_NB]; 34 void __iomem *io_base; 35 u32 cr; 36 u8 nb_child; 37 bool restore_omm; 38 }; 39 40 static int stm32_omm_set_amcr(struct device *dev, bool set) 41 { 42 struct stm32_omm *omm = dev_get_drvdata(dev); 43 resource_size_t mm_ospi2_size = 0; 44 static const char * const mm_name[] = { "ospi1", "ospi2" }; 45 struct regmap *syscfg_regmap; 46 struct device_node *node; 47 struct resource res, res1; 48 unsigned int syscon_args[2]; 49 int ret, idx; 50 unsigned int i, amcr, read_amcr; 51 52 for (i = 0; i < omm->nb_child; i++) { 53 idx = of_property_match_string(dev->of_node, 54 "memory-region-names", 55 mm_name[i]); 56 if (idx < 0) 57 continue; 58 59 /* res1 only used on second loop iteration */ 60 res1.start = res.start; 61 res1.end = res.end; 62 63 node = of_parse_phandle(dev->of_node, "memory-region", idx); 64 if (!node) 65 continue; 66 67 ret = of_address_to_resource(node, 0, &res); 68 if (ret) { 69 of_node_put(node); 70 dev_err(dev, "unable to resolve memory region\n"); 71 return ret; 72 } 73 74 /* check that memory region fits inside OMM memory map area */ 75 if (!resource_contains(omm->mm_res, &res)) { 76 dev_err(dev, "%s doesn't fit inside OMM memory map area\n", 77 mm_name[i]); 78 dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res); 79 of_node_put(node); 80 81 return -EFAULT; 82 } 83 84 if (i == 1) { 85 mm_ospi2_size = resource_size(&res); 86 87 /* check that OMM memory region 1 doesn't overlap memory region 2 */ 88 if (resource_overlaps(&res, &res1)) { 89 dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", 90 mm_name[0], mm_name[1]); 91 dev_err(dev, "%pR overlaps %pR\n", &res1, &res); 92 of_node_put(node); 93 94 return -EFAULT; 95 } 96 } 97 of_node_put(node); 98 } 99 100 syscfg_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg-amcr", 101 2, syscon_args); 102 if (IS_ERR(syscfg_regmap)) 103 return dev_err_probe(dev, PTR_ERR(syscfg_regmap), 104 "Failed to get st,syscfg-amcr property\n"); 105 106 amcr = mm_ospi2_size / SZ_64M; 107 108 if (set) 109 regmap_update_bits(syscfg_regmap, syscon_args[0], syscon_args[1], amcr); 110 111 /* read AMCR and check coherency with memory-map areas defined in DT */ 112 regmap_read(syscfg_regmap, syscon_args[0], &read_amcr); 113 read_amcr = read_amcr >> (ffs(syscon_args[1]) - 1); 114 115 if (amcr != read_amcr) { 116 dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); 117 ret = -EINVAL; 118 } 119 120 return ret; 121 } 122 123 static int stm32_omm_toggle_child_clock(struct device *dev, bool enable) 124 { 125 struct stm32_omm *omm = dev_get_drvdata(dev); 126 int i, ret; 127 128 for (i = 0; i < omm->nb_child; i++) { 129 if (enable) { 130 ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk); 131 if (ret) { 132 dev_err(dev, "Can not enable clock\n"); 133 goto clk_error; 134 } 135 } else { 136 clk_disable_unprepare(omm->clk_bulk[i + 1].clk); 137 } 138 } 139 140 return 0; 141 142 clk_error: 143 while (i--) 144 clk_disable_unprepare(omm->clk_bulk[i + 1].clk); 145 146 return ret; 147 } 148 149 static int stm32_omm_disable_child(struct device *dev) 150 { 151 struct stm32_omm *omm = dev_get_drvdata(dev); 152 struct reset_control *reset; 153 int ret; 154 u8 i; 155 156 ret = stm32_omm_toggle_child_clock(dev, true); 157 if (ret) 158 return ret; 159 160 for (i = 0; i < omm->nb_child; i++) { 161 /* reset OSPI to ensure CR_EN bit is set to 0 */ 162 reset = omm->child_reset[i]; 163 ret = reset_control_acquire(reset); 164 if (ret) { 165 stm32_omm_toggle_child_clock(dev, false); 166 dev_err(dev, "Can not acquire reset %d\n", ret); 167 return ret; 168 } 169 170 reset_control_assert(reset); 171 udelay(2); 172 reset_control_deassert(reset); 173 174 reset_control_release(reset); 175 } 176 177 return stm32_omm_toggle_child_clock(dev, false); 178 } 179 180 static int stm32_omm_configure(struct device *dev) 181 { 182 static const char * const clocks_name[] = {"omm", "ospi1", "ospi2"}; 183 struct stm32_omm *omm = dev_get_drvdata(dev); 184 unsigned long clk_rate_max = 0; 185 u32 mux = 0; 186 u32 cssel_ovr = 0; 187 u32 req2ack = 0; 188 struct reset_control *rstc; 189 unsigned long clk_rate; 190 int ret; 191 u8 i; 192 193 for (i = 0; i < OMM_CLK_NB; i++) 194 omm->clk_bulk[i].id = clocks_name[i]; 195 196 /* retrieve OMM, OSPI1 and OSPI2 clocks */ 197 ret = devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk); 198 if (ret) 199 return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n"); 200 201 /* Ensure both OSPI instance are disabled before configuring OMM */ 202 ret = stm32_omm_disable_child(dev); 203 if (ret) 204 return ret; 205 206 ret = pm_runtime_resume_and_get(dev); 207 if (ret < 0) 208 return ret; 209 210 /* parse children's clock */ 211 for (i = 1; i <= omm->nb_child; i++) { 212 clk_rate = clk_get_rate(omm->clk_bulk[i].clk); 213 if (!clk_rate) { 214 dev_err(dev, "Invalid clock rate\n"); 215 ret = -EINVAL; 216 goto error; 217 } 218 219 if (clk_rate > clk_rate_max) 220 clk_rate_max = clk_rate; 221 } 222 223 rstc = devm_reset_control_get_exclusive(dev, "omm"); 224 if (IS_ERR(rstc)) { 225 ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); 226 goto error; 227 } 228 229 reset_control_assert(rstc); 230 udelay(2); 231 reset_control_deassert(rstc); 232 233 omm->cr = readl_relaxed(omm->io_base + OMM_CR); 234 /* optional */ 235 ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); 236 if (!ret) { 237 if (mux & CR_MUXEN) { 238 ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", 239 &req2ack); 240 if (!ret && req2ack) { 241 req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; 242 243 if (req2ack > 256) 244 req2ack = 256; 245 } 246 247 req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); 248 249 omm->cr &= ~CR_REQ2ACK_MASK; 250 omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); 251 252 /* 253 * If the mux is enabled, the 2 OSPI clocks have to be 254 * always enabled 255 */ 256 ret = stm32_omm_toggle_child_clock(dev, true); 257 if (ret) 258 goto error; 259 } 260 261 omm->cr &= ~CR_MUXENMODE_MASK; 262 omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); 263 } 264 265 /* optional */ 266 ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); 267 if (!ret) { 268 omm->cr &= ~CR_CSSEL_OVR_MASK; 269 omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); 270 omm->cr |= CR_CSSEL_OVR_EN; 271 } 272 273 omm->restore_omm = true; 274 writel_relaxed(omm->cr, omm->io_base + OMM_CR); 275 276 ret = stm32_omm_set_amcr(dev, true); 277 278 error: 279 pm_runtime_put_sync_suspend(dev); 280 281 return ret; 282 } 283 284 static int stm32_omm_check_access(struct device_node *np) 285 { 286 struct stm32_firewall firewall; 287 int ret; 288 289 ret = stm32_firewall_get_firewall(np, &firewall, 1); 290 if (ret) 291 return ret; 292 293 return stm32_firewall_grant_access(&firewall); 294 } 295 296 static int stm32_omm_probe(struct platform_device *pdev) 297 { 298 static const char * const resets_name[] = {"ospi1", "ospi2"}; 299 struct device *dev = &pdev->dev; 300 u8 child_access_granted = 0; 301 struct stm32_omm *omm; 302 int i, ret; 303 304 omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); 305 if (!omm) 306 return -ENOMEM; 307 308 omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); 309 if (IS_ERR(omm->io_base)) 310 return PTR_ERR(omm->io_base); 311 312 omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); 313 if (!omm->mm_res) 314 return -ENODEV; 315 316 /* check child's access */ 317 for_each_child_of_node_scoped(dev->of_node, child) { 318 if (omm->nb_child >= OMM_CHILD_NB) { 319 dev_err(dev, "Bad DT, found too much children\n"); 320 return -E2BIG; 321 } 322 323 ret = stm32_omm_check_access(child); 324 if (ret < 0 && ret != -EACCES) 325 return ret; 326 327 if (!ret) 328 child_access_granted++; 329 330 omm->nb_child++; 331 } 332 333 if (omm->nb_child != OMM_CHILD_NB) 334 return -EINVAL; 335 336 platform_set_drvdata(pdev, omm); 337 338 devm_pm_runtime_enable(dev); 339 340 /* check if OMM's resource access is granted */ 341 ret = stm32_omm_check_access(dev->of_node); 342 if (ret < 0 && ret != -EACCES) 343 return ret; 344 345 for (i = 0; i < omm->nb_child; i++) { 346 omm->child_reset[i] = devm_reset_control_get_exclusive_released(dev, 347 resets_name[i]); 348 349 if (IS_ERR(omm->child_reset[i])) 350 return dev_err_probe(dev, PTR_ERR(omm->child_reset[i]), 351 "Can't get %s reset\n", resets_name[i]); 352 } 353 354 if (!ret && child_access_granted == OMM_CHILD_NB) { 355 ret = stm32_omm_configure(dev); 356 if (ret) 357 return ret; 358 } else { 359 dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); 360 /* 361 * AMCR can't be set, so check if current value is coherent 362 * with memory-map areas defined in DT 363 */ 364 ret = stm32_omm_set_amcr(dev, false); 365 if (ret) 366 return ret; 367 } 368 369 ret = devm_of_platform_populate(dev); 370 if (ret) { 371 if (omm->cr & CR_MUXEN) 372 stm32_omm_toggle_child_clock(&pdev->dev, false); 373 374 return dev_err_probe(dev, ret, "Failed to create Octo Memory Manager child\n"); 375 } 376 377 return 0; 378 } 379 380 static void stm32_omm_remove(struct platform_device *pdev) 381 { 382 struct stm32_omm *omm = platform_get_drvdata(pdev); 383 384 if (omm->cr & CR_MUXEN) 385 stm32_omm_toggle_child_clock(&pdev->dev, false); 386 } 387 388 static const struct of_device_id stm32_omm_of_match[] = { 389 { .compatible = "st,stm32mp25-omm", }, 390 {} 391 }; 392 MODULE_DEVICE_TABLE(of, stm32_omm_of_match); 393 394 static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) 395 { 396 struct stm32_omm *omm = dev_get_drvdata(dev); 397 398 clk_disable_unprepare(omm->clk_bulk[0].clk); 399 400 return 0; 401 } 402 403 static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) 404 { 405 struct stm32_omm *omm = dev_get_drvdata(dev); 406 407 return clk_prepare_enable(omm->clk_bulk[0].clk); 408 } 409 410 static int __maybe_unused stm32_omm_suspend(struct device *dev) 411 { 412 struct stm32_omm *omm = dev_get_drvdata(dev); 413 414 if (omm->restore_omm && omm->cr & CR_MUXEN) 415 stm32_omm_toggle_child_clock(dev, false); 416 417 return pinctrl_pm_select_sleep_state(dev); 418 } 419 420 static int __maybe_unused stm32_omm_resume(struct device *dev) 421 { 422 struct stm32_omm *omm = dev_get_drvdata(dev); 423 int ret; 424 425 pinctrl_pm_select_default_state(dev); 426 427 if (!omm->restore_omm) 428 return 0; 429 430 /* Ensure both OSPI instance are disabled before configuring OMM */ 431 ret = stm32_omm_disable_child(dev); 432 if (ret) 433 return ret; 434 435 ret = pm_runtime_resume_and_get(dev); 436 if (ret < 0) 437 return ret; 438 439 writel_relaxed(omm->cr, omm->io_base + OMM_CR); 440 ret = stm32_omm_set_amcr(dev, true); 441 pm_runtime_put_sync_suspend(dev); 442 if (ret) 443 return ret; 444 445 if (omm->cr & CR_MUXEN) 446 ret = stm32_omm_toggle_child_clock(dev, true); 447 448 return ret; 449 } 450 451 static const struct dev_pm_ops stm32_omm_pm_ops = { 452 SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend, 453 stm32_omm_runtime_resume, NULL) 454 SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume) 455 }; 456 457 static struct platform_driver stm32_omm_driver = { 458 .probe = stm32_omm_probe, 459 .remove = stm32_omm_remove, 460 .driver = { 461 .name = "stm32-omm", 462 .of_match_table = stm32_omm_of_match, 463 .pm = &stm32_omm_pm_ops, 464 }, 465 }; 466 module_platform_driver(stm32_omm_driver); 467 468 MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); 469 MODULE_LICENSE("GPL"); 470