xref: /linux/drivers/memory/stm32_omm.c (revision 260f6f4fda93c8485c8037865c941b42b9cba5d2) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) STMicroelectronics 2025 - All Rights Reserved
4  * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics.
5  */
6 
7 #include <linux/bitfield.h>
8 #include <linux/bus/stm32_firewall_device.h>
9 #include <linux/clk.h>
10 #include <linux/err.h>
11 #include <linux/mfd/syscon.h>
12 #include <linux/mod_devicetable.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_platform.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <linux/reset.h>
20 
21 #define OMM_CR			0
22 #define CR_MUXEN		BIT(0)
23 #define CR_MUXENMODE_MASK	GENMASK(1, 0)
24 #define CR_CSSEL_OVR_EN		BIT(4)
25 #define CR_CSSEL_OVR_MASK	GENMASK(6, 5)
26 #define CR_REQ2ACK_MASK		GENMASK(23, 16)
27 
28 #define OMM_CHILD_NB		2
29 #define OMM_CLK_NB		3
30 
31 struct stm32_omm {
32 	struct resource *mm_res;
33 	struct clk_bulk_data clk_bulk[OMM_CLK_NB];
34 	struct reset_control *child_reset[OMM_CHILD_NB];
35 	void __iomem *io_base;
36 	u32 cr;
37 	u8 nb_child;
38 	bool restore_omm;
39 };
40 
41 static int stm32_omm_set_amcr(struct device *dev, bool set)
42 {
43 	struct stm32_omm *omm = dev_get_drvdata(dev);
44 	resource_size_t mm_ospi2_size = 0;
45 	static const char * const mm_name[] = { "ospi1", "ospi2" };
46 	struct regmap *syscfg_regmap;
47 	struct device_node *node;
48 	struct resource res, res1;
49 	unsigned int syscon_args[2];
50 	int ret, idx;
51 	unsigned int i, amcr, read_amcr;
52 
53 	for (i = 0; i < omm->nb_child; i++) {
54 		idx = of_property_match_string(dev->of_node,
55 					       "memory-region-names",
56 					       mm_name[i]);
57 		if (idx < 0)
58 			continue;
59 
60 		/* res1 only used on second loop iteration */
61 		res1.start = res.start;
62 		res1.end = res.end;
63 
64 		node = of_parse_phandle(dev->of_node, "memory-region", idx);
65 		if (!node)
66 			continue;
67 
68 		ret = of_address_to_resource(node, 0, &res);
69 		if (ret) {
70 			of_node_put(node);
71 			dev_err(dev, "unable to resolve memory region\n");
72 			return ret;
73 		}
74 
75 		/* check that memory region fits inside OMM memory map area */
76 		if (!resource_contains(omm->mm_res, &res)) {
77 			dev_err(dev, "%s doesn't fit inside OMM memory map area\n",
78 				mm_name[i]);
79 			dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res);
80 			of_node_put(node);
81 
82 			return -EFAULT;
83 		}
84 
85 		if (i == 1) {
86 			mm_ospi2_size = resource_size(&res);
87 
88 			/* check that OMM memory region 1 doesn't overlap memory region 2 */
89 			if (resource_overlaps(&res, &res1)) {
90 				dev_err(dev, "OMM memory-region %s overlaps memory region %s\n",
91 					mm_name[0], mm_name[1]);
92 				dev_err(dev, "%pR overlaps %pR\n", &res1, &res);
93 				of_node_put(node);
94 
95 				return -EFAULT;
96 			}
97 		}
98 		of_node_put(node);
99 	}
100 
101 	syscfg_regmap = syscon_regmap_lookup_by_phandle_args(dev->of_node, "st,syscfg-amcr",
102 							     2, syscon_args);
103 	if (IS_ERR(syscfg_regmap))
104 		return dev_err_probe(dev, PTR_ERR(syscfg_regmap),
105 				     "Failed to get st,syscfg-amcr property\n");
106 
107 	amcr = mm_ospi2_size / SZ_64M;
108 
109 	if (set)
110 		regmap_update_bits(syscfg_regmap, syscon_args[0], syscon_args[1], amcr);
111 
112 	/* read AMCR and check coherency with memory-map areas defined in DT */
113 	regmap_read(syscfg_regmap, syscon_args[0], &read_amcr);
114 	read_amcr = read_amcr >> (ffs(syscon_args[1]) - 1);
115 
116 	if (amcr != read_amcr) {
117 		dev_err(dev, "AMCR value not coherent with DT memory-map areas\n");
118 		ret = -EINVAL;
119 	}
120 
121 	return ret;
122 }
123 
124 static int stm32_omm_toggle_child_clock(struct device *dev, bool enable)
125 {
126 	struct stm32_omm *omm = dev_get_drvdata(dev);
127 	int i, ret;
128 
129 	for (i = 0; i < omm->nb_child; i++) {
130 		if (enable) {
131 			ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk);
132 			if (ret) {
133 				dev_err(dev, "Can not enable clock\n");
134 				goto clk_error;
135 			}
136 		} else {
137 			clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
138 		}
139 	}
140 
141 	return 0;
142 
143 clk_error:
144 	while (i--)
145 		clk_disable_unprepare(omm->clk_bulk[i + 1].clk);
146 
147 	return ret;
148 }
149 
150 static int stm32_omm_disable_child(struct device *dev)
151 {
152 	struct stm32_omm *omm = dev_get_drvdata(dev);
153 	struct reset_control *reset;
154 	int ret;
155 	u8 i;
156 
157 	ret = stm32_omm_toggle_child_clock(dev, true);
158 	if (ret)
159 		return ret;
160 
161 	for (i = 0; i < omm->nb_child; i++) {
162 		/* reset OSPI to ensure CR_EN bit is set to 0 */
163 		reset = omm->child_reset[i];
164 		ret = reset_control_acquire(reset);
165 		if (ret) {
166 			stm32_omm_toggle_child_clock(dev, false);
167 			dev_err(dev, "Can not acquire reset %d\n", ret);
168 			return ret;
169 		}
170 
171 		reset_control_assert(reset);
172 		udelay(2);
173 		reset_control_deassert(reset);
174 
175 		reset_control_release(reset);
176 	}
177 
178 	return stm32_omm_toggle_child_clock(dev, false);
179 }
180 
181 static int stm32_omm_configure(struct device *dev)
182 {
183 	static const char * const clocks_name[] = {"omm", "ospi1", "ospi2"};
184 	struct stm32_omm *omm = dev_get_drvdata(dev);
185 	unsigned long clk_rate_max = 0;
186 	u32 mux = 0;
187 	u32 cssel_ovr = 0;
188 	u32 req2ack = 0;
189 	struct reset_control *rstc;
190 	unsigned long clk_rate;
191 	int ret;
192 	u8 i;
193 
194 	for (i = 0; i < OMM_CLK_NB; i++)
195 		omm->clk_bulk[i].id = clocks_name[i];
196 
197 	/* retrieve OMM, OSPI1 and OSPI2 clocks */
198 	ret = devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk);
199 	if (ret)
200 		return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n");
201 
202 	/* Ensure both OSPI instance are disabled before configuring OMM */
203 	ret = stm32_omm_disable_child(dev);
204 	if (ret)
205 		return ret;
206 
207 	ret = pm_runtime_resume_and_get(dev);
208 	if (ret < 0)
209 		return ret;
210 
211 	/* parse children's clock */
212 	for (i = 1; i <= omm->nb_child; i++) {
213 		clk_rate = clk_get_rate(omm->clk_bulk[i].clk);
214 		if (!clk_rate) {
215 			dev_err(dev, "Invalid clock rate\n");
216 			ret = -EINVAL;
217 			goto error;
218 		}
219 
220 		if (clk_rate > clk_rate_max)
221 			clk_rate_max = clk_rate;
222 	}
223 
224 	rstc = devm_reset_control_get_exclusive(dev, "omm");
225 	if (IS_ERR(rstc)) {
226 		ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n");
227 		goto error;
228 	}
229 
230 	reset_control_assert(rstc);
231 	udelay(2);
232 	reset_control_deassert(rstc);
233 
234 	omm->cr = readl_relaxed(omm->io_base + OMM_CR);
235 	/* optional */
236 	ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux);
237 	if (!ret) {
238 		if (mux & CR_MUXEN) {
239 			ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns",
240 						   &req2ack);
241 			if (!ret && !req2ack) {
242 				req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1;
243 
244 				if (req2ack > 256)
245 					req2ack = 256;
246 			}
247 
248 			req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
249 
250 			omm->cr &= ~CR_REQ2ACK_MASK;
251 			omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack);
252 
253 			/*
254 			 * If the mux is enabled, the 2 OSPI clocks have to be
255 			 * always enabled
256 			 */
257 			ret = stm32_omm_toggle_child_clock(dev, true);
258 			if (ret)
259 				goto error;
260 		}
261 
262 		omm->cr &= ~CR_MUXENMODE_MASK;
263 		omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux);
264 	}
265 
266 	/* optional */
267 	ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr);
268 	if (!ret) {
269 		omm->cr &= ~CR_CSSEL_OVR_MASK;
270 		omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr);
271 		omm->cr |= CR_CSSEL_OVR_EN;
272 	}
273 
274 	omm->restore_omm = true;
275 	writel_relaxed(omm->cr, omm->io_base + OMM_CR);
276 
277 	ret = stm32_omm_set_amcr(dev, true);
278 
279 error:
280 	pm_runtime_put_sync_suspend(dev);
281 
282 	return ret;
283 }
284 
285 static int stm32_omm_check_access(struct device_node *np)
286 {
287 	struct stm32_firewall firewall;
288 	int ret;
289 
290 	ret = stm32_firewall_get_firewall(np, &firewall, 1);
291 	if (ret)
292 		return ret;
293 
294 	return stm32_firewall_grant_access(&firewall);
295 }
296 
297 static int stm32_omm_probe(struct platform_device *pdev)
298 {
299 	static const char * const resets_name[] = {"ospi1", "ospi2"};
300 	struct device *dev = &pdev->dev;
301 	u8 child_access_granted = 0;
302 	struct stm32_omm *omm;
303 	int i, ret;
304 
305 	omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL);
306 	if (!omm)
307 		return -ENOMEM;
308 
309 	omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs");
310 	if (IS_ERR(omm->io_base))
311 		return PTR_ERR(omm->io_base);
312 
313 	omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map");
314 	if (!omm->mm_res)
315 		return -ENODEV;
316 
317 	/* check child's access */
318 	for_each_child_of_node_scoped(dev->of_node, child) {
319 		if (omm->nb_child >= OMM_CHILD_NB) {
320 			dev_err(dev, "Bad DT, found too much children\n");
321 			return -E2BIG;
322 		}
323 
324 		ret = stm32_omm_check_access(child);
325 		if (ret < 0 && ret != -EACCES)
326 			return ret;
327 
328 		if (!ret)
329 			child_access_granted++;
330 
331 		omm->nb_child++;
332 	}
333 
334 	if (omm->nb_child != OMM_CHILD_NB)
335 		return -EINVAL;
336 
337 	platform_set_drvdata(pdev, omm);
338 
339 	devm_pm_runtime_enable(dev);
340 
341 	/* check if OMM's resource access is granted */
342 	ret = stm32_omm_check_access(dev->of_node);
343 	if (ret < 0 && ret != -EACCES)
344 		return ret;
345 
346 	for (i = 0; i < omm->nb_child; i++) {
347 		omm->child_reset[i] = devm_reset_control_get_exclusive_released(dev,
348 										resets_name[i]);
349 
350 		if (IS_ERR(omm->child_reset[i]))
351 			return dev_err_probe(dev, PTR_ERR(omm->child_reset[i]),
352 					     "Can't get %s reset\n", resets_name[i]);
353 	}
354 
355 	if (!ret && child_access_granted == OMM_CHILD_NB) {
356 		ret = stm32_omm_configure(dev);
357 		if (ret)
358 			return ret;
359 	} else {
360 		dev_dbg(dev, "Octo Memory Manager resource's access not granted\n");
361 		/*
362 		 * AMCR can't be set, so check if current value is coherent
363 		 * with memory-map areas defined in DT
364 		 */
365 		ret = stm32_omm_set_amcr(dev, false);
366 		if (ret)
367 			return ret;
368 	}
369 
370 	ret = devm_of_platform_populate(dev);
371 	if (ret) {
372 		if (omm->cr & CR_MUXEN)
373 			stm32_omm_toggle_child_clock(&pdev->dev, false);
374 
375 		return dev_err_probe(dev, ret, "Failed to create Octo Memory Manager child\n");
376 	}
377 
378 	return 0;
379 }
380 
381 static void stm32_omm_remove(struct platform_device *pdev)
382 {
383 	struct stm32_omm *omm = platform_get_drvdata(pdev);
384 
385 	if (omm->cr & CR_MUXEN)
386 		stm32_omm_toggle_child_clock(&pdev->dev, false);
387 }
388 
389 static const struct of_device_id stm32_omm_of_match[] = {
390 	{ .compatible = "st,stm32mp25-omm", },
391 	{}
392 };
393 MODULE_DEVICE_TABLE(of, stm32_omm_of_match);
394 
395 static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev)
396 {
397 	struct stm32_omm *omm = dev_get_drvdata(dev);
398 
399 	clk_disable_unprepare(omm->clk_bulk[0].clk);
400 
401 	return 0;
402 }
403 
404 static int __maybe_unused stm32_omm_runtime_resume(struct device *dev)
405 {
406 	struct stm32_omm *omm = dev_get_drvdata(dev);
407 
408 	return clk_prepare_enable(omm->clk_bulk[0].clk);
409 }
410 
411 static int __maybe_unused stm32_omm_suspend(struct device *dev)
412 {
413 	struct stm32_omm *omm = dev_get_drvdata(dev);
414 
415 	if (omm->restore_omm && omm->cr & CR_MUXEN)
416 		stm32_omm_toggle_child_clock(dev, false);
417 
418 	return pinctrl_pm_select_sleep_state(dev);
419 }
420 
421 static int __maybe_unused stm32_omm_resume(struct device *dev)
422 {
423 	struct stm32_omm *omm = dev_get_drvdata(dev);
424 	int ret;
425 
426 	pinctrl_pm_select_default_state(dev);
427 
428 	if (!omm->restore_omm)
429 		return 0;
430 
431 	/* Ensure both OSPI instance are disabled before configuring OMM */
432 	ret = stm32_omm_disable_child(dev);
433 	if (ret)
434 		return ret;
435 
436 	ret = pm_runtime_resume_and_get(dev);
437 	if (ret < 0)
438 		return ret;
439 
440 	writel_relaxed(omm->cr, omm->io_base + OMM_CR);
441 	ret = stm32_omm_set_amcr(dev, true);
442 	pm_runtime_put_sync_suspend(dev);
443 	if (ret)
444 		return ret;
445 
446 	if (omm->cr & CR_MUXEN)
447 		ret = stm32_omm_toggle_child_clock(dev, true);
448 
449 	return ret;
450 }
451 
452 static const struct dev_pm_ops stm32_omm_pm_ops = {
453 	SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend,
454 			   stm32_omm_runtime_resume, NULL)
455 	SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume)
456 };
457 
458 static struct platform_driver stm32_omm_driver = {
459 	.probe	= stm32_omm_probe,
460 	.remove = stm32_omm_remove,
461 	.driver	= {
462 		.name = "stm32-omm",
463 		.of_match_table = stm32_omm_of_match,
464 		.pm = &stm32_omm_pm_ops,
465 	},
466 };
467 module_platform_driver(stm32_omm_driver);
468 
469 MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver");
470 MODULE_LICENSE("GPL");
471