1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) STMicroelectronics 2025 - All Rights Reserved 4 * Author(s): Patrice Chotard <patrice.chotard@foss.st.com> for STMicroelectronics. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bus/stm32_firewall_device.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/mod_devicetable.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_platform.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regmap.h> 19 #include <linux/reset.h> 20 21 #define OMM_CR 0 22 #define CR_MUXEN BIT(0) 23 #define CR_MUXENMODE_MASK GENMASK(1, 0) 24 #define CR_CSSEL_OVR_EN BIT(4) 25 #define CR_CSSEL_OVR_MASK GENMASK(6, 5) 26 #define CR_REQ2ACK_MASK GENMASK(23, 16) 27 28 #define OMM_CHILD_NB 2 29 #define OMM_CLK_NB 3 30 31 struct stm32_omm { 32 struct resource *mm_res; 33 struct clk_bulk_data clk_bulk[OMM_CLK_NB]; 34 struct reset_control *child_reset[OMM_CHILD_NB]; 35 void __iomem *io_base; 36 u32 cr; 37 u8 nb_child; 38 bool restore_omm; 39 }; 40 41 static int stm32_omm_set_amcr(struct device *dev, bool set) 42 { 43 struct stm32_omm *omm = dev_get_drvdata(dev); 44 resource_size_t mm_ospi2_size = 0; 45 static const char * const mm_name[] = { "ospi1", "ospi2" }; 46 struct regmap *syscfg_regmap; 47 struct device_node *node; 48 struct resource res, res1; 49 u32 amcr_base, amcr_mask; 50 int ret, idx; 51 unsigned int i, amcr, read_amcr; 52 53 for (i = 0; i < omm->nb_child; i++) { 54 idx = of_property_match_string(dev->of_node, 55 "memory-region-names", 56 mm_name[i]); 57 if (idx < 0) 58 continue; 59 60 /* res1 only used on second loop iteration */ 61 res1.start = res.start; 62 res1.end = res.end; 63 64 node = of_parse_phandle(dev->of_node, "memory-region", idx); 65 if (!node) 66 continue; 67 68 ret = of_address_to_resource(node, 0, &res); 69 if (ret) { 70 of_node_put(node); 71 dev_err(dev, "unable to resolve memory region\n"); 72 return ret; 73 } 74 75 /* check that memory region fits inside OMM memory map area */ 76 if (!resource_contains(omm->mm_res, &res)) { 77 dev_err(dev, "%s doesn't fit inside OMM memory map area\n", 78 mm_name[i]); 79 dev_err(dev, "%pR doesn't fit inside %pR\n", &res, omm->mm_res); 80 of_node_put(node); 81 82 return -EFAULT; 83 } 84 85 if (i == 1) { 86 mm_ospi2_size = resource_size(&res); 87 88 /* check that OMM memory region 1 doesn't overlap memory region 2 */ 89 if (resource_overlaps(&res, &res1)) { 90 dev_err(dev, "OMM memory-region %s overlaps memory region %s\n", 91 mm_name[0], mm_name[1]); 92 dev_err(dev, "%pR overlaps %pR\n", &res1, &res); 93 of_node_put(node); 94 95 return -EFAULT; 96 } 97 } 98 of_node_put(node); 99 } 100 101 syscfg_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "st,syscfg-amcr"); 102 if (IS_ERR(syscfg_regmap)) 103 return dev_err_probe(dev, PTR_ERR(syscfg_regmap), 104 "Failed to get st,syscfg-amcr property\n"); 105 106 ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 1, 107 &amcr_base); 108 if (ret) 109 return ret; 110 111 ret = of_property_read_u32_index(dev->of_node, "st,syscfg-amcr", 2, 112 &amcr_mask); 113 if (ret) 114 return ret; 115 116 amcr = mm_ospi2_size / SZ_64M; 117 118 if (set) 119 regmap_update_bits(syscfg_regmap, amcr_base, amcr_mask, amcr); 120 121 /* read AMCR and check coherency with memory-map areas defined in DT */ 122 regmap_read(syscfg_regmap, amcr_base, &read_amcr); 123 read_amcr = read_amcr >> (ffs(amcr_mask) - 1); 124 125 if (amcr != read_amcr) { 126 dev_err(dev, "AMCR value not coherent with DT memory-map areas\n"); 127 ret = -EINVAL; 128 } 129 130 return ret; 131 } 132 133 static int stm32_omm_toggle_child_clock(struct device *dev, bool enable) 134 { 135 struct stm32_omm *omm = dev_get_drvdata(dev); 136 int i, ret; 137 138 for (i = 0; i < omm->nb_child; i++) { 139 if (enable) { 140 ret = clk_prepare_enable(omm->clk_bulk[i + 1].clk); 141 if (ret) { 142 dev_err(dev, "Can not enable clock\n"); 143 goto clk_error; 144 } 145 } else { 146 clk_disable_unprepare(omm->clk_bulk[i + 1].clk); 147 } 148 } 149 150 return 0; 151 152 clk_error: 153 while (i--) 154 clk_disable_unprepare(omm->clk_bulk[i + 1].clk); 155 156 return ret; 157 } 158 159 static int stm32_omm_disable_child(struct device *dev) 160 { 161 struct stm32_omm *omm = dev_get_drvdata(dev); 162 struct reset_control *reset; 163 int ret; 164 u8 i; 165 166 ret = stm32_omm_toggle_child_clock(dev, true); 167 if (ret) 168 return ret; 169 170 for (i = 0; i < omm->nb_child; i++) { 171 /* reset OSPI to ensure CR_EN bit is set to 0 */ 172 reset = omm->child_reset[i]; 173 ret = reset_control_acquire(reset); 174 if (ret) { 175 stm32_omm_toggle_child_clock(dev, false); 176 dev_err(dev, "Can not acquire reset %d\n", ret); 177 return ret; 178 } 179 180 reset_control_assert(reset); 181 udelay(2); 182 reset_control_deassert(reset); 183 184 reset_control_release(reset); 185 } 186 187 return stm32_omm_toggle_child_clock(dev, false); 188 } 189 190 static int stm32_omm_configure(struct device *dev) 191 { 192 static const char * const clocks_name[] = {"omm", "ospi1", "ospi2"}; 193 struct stm32_omm *omm = dev_get_drvdata(dev); 194 unsigned long clk_rate_max = 0; 195 u32 mux = 0; 196 u32 cssel_ovr = 0; 197 u32 req2ack = 0; 198 struct reset_control *rstc; 199 unsigned long clk_rate; 200 int ret; 201 u8 i; 202 203 for (i = 0; i < OMM_CLK_NB; i++) 204 omm->clk_bulk[i].id = clocks_name[i]; 205 206 /* retrieve OMM, OSPI1 and OSPI2 clocks */ 207 ret = devm_clk_bulk_get(dev, OMM_CLK_NB, omm->clk_bulk); 208 if (ret) 209 return dev_err_probe(dev, ret, "Failed to get OMM/OSPI's clocks\n"); 210 211 /* Ensure both OSPI instance are disabled before configuring OMM */ 212 ret = stm32_omm_disable_child(dev); 213 if (ret) 214 return ret; 215 216 ret = pm_runtime_resume_and_get(dev); 217 if (ret < 0) 218 return ret; 219 220 /* parse children's clock */ 221 for (i = 1; i <= omm->nb_child; i++) { 222 clk_rate = clk_get_rate(omm->clk_bulk[i].clk); 223 if (!clk_rate) { 224 dev_err(dev, "Invalid clock rate\n"); 225 ret = -EINVAL; 226 goto error; 227 } 228 229 if (clk_rate > clk_rate_max) 230 clk_rate_max = clk_rate; 231 } 232 233 rstc = devm_reset_control_get_exclusive(dev, "omm"); 234 if (IS_ERR(rstc)) { 235 ret = dev_err_probe(dev, PTR_ERR(rstc), "reset get failed\n"); 236 goto error; 237 } 238 239 reset_control_assert(rstc); 240 udelay(2); 241 reset_control_deassert(rstc); 242 243 omm->cr = readl_relaxed(omm->io_base + OMM_CR); 244 /* optional */ 245 ret = of_property_read_u32(dev->of_node, "st,omm-mux", &mux); 246 if (!ret) { 247 if (mux & CR_MUXEN) { 248 ret = of_property_read_u32(dev->of_node, "st,omm-req2ack-ns", 249 &req2ack); 250 if (!ret && !req2ack) { 251 req2ack = DIV_ROUND_UP(req2ack, NSEC_PER_SEC / clk_rate_max) - 1; 252 253 if (req2ack > 256) 254 req2ack = 256; 255 } 256 257 req2ack = FIELD_PREP(CR_REQ2ACK_MASK, req2ack); 258 259 omm->cr &= ~CR_REQ2ACK_MASK; 260 omm->cr |= FIELD_PREP(CR_REQ2ACK_MASK, req2ack); 261 262 /* 263 * If the mux is enabled, the 2 OSPI clocks have to be 264 * always enabled 265 */ 266 ret = stm32_omm_toggle_child_clock(dev, true); 267 if (ret) 268 goto error; 269 } 270 271 omm->cr &= ~CR_MUXENMODE_MASK; 272 omm->cr |= FIELD_PREP(CR_MUXENMODE_MASK, mux); 273 } 274 275 /* optional */ 276 ret = of_property_read_u32(dev->of_node, "st,omm-cssel-ovr", &cssel_ovr); 277 if (!ret) { 278 omm->cr &= ~CR_CSSEL_OVR_MASK; 279 omm->cr |= FIELD_PREP(CR_CSSEL_OVR_MASK, cssel_ovr); 280 omm->cr |= CR_CSSEL_OVR_EN; 281 } 282 283 omm->restore_omm = true; 284 writel_relaxed(omm->cr, omm->io_base + OMM_CR); 285 286 ret = stm32_omm_set_amcr(dev, true); 287 288 error: 289 pm_runtime_put_sync_suspend(dev); 290 291 return ret; 292 } 293 294 static int stm32_omm_check_access(struct device_node *np) 295 { 296 struct stm32_firewall firewall; 297 int ret; 298 299 ret = stm32_firewall_get_firewall(np, &firewall, 1); 300 if (ret) 301 return ret; 302 303 return stm32_firewall_grant_access(&firewall); 304 } 305 306 static int stm32_omm_probe(struct platform_device *pdev) 307 { 308 static const char * const resets_name[] = {"ospi1", "ospi2"}; 309 struct device *dev = &pdev->dev; 310 u8 child_access_granted = 0; 311 struct stm32_omm *omm; 312 int i, ret; 313 314 omm = devm_kzalloc(dev, sizeof(*omm), GFP_KERNEL); 315 if (!omm) 316 return -ENOMEM; 317 318 omm->io_base = devm_platform_ioremap_resource_byname(pdev, "regs"); 319 if (IS_ERR(omm->io_base)) 320 return PTR_ERR(omm->io_base); 321 322 omm->mm_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "memory_map"); 323 if (!omm->mm_res) 324 return -ENODEV; 325 326 /* check child's access */ 327 for_each_child_of_node_scoped(dev->of_node, child) { 328 if (omm->nb_child >= OMM_CHILD_NB) { 329 dev_err(dev, "Bad DT, found too much children\n"); 330 return -E2BIG; 331 } 332 333 ret = stm32_omm_check_access(child); 334 if (ret < 0 && ret != -EACCES) 335 return ret; 336 337 if (!ret) 338 child_access_granted++; 339 340 omm->nb_child++; 341 } 342 343 if (omm->nb_child != OMM_CHILD_NB) 344 return -EINVAL; 345 346 platform_set_drvdata(pdev, omm); 347 348 devm_pm_runtime_enable(dev); 349 350 /* check if OMM's resource access is granted */ 351 ret = stm32_omm_check_access(dev->of_node); 352 if (ret < 0 && ret != -EACCES) 353 return ret; 354 355 for (i = 0; i < omm->nb_child; i++) { 356 omm->child_reset[i] = devm_reset_control_get_exclusive_released(dev, 357 resets_name[i]); 358 359 if (IS_ERR(omm->child_reset[i])) 360 return dev_err_probe(dev, PTR_ERR(omm->child_reset[i]), 361 "Can't get %s reset\n", resets_name[i]); 362 } 363 364 if (!ret && child_access_granted == OMM_CHILD_NB) { 365 ret = stm32_omm_configure(dev); 366 if (ret) 367 return ret; 368 } else { 369 dev_dbg(dev, "Octo Memory Manager resource's access not granted\n"); 370 /* 371 * AMCR can't be set, so check if current value is coherent 372 * with memory-map areas defined in DT 373 */ 374 ret = stm32_omm_set_amcr(dev, false); 375 if (ret) 376 return ret; 377 } 378 379 ret = devm_of_platform_populate(dev); 380 if (ret) { 381 if (omm->cr & CR_MUXEN) 382 stm32_omm_toggle_child_clock(&pdev->dev, false); 383 384 return dev_err_probe(dev, ret, "Failed to create Octo Memory Manager child\n"); 385 } 386 387 return 0; 388 } 389 390 static void stm32_omm_remove(struct platform_device *pdev) 391 { 392 struct stm32_omm *omm = platform_get_drvdata(pdev); 393 394 if (omm->cr & CR_MUXEN) 395 stm32_omm_toggle_child_clock(&pdev->dev, false); 396 } 397 398 static const struct of_device_id stm32_omm_of_match[] = { 399 { .compatible = "st,stm32mp25-omm", }, 400 {} 401 }; 402 MODULE_DEVICE_TABLE(of, stm32_omm_of_match); 403 404 static int __maybe_unused stm32_omm_runtime_suspend(struct device *dev) 405 { 406 struct stm32_omm *omm = dev_get_drvdata(dev); 407 408 clk_disable_unprepare(omm->clk_bulk[0].clk); 409 410 return 0; 411 } 412 413 static int __maybe_unused stm32_omm_runtime_resume(struct device *dev) 414 { 415 struct stm32_omm *omm = dev_get_drvdata(dev); 416 417 return clk_prepare_enable(omm->clk_bulk[0].clk); 418 } 419 420 static int __maybe_unused stm32_omm_suspend(struct device *dev) 421 { 422 struct stm32_omm *omm = dev_get_drvdata(dev); 423 424 if (omm->restore_omm && omm->cr & CR_MUXEN) 425 stm32_omm_toggle_child_clock(dev, false); 426 427 return pinctrl_pm_select_sleep_state(dev); 428 } 429 430 static int __maybe_unused stm32_omm_resume(struct device *dev) 431 { 432 struct stm32_omm *omm = dev_get_drvdata(dev); 433 int ret; 434 435 pinctrl_pm_select_default_state(dev); 436 437 if (!omm->restore_omm) 438 return 0; 439 440 /* Ensure both OSPI instance are disabled before configuring OMM */ 441 ret = stm32_omm_disable_child(dev); 442 if (ret) 443 return ret; 444 445 ret = pm_runtime_resume_and_get(dev); 446 if (ret < 0) 447 return ret; 448 449 writel_relaxed(omm->cr, omm->io_base + OMM_CR); 450 ret = stm32_omm_set_amcr(dev, true); 451 pm_runtime_put_sync_suspend(dev); 452 if (ret) 453 return ret; 454 455 if (omm->cr & CR_MUXEN) 456 ret = stm32_omm_toggle_child_clock(dev, true); 457 458 return ret; 459 } 460 461 static const struct dev_pm_ops stm32_omm_pm_ops = { 462 SET_RUNTIME_PM_OPS(stm32_omm_runtime_suspend, 463 stm32_omm_runtime_resume, NULL) 464 SET_SYSTEM_SLEEP_PM_OPS(stm32_omm_suspend, stm32_omm_resume) 465 }; 466 467 static struct platform_driver stm32_omm_driver = { 468 .probe = stm32_omm_probe, 469 .remove = stm32_omm_remove, 470 .driver = { 471 .name = "stm32-omm", 472 .of_match_table = stm32_omm_of_match, 473 .pm = &stm32_omm_pm_ops, 474 }, 475 }; 476 module_platform_driver(stm32_omm_driver); 477 478 MODULE_DESCRIPTION("STMicroelectronics Octo Memory Manager driver"); 479 MODULE_LICENSE("GPL"); 480