1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2020 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 17 /* FMC2 Controller Registers */ 18 #define FMC2_BCR1 0x0 19 #define FMC2_BTR1 0x4 20 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) 21 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) 22 #define FMC2_PCSCNTR 0x20 23 #define FMC2_CFGR 0x20 24 #define FMC2_SR 0x84 25 #define FMC2_BWTR1 0x104 26 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) 27 #define FMC2_SECCFGR 0x300 28 #define FMC2_CIDCFGR0 0x30c 29 #define FMC2_CIDCFGR(x) ((x) * 0x8 + FMC2_CIDCFGR0) 30 #define FMC2_SEMCR0 0x310 31 #define FMC2_SEMCR(x) ((x) * 0x8 + FMC2_SEMCR0) 32 33 /* Register: FMC2_BCR1 */ 34 #define FMC2_BCR1_CCLKEN BIT(20) 35 #define FMC2_BCR1_FMC2EN BIT(31) 36 37 /* Register: FMC2_BCRx */ 38 #define FMC2_BCR_MBKEN BIT(0) 39 #define FMC2_BCR_MUXEN BIT(1) 40 #define FMC2_BCR_MTYP GENMASK(3, 2) 41 #define FMC2_BCR_MWID GENMASK(5, 4) 42 #define FMC2_BCR_FACCEN BIT(6) 43 #define FMC2_BCR_BURSTEN BIT(8) 44 #define FMC2_BCR_WAITPOL BIT(9) 45 #define FMC2_BCR_WAITCFG BIT(11) 46 #define FMC2_BCR_WREN BIT(12) 47 #define FMC2_BCR_WAITEN BIT(13) 48 #define FMC2_BCR_EXTMOD BIT(14) 49 #define FMC2_BCR_ASYNCWAIT BIT(15) 50 #define FMC2_BCR_CPSIZE GENMASK(18, 16) 51 #define FMC2_BCR_CBURSTRW BIT(19) 52 #define FMC2_BCR_CSCOUNT GENMASK(21, 20) 53 #define FMC2_BCR_NBLSET GENMASK(23, 22) 54 55 /* Register: FMC2_BTRx/FMC2_BWTRx */ 56 #define FMC2_BXTR_ADDSET GENMASK(3, 0) 57 #define FMC2_BXTR_ADDHLD GENMASK(7, 4) 58 #define FMC2_BXTR_DATAST GENMASK(15, 8) 59 #define FMC2_BXTR_BUSTURN GENMASK(19, 16) 60 #define FMC2_BTR_CLKDIV GENMASK(23, 20) 61 #define FMC2_BTR_DATLAT GENMASK(27, 24) 62 #define FMC2_BXTR_ACCMOD GENMASK(29, 28) 63 #define FMC2_BXTR_DATAHLD GENMASK(31, 30) 64 65 /* Register: FMC2_PCSCNTR */ 66 #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) 67 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) 68 69 /* Register: FMC2_CFGR */ 70 #define FMC2_CFGR_CLKDIV GENMASK(19, 16) 71 #define FMC2_CFGR_CCLKEN BIT(20) 72 #define FMC2_CFGR_FMC2EN BIT(31) 73 74 /* Register: FMC2_SR */ 75 #define FMC2_SR_ISOST GENMASK(1, 0) 76 77 /* Register: FMC2_CIDCFGR */ 78 #define FMC2_CIDCFGR_CFEN BIT(0) 79 #define FMC2_CIDCFGR_SEMEN BIT(1) 80 #define FMC2_CIDCFGR_SCID GENMASK(6, 4) 81 #define FMC2_CIDCFGR_SEMWLC1 BIT(17) 82 83 /* Register: FMC2_SEMCR */ 84 #define FMC2_SEMCR_SEM_MUTEX BIT(0) 85 #define FMC2_SEMCR_SEMCID GENMASK(6, 4) 86 87 #define FMC2_MAX_EBI_CE 4 88 #define FMC2_MAX_BANKS 5 89 #define FMC2_MAX_RESOURCES 6 90 #define FMC2_CID1 1 91 92 #define FMC2_BCR_CPSIZE_0 0x0 93 #define FMC2_BCR_CPSIZE_128 0x1 94 #define FMC2_BCR_CPSIZE_256 0x2 95 #define FMC2_BCR_CPSIZE_512 0x3 96 #define FMC2_BCR_CPSIZE_1024 0x4 97 98 #define FMC2_BCR_MWID_8 0x0 99 #define FMC2_BCR_MWID_16 0x1 100 101 #define FMC2_BCR_MTYP_SRAM 0x0 102 #define FMC2_BCR_MTYP_PSRAM 0x1 103 #define FMC2_BCR_MTYP_NOR 0x2 104 105 #define FMC2_BCR_CSCOUNT_0 0x0 106 #define FMC2_BCR_CSCOUNT_1 0x1 107 #define FMC2_BCR_CSCOUNT_64 0x2 108 #define FMC2_BCR_CSCOUNT_256 0x3 109 110 #define FMC2_BXTR_EXTMOD_A 0x0 111 #define FMC2_BXTR_EXTMOD_B 0x1 112 #define FMC2_BXTR_EXTMOD_C 0x2 113 #define FMC2_BXTR_EXTMOD_D 0x3 114 115 #define FMC2_BCR_NBLSET_MAX 0x3 116 #define FMC2_BXTR_ADDSET_MAX 0xf 117 #define FMC2_BXTR_ADDHLD_MAX 0xf 118 #define FMC2_BXTR_DATAST_MAX 0xff 119 #define FMC2_BXTR_BUSTURN_MAX 0xf 120 #define FMC2_BXTR_DATAHLD_MAX 0x3 121 #define FMC2_BTR_CLKDIV_MAX 0xf 122 #define FMC2_BTR_DATLAT_MAX 0xf 123 #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff 124 #define FMC2_CFGR_CLKDIV_MAX 0xf 125 126 enum stm32_fmc2_ebi_bank { 127 FMC2_EBI1 = 0, 128 FMC2_EBI2, 129 FMC2_EBI3, 130 FMC2_EBI4, 131 FMC2_NAND 132 }; 133 134 enum stm32_fmc2_ebi_register_type { 135 FMC2_REG_BCR = 1, 136 FMC2_REG_BTR, 137 FMC2_REG_BWTR, 138 FMC2_REG_PCSCNTR, 139 FMC2_REG_CFGR 140 }; 141 142 enum stm32_fmc2_ebi_transaction_type { 143 FMC2_ASYNC_MODE_1_SRAM = 0, 144 FMC2_ASYNC_MODE_1_PSRAM, 145 FMC2_ASYNC_MODE_A_SRAM, 146 FMC2_ASYNC_MODE_A_PSRAM, 147 FMC2_ASYNC_MODE_2_NOR, 148 FMC2_ASYNC_MODE_B_NOR, 149 FMC2_ASYNC_MODE_C_NOR, 150 FMC2_ASYNC_MODE_D_NOR, 151 FMC2_SYNC_READ_SYNC_WRITE_PSRAM, 152 FMC2_SYNC_READ_ASYNC_WRITE_PSRAM, 153 FMC2_SYNC_READ_SYNC_WRITE_NOR, 154 FMC2_SYNC_READ_ASYNC_WRITE_NOR 155 }; 156 157 enum stm32_fmc2_ebi_buswidth { 158 FMC2_BUSWIDTH_8 = 8, 159 FMC2_BUSWIDTH_16 = 16 160 }; 161 162 enum stm32_fmc2_ebi_cpsize { 163 FMC2_CPSIZE_0 = 0, 164 FMC2_CPSIZE_128 = 128, 165 FMC2_CPSIZE_256 = 256, 166 FMC2_CPSIZE_512 = 512, 167 FMC2_CPSIZE_1024 = 1024 168 }; 169 170 enum stm32_fmc2_ebi_cscount { 171 FMC2_CSCOUNT_0 = 0, 172 FMC2_CSCOUNT_1 = 1, 173 FMC2_CSCOUNT_64 = 64, 174 FMC2_CSCOUNT_256 = 256 175 }; 176 177 struct stm32_fmc2_ebi; 178 179 struct stm32_fmc2_ebi_data { 180 const struct stm32_fmc2_prop *child_props; 181 unsigned int nb_child_props; 182 u32 fmc2_enable_reg; 183 u32 fmc2_enable_bit; 184 int (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *ebi); 185 void (*set_setup)(struct stm32_fmc2_ebi *ebi); 186 int (*save_setup)(struct stm32_fmc2_ebi *ebi); 187 int (*check_rif)(struct stm32_fmc2_ebi *ebi, u32 resource); 188 void (*put_sems)(struct stm32_fmc2_ebi *ebi); 189 void (*get_sems)(struct stm32_fmc2_ebi *ebi); 190 }; 191 192 struct stm32_fmc2_ebi { 193 struct device *dev; 194 struct clk *clk; 195 struct regmap *regmap; 196 const struct stm32_fmc2_ebi_data *data; 197 u8 bank_assigned; 198 u8 sem_taken; 199 bool access_granted; 200 201 u32 bcr[FMC2_MAX_EBI_CE]; 202 u32 btr[FMC2_MAX_EBI_CE]; 203 u32 bwtr[FMC2_MAX_EBI_CE]; 204 u32 pcscntr; 205 u32 cfgr; 206 }; 207 208 /* 209 * struct stm32_fmc2_prop - STM32 FMC2 EBI property 210 * @name: the device tree binding name of the property 211 * @bprop: indicate that it is a boolean property 212 * @mprop: indicate that it is a mandatory property 213 * @reg_type: the register that have to be modified 214 * @reg_mask: the bit that have to be modified in the selected register 215 * in case of it is a boolean property 216 * @reset_val: the default value that have to be set in case the property 217 * has not been defined in the device tree 218 * @check: this callback ckecks that the property is compliant with the 219 * transaction type selected 220 * @calculate: this callback is called to calculate for exemple a timing 221 * set in nanoseconds in the device tree in clock cycles or in 222 * clock period 223 * @set: this callback applies the values in the registers 224 */ 225 struct stm32_fmc2_prop { 226 const char *name; 227 bool bprop; 228 bool mprop; 229 int reg_type; 230 u32 reg_mask; 231 u32 reset_val; 232 int (*check)(struct stm32_fmc2_ebi *ebi, 233 const struct stm32_fmc2_prop *prop, int cs); 234 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup); 235 int (*set)(struct stm32_fmc2_ebi *ebi, 236 const struct stm32_fmc2_prop *prop, 237 int cs, u32 setup); 238 }; 239 240 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi, 241 const struct stm32_fmc2_prop *prop, 242 int cs) 243 { 244 u32 bcr; 245 int ret; 246 247 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 248 if (ret) 249 return ret; 250 251 if (bcr & FMC2_BCR_MTYP) 252 return 0; 253 254 return -EINVAL; 255 } 256 257 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi, 258 const struct stm32_fmc2_prop *prop, 259 int cs) 260 { 261 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 262 int ret; 263 264 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 265 if (ret) 266 return ret; 267 268 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 269 return 0; 270 271 return -EINVAL; 272 } 273 274 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi, 275 const struct stm32_fmc2_prop *prop, 276 int cs) 277 { 278 u32 bcr; 279 int ret; 280 281 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 282 if (ret) 283 return ret; 284 285 if (bcr & FMC2_BCR_BURSTEN) 286 return 0; 287 288 return -EINVAL; 289 } 290 291 static int stm32_fmc2_ebi_mp25_check_cclk(struct stm32_fmc2_ebi *ebi, 292 const struct stm32_fmc2_prop *prop, 293 int cs) 294 { 295 if (!ebi->access_granted) 296 return -EACCES; 297 298 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); 299 } 300 301 static int stm32_fmc2_ebi_mp25_check_clk_period(struct stm32_fmc2_ebi *ebi, 302 const struct stm32_fmc2_prop *prop, 303 int cs) 304 { 305 u32 cfgr; 306 int ret; 307 308 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); 309 if (ret) 310 return ret; 311 312 if (cfgr & FMC2_CFGR_CCLKEN && !ebi->access_granted) 313 return -EACCES; 314 315 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); 316 } 317 318 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi, 319 const struct stm32_fmc2_prop *prop, 320 int cs) 321 { 322 u32 bcr; 323 int ret; 324 325 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 326 if (ret) 327 return ret; 328 329 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) 330 return 0; 331 332 return -EINVAL; 333 } 334 335 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi, 336 const struct stm32_fmc2_prop *prop, 337 int cs) 338 { 339 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 340 int ret; 341 342 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 343 if (ret) 344 return ret; 345 346 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 347 return 0; 348 349 return -EINVAL; 350 } 351 352 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi, 353 const struct stm32_fmc2_prop *prop, 354 int cs) 355 { 356 u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 357 int ret; 358 359 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 360 if (ret) 361 return ret; 362 363 if (prop->reg_type == FMC2_REG_BWTR) 364 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 365 else 366 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 367 if (ret) 368 return ret; 369 370 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) && 371 ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)) 372 return 0; 373 374 return -EINVAL; 375 } 376 377 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi, 378 const struct stm32_fmc2_prop *prop, 379 int cs) 380 { 381 u32 bcr, bcr1; 382 int ret; 383 384 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 385 if (ret) 386 return ret; 387 388 if (cs) { 389 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); 390 if (ret) 391 return ret; 392 } else { 393 bcr1 = bcr; 394 } 395 396 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) 397 return 0; 398 399 return -EINVAL; 400 } 401 402 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi, 403 const struct stm32_fmc2_prop *prop, 404 int cs) 405 { 406 if (cs) 407 return -EINVAL; 408 409 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); 410 } 411 412 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi, 413 int cs, u32 setup) 414 { 415 unsigned long hclk = clk_get_rate(ebi->clk); 416 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 417 418 return DIV_ROUND_UP(setup * 1000, hclkp); 419 } 420 421 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, 422 int cs, u32 setup) 423 { 424 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); 425 u32 bcr, btr, clk_period; 426 int ret; 427 428 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr); 429 if (ret) 430 return ret; 431 432 if (bcr & FMC2_BCR1_CCLKEN || !cs) 433 ret = regmap_read(ebi->regmap, FMC2_BTR1, &btr); 434 else 435 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); 436 if (ret) 437 return ret; 438 439 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; 440 441 return DIV_ROUND_UP(nb_clk_cycles, clk_period); 442 } 443 444 static u32 stm32_fmc2_ebi_mp25_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, 445 int cs, u32 setup) 446 { 447 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); 448 u32 cfgr, btr, clk_period; 449 int ret; 450 451 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); 452 if (ret) 453 return ret; 454 455 if (cfgr & FMC2_CFGR_CCLKEN) { 456 clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; 457 } else { 458 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); 459 if (ret) 460 return ret; 461 462 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; 463 } 464 465 return DIV_ROUND_UP(nb_clk_cycles, clk_period); 466 } 467 468 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) 469 { 470 switch (reg_type) { 471 case FMC2_REG_BCR: 472 *reg = FMC2_BCR(cs); 473 break; 474 case FMC2_REG_BTR: 475 *reg = FMC2_BTR(cs); 476 break; 477 case FMC2_REG_BWTR: 478 *reg = FMC2_BWTR(cs); 479 break; 480 case FMC2_REG_PCSCNTR: 481 *reg = FMC2_PCSCNTR; 482 break; 483 case FMC2_REG_CFGR: 484 *reg = FMC2_CFGR; 485 break; 486 default: 487 return -EINVAL; 488 } 489 490 return 0; 491 } 492 493 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi, 494 const struct stm32_fmc2_prop *prop, 495 int cs, u32 setup) 496 { 497 u32 reg; 498 int ret; 499 500 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 501 if (ret) 502 return ret; 503 504 regmap_update_bits(ebi->regmap, reg, prop->reg_mask, 505 setup ? prop->reg_mask : 0); 506 507 return 0; 508 } 509 510 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi, 511 const struct stm32_fmc2_prop *prop, 512 int cs, u32 setup) 513 { 514 u32 bcr_mask, bcr = FMC2_BCR_WREN; 515 u32 btr_mask, btr = 0; 516 u32 bwtr_mask, bwtr = 0; 517 518 bwtr_mask = FMC2_BXTR_ACCMOD; 519 btr_mask = FMC2_BXTR_ACCMOD; 520 bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN | 521 FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN | 522 FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW; 523 524 switch (setup) { 525 case FMC2_ASYNC_MODE_1_SRAM: 526 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 527 /* 528 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 529 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 530 */ 531 break; 532 case FMC2_ASYNC_MODE_1_PSRAM: 533 /* 534 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 535 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 536 */ 537 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 538 break; 539 case FMC2_ASYNC_MODE_A_SRAM: 540 /* 541 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 542 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 543 */ 544 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 545 bcr |= FMC2_BCR_EXTMOD; 546 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 547 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 548 break; 549 case FMC2_ASYNC_MODE_A_PSRAM: 550 /* 551 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 552 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 553 */ 554 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 555 bcr |= FMC2_BCR_EXTMOD; 556 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 557 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 558 break; 559 case FMC2_ASYNC_MODE_2_NOR: 560 /* 561 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 562 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 563 */ 564 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 565 bcr |= FMC2_BCR_FACCEN; 566 break; 567 case FMC2_ASYNC_MODE_B_NOR: 568 /* 569 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 570 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1 571 */ 572 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 573 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 574 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 575 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 576 break; 577 case FMC2_ASYNC_MODE_C_NOR: 578 /* 579 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 580 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2 581 */ 582 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 583 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 584 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 585 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 586 break; 587 case FMC2_ASYNC_MODE_D_NOR: 588 /* 589 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 590 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3 591 */ 592 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 593 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 594 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 595 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 596 break; 597 case FMC2_SYNC_READ_SYNC_WRITE_PSRAM: 598 /* 599 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 600 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 601 */ 602 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 603 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 604 break; 605 case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM: 606 /* 607 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 608 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 609 */ 610 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 611 bcr |= FMC2_BCR_BURSTEN; 612 break; 613 case FMC2_SYNC_READ_SYNC_WRITE_NOR: 614 /* 615 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 616 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 617 */ 618 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 619 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 620 break; 621 case FMC2_SYNC_READ_ASYNC_WRITE_NOR: 622 /* 623 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 624 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 625 */ 626 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 627 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN; 628 break; 629 default: 630 /* Type of transaction not supported */ 631 return -EINVAL; 632 } 633 634 if (bcr & FMC2_BCR_EXTMOD) 635 regmap_update_bits(ebi->regmap, FMC2_BWTR(cs), 636 bwtr_mask, bwtr); 637 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr); 638 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr); 639 640 return 0; 641 } 642 643 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi, 644 const struct stm32_fmc2_prop *prop, 645 int cs, u32 setup) 646 { 647 u32 val; 648 649 switch (setup) { 650 case FMC2_BUSWIDTH_8: 651 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8); 652 break; 653 case FMC2_BUSWIDTH_16: 654 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16); 655 break; 656 default: 657 /* Buswidth not supported */ 658 return -EINVAL; 659 } 660 661 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val); 662 663 return 0; 664 } 665 666 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi, 667 const struct stm32_fmc2_prop *prop, 668 int cs, u32 setup) 669 { 670 u32 val; 671 672 switch (setup) { 673 case FMC2_CPSIZE_0: 674 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0); 675 break; 676 case FMC2_CPSIZE_128: 677 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128); 678 break; 679 case FMC2_CPSIZE_256: 680 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256); 681 break; 682 case FMC2_CPSIZE_512: 683 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512); 684 break; 685 case FMC2_CPSIZE_1024: 686 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024); 687 break; 688 default: 689 /* Cpsize not supported */ 690 return -EINVAL; 691 } 692 693 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val); 694 695 return 0; 696 } 697 698 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi, 699 const struct stm32_fmc2_prop *prop, 700 int cs, u32 setup) 701 { 702 u32 val; 703 704 val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX); 705 val = FIELD_PREP(FMC2_BCR_NBLSET, val); 706 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val); 707 708 return 0; 709 } 710 711 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi, 712 const struct stm32_fmc2_prop *prop, 713 int cs, u32 setup) 714 { 715 u32 bcr, bxtr, reg; 716 u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 717 int ret; 718 719 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 720 if (ret) 721 return ret; 722 723 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 724 if (ret) 725 return ret; 726 727 if (prop->reg_type == FMC2_REG_BWTR) 728 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 729 else 730 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 731 if (ret) 732 return ret; 733 734 if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN) 735 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX); 736 else 737 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX); 738 val = FIELD_PREP(FMC2_BXTR_ADDSET, val); 739 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val); 740 741 return 0; 742 } 743 744 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi, 745 const struct stm32_fmc2_prop *prop, 746 int cs, u32 setup) 747 { 748 u32 val, reg; 749 int ret; 750 751 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 752 if (ret) 753 return ret; 754 755 val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX); 756 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val); 757 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val); 758 759 return 0; 760 } 761 762 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi, 763 const struct stm32_fmc2_prop *prop, 764 int cs, u32 setup) 765 { 766 u32 val, reg; 767 int ret; 768 769 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 770 if (ret) 771 return ret; 772 773 val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX); 774 val = FIELD_PREP(FMC2_BXTR_DATAST, val); 775 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val); 776 777 return 0; 778 } 779 780 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi, 781 const struct stm32_fmc2_prop *prop, 782 int cs, u32 setup) 783 { 784 u32 val, reg; 785 int ret; 786 787 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 788 if (ret) 789 return ret; 790 791 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0; 792 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val); 793 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val); 794 795 return 0; 796 } 797 798 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi, 799 const struct stm32_fmc2_prop *prop, 800 int cs, u32 setup) 801 { 802 u32 val, reg; 803 int ret; 804 805 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 806 if (ret) 807 return ret; 808 809 if (prop->reg_type == FMC2_REG_BWTR) 810 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0; 811 else 812 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX); 813 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val); 814 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val); 815 816 return 0; 817 } 818 819 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, 820 const struct stm32_fmc2_prop *prop, 821 int cs, u32 setup) 822 { 823 u32 val; 824 825 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; 826 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); 827 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); 828 829 return 0; 830 } 831 832 static int stm32_fmc2_ebi_mp25_set_clk_period(struct stm32_fmc2_ebi *ebi, 833 const struct stm32_fmc2_prop *prop, 834 int cs, u32 setup) 835 { 836 u32 val, cfgr; 837 int ret; 838 839 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); 840 if (ret) 841 return ret; 842 843 if (cfgr & FMC2_CFGR_CCLKEN) { 844 val = setup ? clamp_val(setup - 1, 1, FMC2_CFGR_CLKDIV_MAX) : 1; 845 val = FIELD_PREP(FMC2_CFGR_CLKDIV, val); 846 regmap_update_bits(ebi->regmap, FMC2_CFGR, FMC2_CFGR_CLKDIV, val); 847 } else { 848 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; 849 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); 850 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); 851 } 852 853 return 0; 854 } 855 856 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi, 857 const struct stm32_fmc2_prop *prop, 858 int cs, u32 setup) 859 { 860 u32 val; 861 862 val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0; 863 val = FIELD_PREP(FMC2_BTR_DATLAT, val); 864 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val); 865 866 return 0; 867 } 868 869 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, 870 const struct stm32_fmc2_prop *prop, 871 int cs, u32 setup) 872 { 873 u32 old_val, new_val, pcscntr; 874 int ret; 875 876 if (setup < 1) 877 return 0; 878 879 ret = regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); 880 if (ret) 881 return ret; 882 883 /* Enable counter for the bank */ 884 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 885 FMC2_PCSCNTR_CNTBEN(cs), 886 FMC2_PCSCNTR_CNTBEN(cs)); 887 888 new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); 889 old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); 890 if (old_val && new_val > old_val) 891 /* Keep current counter value */ 892 return 0; 893 894 new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); 895 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 896 FMC2_PCSCNTR_CSCOUNT, new_val); 897 898 return 0; 899 } 900 901 static int stm32_fmc2_ebi_mp25_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, 902 const struct stm32_fmc2_prop *prop, 903 int cs, u32 setup) 904 { 905 u32 val; 906 907 if (setup == FMC2_CSCOUNT_0) 908 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_0); 909 else if (setup == FMC2_CSCOUNT_1) 910 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_1); 911 else if (setup <= FMC2_CSCOUNT_64) 912 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_64); 913 else 914 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_256); 915 916 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), 917 FMC2_BCR_CSCOUNT, val); 918 919 return 0; 920 } 921 922 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { 923 /* st,fmc2-ebi-cs-trans-type must be the first property */ 924 { 925 .name = "st,fmc2-ebi-cs-transaction-type", 926 .mprop = true, 927 .set = stm32_fmc2_ebi_set_trans_type, 928 }, 929 { 930 .name = "st,fmc2-ebi-cs-cclk-enable", 931 .bprop = true, 932 .reg_type = FMC2_REG_BCR, 933 .reg_mask = FMC2_BCR1_CCLKEN, 934 .check = stm32_fmc2_ebi_check_cclk, 935 .set = stm32_fmc2_ebi_set_bit_field, 936 }, 937 { 938 .name = "st,fmc2-ebi-cs-mux-enable", 939 .bprop = true, 940 .reg_type = FMC2_REG_BCR, 941 .reg_mask = FMC2_BCR_MUXEN, 942 .check = stm32_fmc2_ebi_check_mux, 943 .set = stm32_fmc2_ebi_set_bit_field, 944 }, 945 { 946 .name = "st,fmc2-ebi-cs-buswidth", 947 .reset_val = FMC2_BUSWIDTH_16, 948 .set = stm32_fmc2_ebi_set_buswidth, 949 }, 950 { 951 .name = "st,fmc2-ebi-cs-waitpol-high", 952 .bprop = true, 953 .reg_type = FMC2_REG_BCR, 954 .reg_mask = FMC2_BCR_WAITPOL, 955 .set = stm32_fmc2_ebi_set_bit_field, 956 }, 957 { 958 .name = "st,fmc2-ebi-cs-waitcfg-enable", 959 .bprop = true, 960 .reg_type = FMC2_REG_BCR, 961 .reg_mask = FMC2_BCR_WAITCFG, 962 .check = stm32_fmc2_ebi_check_waitcfg, 963 .set = stm32_fmc2_ebi_set_bit_field, 964 }, 965 { 966 .name = "st,fmc2-ebi-cs-wait-enable", 967 .bprop = true, 968 .reg_type = FMC2_REG_BCR, 969 .reg_mask = FMC2_BCR_WAITEN, 970 .check = stm32_fmc2_ebi_check_sync_trans, 971 .set = stm32_fmc2_ebi_set_bit_field, 972 }, 973 { 974 .name = "st,fmc2-ebi-cs-asyncwait-enable", 975 .bprop = true, 976 .reg_type = FMC2_REG_BCR, 977 .reg_mask = FMC2_BCR_ASYNCWAIT, 978 .check = stm32_fmc2_ebi_check_async_trans, 979 .set = stm32_fmc2_ebi_set_bit_field, 980 }, 981 { 982 .name = "st,fmc2-ebi-cs-cpsize", 983 .check = stm32_fmc2_ebi_check_cpsize, 984 .set = stm32_fmc2_ebi_set_cpsize, 985 }, 986 { 987 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", 988 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 989 .set = stm32_fmc2_ebi_set_bl_setup, 990 }, 991 { 992 .name = "st,fmc2-ebi-cs-address-setup-ns", 993 .reg_type = FMC2_REG_BTR, 994 .reset_val = FMC2_BXTR_ADDSET_MAX, 995 .check = stm32_fmc2_ebi_check_async_trans, 996 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 997 .set = stm32_fmc2_ebi_set_address_setup, 998 }, 999 { 1000 .name = "st,fmc2-ebi-cs-address-hold-ns", 1001 .reg_type = FMC2_REG_BTR, 1002 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1003 .check = stm32_fmc2_ebi_check_address_hold, 1004 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1005 .set = stm32_fmc2_ebi_set_address_hold, 1006 }, 1007 { 1008 .name = "st,fmc2-ebi-cs-data-setup-ns", 1009 .reg_type = FMC2_REG_BTR, 1010 .reset_val = FMC2_BXTR_DATAST_MAX, 1011 .check = stm32_fmc2_ebi_check_async_trans, 1012 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1013 .set = stm32_fmc2_ebi_set_data_setup, 1014 }, 1015 { 1016 .name = "st,fmc2-ebi-cs-bus-turnaround-ns", 1017 .reg_type = FMC2_REG_BTR, 1018 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1019 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1020 .set = stm32_fmc2_ebi_set_bus_turnaround, 1021 }, 1022 { 1023 .name = "st,fmc2-ebi-cs-data-hold-ns", 1024 .reg_type = FMC2_REG_BTR, 1025 .check = stm32_fmc2_ebi_check_async_trans, 1026 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1027 .set = stm32_fmc2_ebi_set_data_hold, 1028 }, 1029 { 1030 .name = "st,fmc2-ebi-cs-clk-period-ns", 1031 .reset_val = FMC2_BTR_CLKDIV_MAX + 1, 1032 .check = stm32_fmc2_ebi_check_clk_period, 1033 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1034 .set = stm32_fmc2_ebi_set_clk_period, 1035 }, 1036 { 1037 .name = "st,fmc2-ebi-cs-data-latency-ns", 1038 .check = stm32_fmc2_ebi_check_sync_trans, 1039 .calculate = stm32_fmc2_ebi_ns_to_clk_period, 1040 .set = stm32_fmc2_ebi_set_data_latency, 1041 }, 1042 { 1043 .name = "st,fmc2-ebi-cs-write-address-setup-ns", 1044 .reg_type = FMC2_REG_BWTR, 1045 .reset_val = FMC2_BXTR_ADDSET_MAX, 1046 .check = stm32_fmc2_ebi_check_async_trans, 1047 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1048 .set = stm32_fmc2_ebi_set_address_setup, 1049 }, 1050 { 1051 .name = "st,fmc2-ebi-cs-write-address-hold-ns", 1052 .reg_type = FMC2_REG_BWTR, 1053 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1054 .check = stm32_fmc2_ebi_check_address_hold, 1055 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1056 .set = stm32_fmc2_ebi_set_address_hold, 1057 }, 1058 { 1059 .name = "st,fmc2-ebi-cs-write-data-setup-ns", 1060 .reg_type = FMC2_REG_BWTR, 1061 .reset_val = FMC2_BXTR_DATAST_MAX, 1062 .check = stm32_fmc2_ebi_check_async_trans, 1063 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1064 .set = stm32_fmc2_ebi_set_data_setup, 1065 }, 1066 { 1067 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", 1068 .reg_type = FMC2_REG_BWTR, 1069 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1070 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1071 .set = stm32_fmc2_ebi_set_bus_turnaround, 1072 }, 1073 { 1074 .name = "st,fmc2-ebi-cs-write-data-hold-ns", 1075 .reg_type = FMC2_REG_BWTR, 1076 .check = stm32_fmc2_ebi_check_async_trans, 1077 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1078 .set = stm32_fmc2_ebi_set_data_hold, 1079 }, 1080 { 1081 .name = "st,fmc2-ebi-cs-max-low-pulse-ns", 1082 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1083 .set = stm32_fmc2_ebi_set_max_low_pulse, 1084 }, 1085 }; 1086 1087 static const struct stm32_fmc2_prop stm32_fmc2_mp25_child_props[] = { 1088 /* st,fmc2-ebi-cs-trans-type must be the first property */ 1089 { 1090 .name = "st,fmc2-ebi-cs-transaction-type", 1091 .mprop = true, 1092 .set = stm32_fmc2_ebi_set_trans_type, 1093 }, 1094 { 1095 .name = "st,fmc2-ebi-cs-cclk-enable", 1096 .bprop = true, 1097 .reg_type = FMC2_REG_CFGR, 1098 .reg_mask = FMC2_CFGR_CCLKEN, 1099 .check = stm32_fmc2_ebi_mp25_check_cclk, 1100 .set = stm32_fmc2_ebi_set_bit_field, 1101 }, 1102 { 1103 .name = "st,fmc2-ebi-cs-mux-enable", 1104 .bprop = true, 1105 .reg_type = FMC2_REG_BCR, 1106 .reg_mask = FMC2_BCR_MUXEN, 1107 .check = stm32_fmc2_ebi_check_mux, 1108 .set = stm32_fmc2_ebi_set_bit_field, 1109 }, 1110 { 1111 .name = "st,fmc2-ebi-cs-buswidth", 1112 .reset_val = FMC2_BUSWIDTH_16, 1113 .set = stm32_fmc2_ebi_set_buswidth, 1114 }, 1115 { 1116 .name = "st,fmc2-ebi-cs-waitpol-high", 1117 .bprop = true, 1118 .reg_type = FMC2_REG_BCR, 1119 .reg_mask = FMC2_BCR_WAITPOL, 1120 .set = stm32_fmc2_ebi_set_bit_field, 1121 }, 1122 { 1123 .name = "st,fmc2-ebi-cs-waitcfg-enable", 1124 .bprop = true, 1125 .reg_type = FMC2_REG_BCR, 1126 .reg_mask = FMC2_BCR_WAITCFG, 1127 .check = stm32_fmc2_ebi_check_waitcfg, 1128 .set = stm32_fmc2_ebi_set_bit_field, 1129 }, 1130 { 1131 .name = "st,fmc2-ebi-cs-wait-enable", 1132 .bprop = true, 1133 .reg_type = FMC2_REG_BCR, 1134 .reg_mask = FMC2_BCR_WAITEN, 1135 .check = stm32_fmc2_ebi_check_sync_trans, 1136 .set = stm32_fmc2_ebi_set_bit_field, 1137 }, 1138 { 1139 .name = "st,fmc2-ebi-cs-asyncwait-enable", 1140 .bprop = true, 1141 .reg_type = FMC2_REG_BCR, 1142 .reg_mask = FMC2_BCR_ASYNCWAIT, 1143 .check = stm32_fmc2_ebi_check_async_trans, 1144 .set = stm32_fmc2_ebi_set_bit_field, 1145 }, 1146 { 1147 .name = "st,fmc2-ebi-cs-cpsize", 1148 .check = stm32_fmc2_ebi_check_cpsize, 1149 .set = stm32_fmc2_ebi_set_cpsize, 1150 }, 1151 { 1152 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", 1153 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1154 .set = stm32_fmc2_ebi_set_bl_setup, 1155 }, 1156 { 1157 .name = "st,fmc2-ebi-cs-address-setup-ns", 1158 .reg_type = FMC2_REG_BTR, 1159 .reset_val = FMC2_BXTR_ADDSET_MAX, 1160 .check = stm32_fmc2_ebi_check_async_trans, 1161 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1162 .set = stm32_fmc2_ebi_set_address_setup, 1163 }, 1164 { 1165 .name = "st,fmc2-ebi-cs-address-hold-ns", 1166 .reg_type = FMC2_REG_BTR, 1167 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1168 .check = stm32_fmc2_ebi_check_address_hold, 1169 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1170 .set = stm32_fmc2_ebi_set_address_hold, 1171 }, 1172 { 1173 .name = "st,fmc2-ebi-cs-data-setup-ns", 1174 .reg_type = FMC2_REG_BTR, 1175 .reset_val = FMC2_BXTR_DATAST_MAX, 1176 .check = stm32_fmc2_ebi_check_async_trans, 1177 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1178 .set = stm32_fmc2_ebi_set_data_setup, 1179 }, 1180 { 1181 .name = "st,fmc2-ebi-cs-bus-turnaround-ns", 1182 .reg_type = FMC2_REG_BTR, 1183 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1184 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1185 .set = stm32_fmc2_ebi_set_bus_turnaround, 1186 }, 1187 { 1188 .name = "st,fmc2-ebi-cs-data-hold-ns", 1189 .reg_type = FMC2_REG_BTR, 1190 .check = stm32_fmc2_ebi_check_async_trans, 1191 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1192 .set = stm32_fmc2_ebi_set_data_hold, 1193 }, 1194 { 1195 .name = "st,fmc2-ebi-cs-clk-period-ns", 1196 .reset_val = FMC2_CFGR_CLKDIV_MAX + 1, 1197 .check = stm32_fmc2_ebi_mp25_check_clk_period, 1198 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1199 .set = stm32_fmc2_ebi_mp25_set_clk_period, 1200 }, 1201 { 1202 .name = "st,fmc2-ebi-cs-data-latency-ns", 1203 .check = stm32_fmc2_ebi_check_sync_trans, 1204 .calculate = stm32_fmc2_ebi_mp25_ns_to_clk_period, 1205 .set = stm32_fmc2_ebi_set_data_latency, 1206 }, 1207 { 1208 .name = "st,fmc2-ebi-cs-write-address-setup-ns", 1209 .reg_type = FMC2_REG_BWTR, 1210 .reset_val = FMC2_BXTR_ADDSET_MAX, 1211 .check = stm32_fmc2_ebi_check_async_trans, 1212 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1213 .set = stm32_fmc2_ebi_set_address_setup, 1214 }, 1215 { 1216 .name = "st,fmc2-ebi-cs-write-address-hold-ns", 1217 .reg_type = FMC2_REG_BWTR, 1218 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1219 .check = stm32_fmc2_ebi_check_address_hold, 1220 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1221 .set = stm32_fmc2_ebi_set_address_hold, 1222 }, 1223 { 1224 .name = "st,fmc2-ebi-cs-write-data-setup-ns", 1225 .reg_type = FMC2_REG_BWTR, 1226 .reset_val = FMC2_BXTR_DATAST_MAX, 1227 .check = stm32_fmc2_ebi_check_async_trans, 1228 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1229 .set = stm32_fmc2_ebi_set_data_setup, 1230 }, 1231 { 1232 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", 1233 .reg_type = FMC2_REG_BWTR, 1234 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1235 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1236 .set = stm32_fmc2_ebi_set_bus_turnaround, 1237 }, 1238 { 1239 .name = "st,fmc2-ebi-cs-write-data-hold-ns", 1240 .reg_type = FMC2_REG_BWTR, 1241 .check = stm32_fmc2_ebi_check_async_trans, 1242 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1243 .set = stm32_fmc2_ebi_set_data_hold, 1244 }, 1245 { 1246 .name = "st,fmc2-ebi-cs-max-low-pulse-ns", 1247 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1248 .set = stm32_fmc2_ebi_mp25_set_max_low_pulse, 1249 }, 1250 }; 1251 1252 static int stm32_fmc2_ebi_mp25_check_rif(struct stm32_fmc2_ebi *ebi, u32 resource) 1253 { 1254 u32 seccfgr, cidcfgr, semcr; 1255 int cid, ret; 1256 1257 if (resource >= FMC2_MAX_RESOURCES) 1258 return -EINVAL; 1259 1260 ret = regmap_read(ebi->regmap, FMC2_SECCFGR, &seccfgr); 1261 if (ret) 1262 return ret; 1263 1264 if (seccfgr & BIT(resource)) { 1265 if (resource) 1266 dev_err(ebi->dev, "resource %d is configured as secure\n", 1267 resource); 1268 1269 return -EACCES; 1270 } 1271 1272 ret = regmap_read(ebi->regmap, FMC2_CIDCFGR(resource), &cidcfgr); 1273 if (ret) 1274 return ret; 1275 1276 if (!(cidcfgr & FMC2_CIDCFGR_CFEN)) 1277 /* CID filtering is turned off: access granted */ 1278 return 0; 1279 1280 if (!(cidcfgr & FMC2_CIDCFGR_SEMEN)) { 1281 /* Static CID mode */ 1282 cid = FIELD_GET(FMC2_CIDCFGR_SCID, cidcfgr); 1283 if (cid != FMC2_CID1) { 1284 if (resource) 1285 dev_err(ebi->dev, "static CID%d set for resource %d\n", 1286 cid, resource); 1287 1288 return -EACCES; 1289 } 1290 1291 return 0; 1292 } 1293 1294 /* Pass-list with semaphore mode */ 1295 if (!(cidcfgr & FMC2_CIDCFGR_SEMWLC1)) { 1296 if (resource) 1297 dev_err(ebi->dev, "CID1 is block-listed for resource %d\n", 1298 resource); 1299 1300 return -EACCES; 1301 } 1302 1303 ret = regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); 1304 if (ret) 1305 return ret; 1306 1307 if (!(semcr & FMC2_SEMCR_SEM_MUTEX)) { 1308 regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), 1309 FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); 1310 1311 ret = regmap_read(ebi->regmap, FMC2_SEMCR(resource), &semcr); 1312 if (ret) 1313 return ret; 1314 } 1315 1316 cid = FIELD_GET(FMC2_SEMCR_SEMCID, semcr); 1317 if (cid != FMC2_CID1) { 1318 if (resource) 1319 dev_err(ebi->dev, "resource %d is already used by CID%d\n", 1320 resource, cid); 1321 1322 return -EACCES; 1323 } 1324 1325 ebi->sem_taken |= BIT(resource); 1326 1327 return 0; 1328 } 1329 1330 static void stm32_fmc2_ebi_mp25_put_sems(struct stm32_fmc2_ebi *ebi) 1331 { 1332 unsigned int resource; 1333 1334 for (resource = 0; resource < FMC2_MAX_RESOURCES; resource++) { 1335 if (!(ebi->sem_taken & BIT(resource))) 1336 continue; 1337 1338 regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), 1339 FMC2_SEMCR_SEM_MUTEX, 0); 1340 } 1341 } 1342 1343 static void stm32_fmc2_ebi_mp25_get_sems(struct stm32_fmc2_ebi *ebi) 1344 { 1345 unsigned int resource; 1346 1347 for (resource = 0; resource < FMC2_MAX_RESOURCES; resource++) { 1348 if (!(ebi->sem_taken & BIT(resource))) 1349 continue; 1350 1351 regmap_update_bits(ebi->regmap, FMC2_SEMCR(resource), 1352 FMC2_SEMCR_SEM_MUTEX, FMC2_SEMCR_SEM_MUTEX); 1353 } 1354 } 1355 1356 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, 1357 struct device_node *dev_node, 1358 const struct stm32_fmc2_prop *prop, 1359 int cs) 1360 { 1361 struct device *dev = ebi->dev; 1362 u32 setup = 0; 1363 1364 if (!prop->set) { 1365 dev_err(dev, "property %s is not well defined\n", prop->name); 1366 return -EINVAL; 1367 } 1368 1369 if (prop->check && prop->check(ebi, prop, cs)) 1370 /* Skeep this property */ 1371 return 0; 1372 1373 if (prop->bprop) { 1374 bool bprop; 1375 1376 bprop = of_property_read_bool(dev_node, prop->name); 1377 if (prop->mprop && !bprop) { 1378 dev_err(dev, "mandatory property %s not defined in the device tree\n", 1379 prop->name); 1380 return -EINVAL; 1381 } 1382 1383 if (bprop) 1384 setup = 1; 1385 } else { 1386 u32 val; 1387 int ret; 1388 1389 ret = of_property_read_u32(dev_node, prop->name, &val); 1390 if (prop->mprop && ret) { 1391 dev_err(dev, "mandatory property %s not defined in the device tree\n", 1392 prop->name); 1393 return ret; 1394 } 1395 1396 if (ret) 1397 setup = prop->reset_val; 1398 else if (prop->calculate) 1399 setup = prop->calculate(ebi, cs, val); 1400 else 1401 setup = val; 1402 } 1403 1404 return prop->set(ebi, prop, cs, setup); 1405 } 1406 1407 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs) 1408 { 1409 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), 1410 FMC2_BCR_MBKEN, FMC2_BCR_MBKEN); 1411 } 1412 1413 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs) 1414 { 1415 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0); 1416 } 1417 1418 static int stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) 1419 { 1420 unsigned int cs; 1421 int ret; 1422 1423 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1424 if (!(ebi->bank_assigned & BIT(cs))) 1425 continue; 1426 1427 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); 1428 ret |= regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); 1429 ret |= regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); 1430 if (ret) 1431 return ret; 1432 } 1433 1434 return 0; 1435 } 1436 1437 static int stm32_fmc2_ebi_mp1_save_setup(struct stm32_fmc2_ebi *ebi) 1438 { 1439 int ret; 1440 1441 ret = stm32_fmc2_ebi_save_setup(ebi); 1442 if (ret) 1443 return ret; 1444 1445 return regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); 1446 } 1447 1448 static int stm32_fmc2_ebi_mp25_save_setup(struct stm32_fmc2_ebi *ebi) 1449 { 1450 int ret; 1451 1452 ret = stm32_fmc2_ebi_save_setup(ebi); 1453 if (ret) 1454 return ret; 1455 1456 if (ebi->access_granted) 1457 ret = regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); 1458 1459 return ret; 1460 } 1461 1462 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) 1463 { 1464 unsigned int cs; 1465 1466 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1467 if (!(ebi->bank_assigned & BIT(cs))) 1468 continue; 1469 1470 regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]); 1471 regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]); 1472 regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); 1473 } 1474 } 1475 1476 static void stm32_fmc2_ebi_mp1_set_setup(struct stm32_fmc2_ebi *ebi) 1477 { 1478 stm32_fmc2_ebi_set_setup(ebi); 1479 regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); 1480 } 1481 1482 static void stm32_fmc2_ebi_mp25_set_setup(struct stm32_fmc2_ebi *ebi) 1483 { 1484 stm32_fmc2_ebi_set_setup(ebi); 1485 1486 if (ebi->access_granted) 1487 regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); 1488 } 1489 1490 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi) 1491 { 1492 unsigned int cs; 1493 1494 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1495 if (!(ebi->bank_assigned & BIT(cs))) 1496 continue; 1497 1498 stm32_fmc2_ebi_disable_bank(ebi, cs); 1499 } 1500 } 1501 1502 /* NWAIT signal can not be connected to EBI controller and NAND controller */ 1503 static int stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) 1504 { 1505 struct device *dev = ebi->dev; 1506 unsigned int cs; 1507 u32 bcr; 1508 int ret; 1509 1510 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1511 if (!(ebi->bank_assigned & BIT(cs))) 1512 continue; 1513 1514 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 1515 if (ret) 1516 return ret; 1517 1518 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && 1519 ebi->bank_assigned & BIT(FMC2_NAND)) { 1520 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); 1521 return -EINVAL; 1522 } 1523 } 1524 1525 return 0; 1526 } 1527 1528 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) 1529 { 1530 if (!ebi->access_granted) 1531 return; 1532 1533 regmap_update_bits(ebi->regmap, ebi->data->fmc2_enable_reg, 1534 ebi->data->fmc2_enable_bit, 1535 ebi->data->fmc2_enable_bit); 1536 } 1537 1538 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) 1539 { 1540 if (!ebi->access_granted) 1541 return; 1542 1543 regmap_update_bits(ebi->regmap, ebi->data->fmc2_enable_reg, 1544 ebi->data->fmc2_enable_bit, 0); 1545 } 1546 1547 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, 1548 struct device_node *dev_node, 1549 u32 cs) 1550 { 1551 unsigned int i; 1552 int ret; 1553 1554 stm32_fmc2_ebi_disable_bank(ebi, cs); 1555 1556 for (i = 0; i < ebi->data->nb_child_props; i++) { 1557 const struct stm32_fmc2_prop *p = &ebi->data->child_props[i]; 1558 1559 ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs); 1560 if (ret) { 1561 dev_err(ebi->dev, "property %s could not be set: %d\n", 1562 p->name, ret); 1563 return ret; 1564 } 1565 } 1566 1567 stm32_fmc2_ebi_enable_bank(ebi, cs); 1568 1569 return 0; 1570 } 1571 1572 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi) 1573 { 1574 struct device *dev = ebi->dev; 1575 struct device_node *child; 1576 bool child_found = false; 1577 u32 bank; 1578 int ret; 1579 1580 for_each_available_child_of_node(dev->of_node, child) { 1581 ret = of_property_read_u32(child, "reg", &bank); 1582 if (ret) { 1583 dev_err(dev, "could not retrieve reg property: %d\n", 1584 ret); 1585 of_node_put(child); 1586 return ret; 1587 } 1588 1589 if (bank >= FMC2_MAX_BANKS) { 1590 dev_err(dev, "invalid reg value: %d\n", bank); 1591 of_node_put(child); 1592 return -EINVAL; 1593 } 1594 1595 if (ebi->bank_assigned & BIT(bank)) { 1596 dev_err(dev, "bank already assigned: %d\n", bank); 1597 of_node_put(child); 1598 return -EINVAL; 1599 } 1600 1601 if (ebi->data->check_rif) { 1602 ret = ebi->data->check_rif(ebi, bank + 1); 1603 if (ret) { 1604 dev_err(dev, "bank access failed: %d\n", bank); 1605 of_node_put(child); 1606 return ret; 1607 } 1608 } 1609 1610 if (bank < FMC2_MAX_EBI_CE) { 1611 ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); 1612 if (ret) { 1613 dev_err(dev, "setup chip select %d failed: %d\n", 1614 bank, ret); 1615 of_node_put(child); 1616 return ret; 1617 } 1618 } 1619 1620 ebi->bank_assigned |= BIT(bank); 1621 child_found = true; 1622 } 1623 1624 if (!child_found) { 1625 dev_warn(dev, "no subnodes found, disable the driver.\n"); 1626 return -ENODEV; 1627 } 1628 1629 if (ebi->data->nwait_used_by_ctrls) { 1630 ret = ebi->data->nwait_used_by_ctrls(ebi); 1631 if (ret) 1632 return ret; 1633 } 1634 1635 stm32_fmc2_ebi_enable(ebi); 1636 1637 return of_platform_populate(dev->of_node, NULL, NULL, dev); 1638 } 1639 1640 static int stm32_fmc2_ebi_probe(struct platform_device *pdev) 1641 { 1642 struct device *dev = &pdev->dev; 1643 struct stm32_fmc2_ebi *ebi; 1644 struct reset_control *rstc; 1645 int ret; 1646 1647 ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL); 1648 if (!ebi) 1649 return -ENOMEM; 1650 1651 ebi->dev = dev; 1652 1653 ebi->data = of_device_get_match_data(dev); 1654 if (!ebi->data) 1655 return -EINVAL; 1656 1657 ebi->regmap = device_node_to_regmap(dev->of_node); 1658 if (IS_ERR(ebi->regmap)) 1659 return PTR_ERR(ebi->regmap); 1660 1661 ebi->clk = devm_clk_get(dev, NULL); 1662 if (IS_ERR(ebi->clk)) 1663 return PTR_ERR(ebi->clk); 1664 1665 rstc = devm_reset_control_get(dev, NULL); 1666 if (PTR_ERR(rstc) == -EPROBE_DEFER) 1667 return -EPROBE_DEFER; 1668 1669 ret = clk_prepare_enable(ebi->clk); 1670 if (ret) 1671 return ret; 1672 1673 if (!IS_ERR(rstc)) { 1674 reset_control_assert(rstc); 1675 reset_control_deassert(rstc); 1676 } 1677 1678 /* Check if CFGR register can be modified */ 1679 ebi->access_granted = true; 1680 if (ebi->data->check_rif) { 1681 ret = ebi->data->check_rif(ebi, 0); 1682 if (ret) { 1683 u32 sr; 1684 1685 ebi->access_granted = false; 1686 1687 ret = regmap_read(ebi->regmap, FMC2_SR, &sr); 1688 if (ret) 1689 goto err_release; 1690 1691 /* In case of CFGR is secure, just check that the FMC2 is enabled */ 1692 if (sr & FMC2_SR_ISOST) { 1693 dev_err(dev, "FMC2 is not ready to be used.\n"); 1694 ret = -EACCES; 1695 goto err_release; 1696 } 1697 } 1698 } 1699 1700 ret = stm32_fmc2_ebi_parse_dt(ebi); 1701 if (ret) 1702 goto err_release; 1703 1704 ret = ebi->data->save_setup(ebi); 1705 if (ret) 1706 goto err_release; 1707 1708 platform_set_drvdata(pdev, ebi); 1709 1710 return 0; 1711 1712 err_release: 1713 stm32_fmc2_ebi_disable_banks(ebi); 1714 stm32_fmc2_ebi_disable(ebi); 1715 if (ebi->data->put_sems) 1716 ebi->data->put_sems(ebi); 1717 clk_disable_unprepare(ebi->clk); 1718 1719 return ret; 1720 } 1721 1722 static void stm32_fmc2_ebi_remove(struct platform_device *pdev) 1723 { 1724 struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev); 1725 1726 of_platform_depopulate(&pdev->dev); 1727 stm32_fmc2_ebi_disable_banks(ebi); 1728 stm32_fmc2_ebi_disable(ebi); 1729 if (ebi->data->put_sems) 1730 ebi->data->put_sems(ebi); 1731 clk_disable_unprepare(ebi->clk); 1732 } 1733 1734 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) 1735 { 1736 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1737 1738 stm32_fmc2_ebi_disable(ebi); 1739 if (ebi->data->put_sems) 1740 ebi->data->put_sems(ebi); 1741 clk_disable_unprepare(ebi->clk); 1742 pinctrl_pm_select_sleep_state(dev); 1743 1744 return 0; 1745 } 1746 1747 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) 1748 { 1749 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1750 int ret; 1751 1752 pinctrl_pm_select_default_state(dev); 1753 1754 ret = clk_prepare_enable(ebi->clk); 1755 if (ret) 1756 return ret; 1757 1758 if (ebi->data->get_sems) 1759 ebi->data->get_sems(ebi); 1760 ebi->data->set_setup(ebi); 1761 stm32_fmc2_ebi_enable(ebi); 1762 1763 return 0; 1764 } 1765 1766 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, 1767 stm32_fmc2_ebi_resume); 1768 1769 static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data = { 1770 .child_props = stm32_fmc2_child_props, 1771 .nb_child_props = ARRAY_SIZE(stm32_fmc2_child_props), 1772 .fmc2_enable_reg = FMC2_BCR1, 1773 .fmc2_enable_bit = FMC2_BCR1_FMC2EN, 1774 .nwait_used_by_ctrls = stm32_fmc2_ebi_nwait_used_by_ctrls, 1775 .set_setup = stm32_fmc2_ebi_mp1_set_setup, 1776 .save_setup = stm32_fmc2_ebi_mp1_save_setup, 1777 }; 1778 1779 static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp25_data = { 1780 .child_props = stm32_fmc2_mp25_child_props, 1781 .nb_child_props = ARRAY_SIZE(stm32_fmc2_mp25_child_props), 1782 .fmc2_enable_reg = FMC2_CFGR, 1783 .fmc2_enable_bit = FMC2_CFGR_FMC2EN, 1784 .set_setup = stm32_fmc2_ebi_mp25_set_setup, 1785 .save_setup = stm32_fmc2_ebi_mp25_save_setup, 1786 .check_rif = stm32_fmc2_ebi_mp25_check_rif, 1787 .put_sems = stm32_fmc2_ebi_mp25_put_sems, 1788 .get_sems = stm32_fmc2_ebi_mp25_get_sems, 1789 }; 1790 1791 static const struct of_device_id stm32_fmc2_ebi_match[] = { 1792 { 1793 .compatible = "st,stm32mp1-fmc2-ebi", 1794 .data = &stm32_fmc2_ebi_mp1_data, 1795 }, 1796 { 1797 .compatible = "st,stm32mp25-fmc2-ebi", 1798 .data = &stm32_fmc2_ebi_mp25_data, 1799 }, 1800 {} 1801 }; 1802 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); 1803 1804 static struct platform_driver stm32_fmc2_ebi_driver = { 1805 .probe = stm32_fmc2_ebi_probe, 1806 .remove_new = stm32_fmc2_ebi_remove, 1807 .driver = { 1808 .name = "stm32_fmc2_ebi", 1809 .of_match_table = stm32_fmc2_ebi_match, 1810 .pm = &stm32_fmc2_ebi_pm_ops, 1811 }, 1812 }; 1813 module_platform_driver(stm32_fmc2_ebi_driver); 1814 1815 MODULE_ALIAS("platform:stm32_fmc2_ebi"); 1816 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>"); 1817 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver"); 1818 MODULE_LICENSE("GPL v2"); 1819