1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics 2020 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/clk.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_platform.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 17 /* FMC2 Controller Registers */ 18 #define FMC2_BCR1 0x0 19 #define FMC2_BTR1 0x4 20 #define FMC2_BCR(x) ((x) * 0x8 + FMC2_BCR1) 21 #define FMC2_BTR(x) ((x) * 0x8 + FMC2_BTR1) 22 #define FMC2_PCSCNTR 0x20 23 #define FMC2_CFGR 0x20 24 #define FMC2_BWTR1 0x104 25 #define FMC2_BWTR(x) ((x) * 0x8 + FMC2_BWTR1) 26 27 /* Register: FMC2_BCR1 */ 28 #define FMC2_BCR1_CCLKEN BIT(20) 29 #define FMC2_BCR1_FMC2EN BIT(31) 30 31 /* Register: FMC2_BCRx */ 32 #define FMC2_BCR_MBKEN BIT(0) 33 #define FMC2_BCR_MUXEN BIT(1) 34 #define FMC2_BCR_MTYP GENMASK(3, 2) 35 #define FMC2_BCR_MWID GENMASK(5, 4) 36 #define FMC2_BCR_FACCEN BIT(6) 37 #define FMC2_BCR_BURSTEN BIT(8) 38 #define FMC2_BCR_WAITPOL BIT(9) 39 #define FMC2_BCR_WAITCFG BIT(11) 40 #define FMC2_BCR_WREN BIT(12) 41 #define FMC2_BCR_WAITEN BIT(13) 42 #define FMC2_BCR_EXTMOD BIT(14) 43 #define FMC2_BCR_ASYNCWAIT BIT(15) 44 #define FMC2_BCR_CPSIZE GENMASK(18, 16) 45 #define FMC2_BCR_CBURSTRW BIT(19) 46 #define FMC2_BCR_CSCOUNT GENMASK(21, 20) 47 #define FMC2_BCR_NBLSET GENMASK(23, 22) 48 49 /* Register: FMC2_BTRx/FMC2_BWTRx */ 50 #define FMC2_BXTR_ADDSET GENMASK(3, 0) 51 #define FMC2_BXTR_ADDHLD GENMASK(7, 4) 52 #define FMC2_BXTR_DATAST GENMASK(15, 8) 53 #define FMC2_BXTR_BUSTURN GENMASK(19, 16) 54 #define FMC2_BTR_CLKDIV GENMASK(23, 20) 55 #define FMC2_BTR_DATLAT GENMASK(27, 24) 56 #define FMC2_BXTR_ACCMOD GENMASK(29, 28) 57 #define FMC2_BXTR_DATAHLD GENMASK(31, 30) 58 59 /* Register: FMC2_PCSCNTR */ 60 #define FMC2_PCSCNTR_CSCOUNT GENMASK(15, 0) 61 #define FMC2_PCSCNTR_CNTBEN(x) BIT((x) + 16) 62 63 /* Register: FMC2_CFGR */ 64 #define FMC2_CFGR_CLKDIV GENMASK(19, 16) 65 #define FMC2_CFGR_CCLKEN BIT(20) 66 #define FMC2_CFGR_FMC2EN BIT(31) 67 68 #define FMC2_MAX_EBI_CE 4 69 #define FMC2_MAX_BANKS 5 70 71 #define FMC2_BCR_CPSIZE_0 0x0 72 #define FMC2_BCR_CPSIZE_128 0x1 73 #define FMC2_BCR_CPSIZE_256 0x2 74 #define FMC2_BCR_CPSIZE_512 0x3 75 #define FMC2_BCR_CPSIZE_1024 0x4 76 77 #define FMC2_BCR_MWID_8 0x0 78 #define FMC2_BCR_MWID_16 0x1 79 80 #define FMC2_BCR_MTYP_SRAM 0x0 81 #define FMC2_BCR_MTYP_PSRAM 0x1 82 #define FMC2_BCR_MTYP_NOR 0x2 83 84 #define FMC2_BCR_CSCOUNT_0 0x0 85 #define FMC2_BCR_CSCOUNT_1 0x1 86 #define FMC2_BCR_CSCOUNT_64 0x2 87 #define FMC2_BCR_CSCOUNT_256 0x3 88 89 #define FMC2_BXTR_EXTMOD_A 0x0 90 #define FMC2_BXTR_EXTMOD_B 0x1 91 #define FMC2_BXTR_EXTMOD_C 0x2 92 #define FMC2_BXTR_EXTMOD_D 0x3 93 94 #define FMC2_BCR_NBLSET_MAX 0x3 95 #define FMC2_BXTR_ADDSET_MAX 0xf 96 #define FMC2_BXTR_ADDHLD_MAX 0xf 97 #define FMC2_BXTR_DATAST_MAX 0xff 98 #define FMC2_BXTR_BUSTURN_MAX 0xf 99 #define FMC2_BXTR_DATAHLD_MAX 0x3 100 #define FMC2_BTR_CLKDIV_MAX 0xf 101 #define FMC2_BTR_DATLAT_MAX 0xf 102 #define FMC2_PCSCNTR_CSCOUNT_MAX 0xff 103 #define FMC2_CFGR_CLKDIV_MAX 0xf 104 105 enum stm32_fmc2_ebi_bank { 106 FMC2_EBI1 = 0, 107 FMC2_EBI2, 108 FMC2_EBI3, 109 FMC2_EBI4, 110 FMC2_NAND 111 }; 112 113 enum stm32_fmc2_ebi_register_type { 114 FMC2_REG_BCR = 1, 115 FMC2_REG_BTR, 116 FMC2_REG_BWTR, 117 FMC2_REG_PCSCNTR, 118 FMC2_REG_CFGR 119 }; 120 121 enum stm32_fmc2_ebi_transaction_type { 122 FMC2_ASYNC_MODE_1_SRAM = 0, 123 FMC2_ASYNC_MODE_1_PSRAM, 124 FMC2_ASYNC_MODE_A_SRAM, 125 FMC2_ASYNC_MODE_A_PSRAM, 126 FMC2_ASYNC_MODE_2_NOR, 127 FMC2_ASYNC_MODE_B_NOR, 128 FMC2_ASYNC_MODE_C_NOR, 129 FMC2_ASYNC_MODE_D_NOR, 130 FMC2_SYNC_READ_SYNC_WRITE_PSRAM, 131 FMC2_SYNC_READ_ASYNC_WRITE_PSRAM, 132 FMC2_SYNC_READ_SYNC_WRITE_NOR, 133 FMC2_SYNC_READ_ASYNC_WRITE_NOR 134 }; 135 136 enum stm32_fmc2_ebi_buswidth { 137 FMC2_BUSWIDTH_8 = 8, 138 FMC2_BUSWIDTH_16 = 16 139 }; 140 141 enum stm32_fmc2_ebi_cpsize { 142 FMC2_CPSIZE_0 = 0, 143 FMC2_CPSIZE_128 = 128, 144 FMC2_CPSIZE_256 = 256, 145 FMC2_CPSIZE_512 = 512, 146 FMC2_CPSIZE_1024 = 1024 147 }; 148 149 enum stm32_fmc2_ebi_cscount { 150 FMC2_CSCOUNT_0 = 0, 151 FMC2_CSCOUNT_1 = 1, 152 FMC2_CSCOUNT_64 = 64, 153 FMC2_CSCOUNT_256 = 256 154 }; 155 156 struct stm32_fmc2_ebi; 157 158 struct stm32_fmc2_ebi_data { 159 const struct stm32_fmc2_prop *child_props; 160 unsigned int nb_child_props; 161 u32 fmc2_enable_reg; 162 u32 fmc2_enable_bit; 163 int (*nwait_used_by_ctrls)(struct stm32_fmc2_ebi *ebi); 164 void (*set_setup)(struct stm32_fmc2_ebi *ebi); 165 int (*save_setup)(struct stm32_fmc2_ebi *ebi); 166 }; 167 168 struct stm32_fmc2_ebi { 169 struct device *dev; 170 struct clk *clk; 171 struct regmap *regmap; 172 const struct stm32_fmc2_ebi_data *data; 173 u8 bank_assigned; 174 175 u32 bcr[FMC2_MAX_EBI_CE]; 176 u32 btr[FMC2_MAX_EBI_CE]; 177 u32 bwtr[FMC2_MAX_EBI_CE]; 178 u32 pcscntr; 179 u32 cfgr; 180 }; 181 182 /* 183 * struct stm32_fmc2_prop - STM32 FMC2 EBI property 184 * @name: the device tree binding name of the property 185 * @bprop: indicate that it is a boolean property 186 * @mprop: indicate that it is a mandatory property 187 * @reg_type: the register that have to be modified 188 * @reg_mask: the bit that have to be modified in the selected register 189 * in case of it is a boolean property 190 * @reset_val: the default value that have to be set in case the property 191 * has not been defined in the device tree 192 * @check: this callback ckecks that the property is compliant with the 193 * transaction type selected 194 * @calculate: this callback is called to calculate for exemple a timing 195 * set in nanoseconds in the device tree in clock cycles or in 196 * clock period 197 * @set: this callback applies the values in the registers 198 */ 199 struct stm32_fmc2_prop { 200 const char *name; 201 bool bprop; 202 bool mprop; 203 int reg_type; 204 u32 reg_mask; 205 u32 reset_val; 206 int (*check)(struct stm32_fmc2_ebi *ebi, 207 const struct stm32_fmc2_prop *prop, int cs); 208 u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup); 209 int (*set)(struct stm32_fmc2_ebi *ebi, 210 const struct stm32_fmc2_prop *prop, 211 int cs, u32 setup); 212 }; 213 214 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi, 215 const struct stm32_fmc2_prop *prop, 216 int cs) 217 { 218 u32 bcr; 219 int ret; 220 221 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 222 if (ret) 223 return ret; 224 225 if (bcr & FMC2_BCR_MTYP) 226 return 0; 227 228 return -EINVAL; 229 } 230 231 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi, 232 const struct stm32_fmc2_prop *prop, 233 int cs) 234 { 235 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 236 int ret; 237 238 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 239 if (ret) 240 return ret; 241 242 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 243 return 0; 244 245 return -EINVAL; 246 } 247 248 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi, 249 const struct stm32_fmc2_prop *prop, 250 int cs) 251 { 252 u32 bcr; 253 int ret; 254 255 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 256 if (ret) 257 return ret; 258 259 if (bcr & FMC2_BCR_BURSTEN) 260 return 0; 261 262 return -EINVAL; 263 } 264 265 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi, 266 const struct stm32_fmc2_prop *prop, 267 int cs) 268 { 269 u32 bcr; 270 int ret; 271 272 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 273 if (ret) 274 return ret; 275 276 if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) 277 return 0; 278 279 return -EINVAL; 280 } 281 282 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi, 283 const struct stm32_fmc2_prop *prop, 284 int cs) 285 { 286 u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 287 int ret; 288 289 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 290 if (ret) 291 return ret; 292 293 if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN) 294 return 0; 295 296 return -EINVAL; 297 } 298 299 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi, 300 const struct stm32_fmc2_prop *prop, 301 int cs) 302 { 303 u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 304 int ret; 305 306 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 307 if (ret) 308 return ret; 309 310 if (prop->reg_type == FMC2_REG_BWTR) 311 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 312 else 313 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 314 if (ret) 315 return ret; 316 317 if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) && 318 ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)) 319 return 0; 320 321 return -EINVAL; 322 } 323 324 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi, 325 const struct stm32_fmc2_prop *prop, 326 int cs) 327 { 328 u32 bcr, bcr1; 329 int ret; 330 331 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 332 if (ret) 333 return ret; 334 335 if (cs) { 336 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr1); 337 if (ret) 338 return ret; 339 } else { 340 bcr1 = bcr; 341 } 342 343 if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN))) 344 return 0; 345 346 return -EINVAL; 347 } 348 349 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi, 350 const struct stm32_fmc2_prop *prop, 351 int cs) 352 { 353 if (cs) 354 return -EINVAL; 355 356 return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs); 357 } 358 359 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi, 360 int cs, u32 setup) 361 { 362 unsigned long hclk = clk_get_rate(ebi->clk); 363 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 364 365 return DIV_ROUND_UP(setup * 1000, hclkp); 366 } 367 368 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, 369 int cs, u32 setup) 370 { 371 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); 372 u32 bcr, btr, clk_period; 373 int ret; 374 375 ret = regmap_read(ebi->regmap, FMC2_BCR1, &bcr); 376 if (ret) 377 return ret; 378 379 if (bcr & FMC2_BCR1_CCLKEN || !cs) 380 ret = regmap_read(ebi->regmap, FMC2_BTR1, &btr); 381 else 382 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); 383 if (ret) 384 return ret; 385 386 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; 387 388 return DIV_ROUND_UP(nb_clk_cycles, clk_period); 389 } 390 391 static u32 stm32_fmc2_ebi_mp25_ns_to_clk_period(struct stm32_fmc2_ebi *ebi, 392 int cs, u32 setup) 393 { 394 u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup); 395 u32 cfgr, btr, clk_period; 396 int ret; 397 398 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); 399 if (ret) 400 return ret; 401 402 if (cfgr & FMC2_CFGR_CCLKEN) { 403 clk_period = FIELD_GET(FMC2_CFGR_CLKDIV, cfgr) + 1; 404 } else { 405 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &btr); 406 if (ret) 407 return ret; 408 409 clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1; 410 } 411 412 return DIV_ROUND_UP(nb_clk_cycles, clk_period); 413 } 414 415 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg) 416 { 417 switch (reg_type) { 418 case FMC2_REG_BCR: 419 *reg = FMC2_BCR(cs); 420 break; 421 case FMC2_REG_BTR: 422 *reg = FMC2_BTR(cs); 423 break; 424 case FMC2_REG_BWTR: 425 *reg = FMC2_BWTR(cs); 426 break; 427 case FMC2_REG_PCSCNTR: 428 *reg = FMC2_PCSCNTR; 429 break; 430 case FMC2_REG_CFGR: 431 *reg = FMC2_CFGR; 432 break; 433 default: 434 return -EINVAL; 435 } 436 437 return 0; 438 } 439 440 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi, 441 const struct stm32_fmc2_prop *prop, 442 int cs, u32 setup) 443 { 444 u32 reg; 445 int ret; 446 447 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 448 if (ret) 449 return ret; 450 451 regmap_update_bits(ebi->regmap, reg, prop->reg_mask, 452 setup ? prop->reg_mask : 0); 453 454 return 0; 455 } 456 457 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi, 458 const struct stm32_fmc2_prop *prop, 459 int cs, u32 setup) 460 { 461 u32 bcr_mask, bcr = FMC2_BCR_WREN; 462 u32 btr_mask, btr = 0; 463 u32 bwtr_mask, bwtr = 0; 464 465 bwtr_mask = FMC2_BXTR_ACCMOD; 466 btr_mask = FMC2_BXTR_ACCMOD; 467 bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN | 468 FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN | 469 FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW; 470 471 switch (setup) { 472 case FMC2_ASYNC_MODE_1_SRAM: 473 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 474 /* 475 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 476 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 477 */ 478 break; 479 case FMC2_ASYNC_MODE_1_PSRAM: 480 /* 481 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 482 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 483 */ 484 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 485 break; 486 case FMC2_ASYNC_MODE_A_SRAM: 487 /* 488 * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 489 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 490 */ 491 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM); 492 bcr |= FMC2_BCR_EXTMOD; 493 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 494 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 495 break; 496 case FMC2_ASYNC_MODE_A_PSRAM: 497 /* 498 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0, 499 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0 500 */ 501 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 502 bcr |= FMC2_BCR_EXTMOD; 503 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 504 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A); 505 break; 506 case FMC2_ASYNC_MODE_2_NOR: 507 /* 508 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 509 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 510 */ 511 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 512 bcr |= FMC2_BCR_FACCEN; 513 break; 514 case FMC2_ASYNC_MODE_B_NOR: 515 /* 516 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 517 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1 518 */ 519 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 520 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 521 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 522 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B); 523 break; 524 case FMC2_ASYNC_MODE_C_NOR: 525 /* 526 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 527 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2 528 */ 529 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 530 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 531 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 532 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C); 533 break; 534 case FMC2_ASYNC_MODE_D_NOR: 535 /* 536 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0, 537 * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3 538 */ 539 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 540 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD; 541 btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 542 bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 543 break; 544 case FMC2_SYNC_READ_SYNC_WRITE_PSRAM: 545 /* 546 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 547 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 548 */ 549 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 550 bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 551 break; 552 case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM: 553 /* 554 * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0, 555 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 556 */ 557 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM); 558 bcr |= FMC2_BCR_BURSTEN; 559 break; 560 case FMC2_SYNC_READ_SYNC_WRITE_NOR: 561 /* 562 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 563 * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0 564 */ 565 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 566 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW; 567 break; 568 case FMC2_SYNC_READ_ASYNC_WRITE_NOR: 569 /* 570 * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0, 571 * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0 572 */ 573 bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR); 574 bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN; 575 break; 576 default: 577 /* Type of transaction not supported */ 578 return -EINVAL; 579 } 580 581 if (bcr & FMC2_BCR_EXTMOD) 582 regmap_update_bits(ebi->regmap, FMC2_BWTR(cs), 583 bwtr_mask, bwtr); 584 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr); 585 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr); 586 587 return 0; 588 } 589 590 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi, 591 const struct stm32_fmc2_prop *prop, 592 int cs, u32 setup) 593 { 594 u32 val; 595 596 switch (setup) { 597 case FMC2_BUSWIDTH_8: 598 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8); 599 break; 600 case FMC2_BUSWIDTH_16: 601 val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16); 602 break; 603 default: 604 /* Buswidth not supported */ 605 return -EINVAL; 606 } 607 608 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val); 609 610 return 0; 611 } 612 613 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi, 614 const struct stm32_fmc2_prop *prop, 615 int cs, u32 setup) 616 { 617 u32 val; 618 619 switch (setup) { 620 case FMC2_CPSIZE_0: 621 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0); 622 break; 623 case FMC2_CPSIZE_128: 624 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128); 625 break; 626 case FMC2_CPSIZE_256: 627 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256); 628 break; 629 case FMC2_CPSIZE_512: 630 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512); 631 break; 632 case FMC2_CPSIZE_1024: 633 val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024); 634 break; 635 default: 636 /* Cpsize not supported */ 637 return -EINVAL; 638 } 639 640 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val); 641 642 return 0; 643 } 644 645 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi, 646 const struct stm32_fmc2_prop *prop, 647 int cs, u32 setup) 648 { 649 u32 val; 650 651 val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX); 652 val = FIELD_PREP(FMC2_BCR_NBLSET, val); 653 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val); 654 655 return 0; 656 } 657 658 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi, 659 const struct stm32_fmc2_prop *prop, 660 int cs, u32 setup) 661 { 662 u32 bcr, bxtr, reg; 663 u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D); 664 int ret; 665 666 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 667 if (ret) 668 return ret; 669 670 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 671 if (ret) 672 return ret; 673 674 if (prop->reg_type == FMC2_REG_BWTR) 675 ret = regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr); 676 else 677 ret = regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr); 678 if (ret) 679 return ret; 680 681 if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN) 682 val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX); 683 else 684 val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX); 685 val = FIELD_PREP(FMC2_BXTR_ADDSET, val); 686 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val); 687 688 return 0; 689 } 690 691 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi, 692 const struct stm32_fmc2_prop *prop, 693 int cs, u32 setup) 694 { 695 u32 val, reg; 696 int ret; 697 698 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 699 if (ret) 700 return ret; 701 702 val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX); 703 val = FIELD_PREP(FMC2_BXTR_ADDHLD, val); 704 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val); 705 706 return 0; 707 } 708 709 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi, 710 const struct stm32_fmc2_prop *prop, 711 int cs, u32 setup) 712 { 713 u32 val, reg; 714 int ret; 715 716 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 717 if (ret) 718 return ret; 719 720 val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX); 721 val = FIELD_PREP(FMC2_BXTR_DATAST, val); 722 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val); 723 724 return 0; 725 } 726 727 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi, 728 const struct stm32_fmc2_prop *prop, 729 int cs, u32 setup) 730 { 731 u32 val, reg; 732 int ret; 733 734 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 735 if (ret) 736 return ret; 737 738 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0; 739 val = FIELD_PREP(FMC2_BXTR_BUSTURN, val); 740 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val); 741 742 return 0; 743 } 744 745 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi, 746 const struct stm32_fmc2_prop *prop, 747 int cs, u32 setup) 748 { 749 u32 val, reg; 750 int ret; 751 752 ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, ®); 753 if (ret) 754 return ret; 755 756 if (prop->reg_type == FMC2_REG_BWTR) 757 val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0; 758 else 759 val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX); 760 val = FIELD_PREP(FMC2_BXTR_DATAHLD, val); 761 regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val); 762 763 return 0; 764 } 765 766 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi, 767 const struct stm32_fmc2_prop *prop, 768 int cs, u32 setup) 769 { 770 u32 val; 771 772 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; 773 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); 774 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); 775 776 return 0; 777 } 778 779 static int stm32_fmc2_ebi_mp25_set_clk_period(struct stm32_fmc2_ebi *ebi, 780 const struct stm32_fmc2_prop *prop, 781 int cs, u32 setup) 782 { 783 u32 val, cfgr; 784 int ret; 785 786 ret = regmap_read(ebi->regmap, FMC2_CFGR, &cfgr); 787 if (ret) 788 return ret; 789 790 if (cfgr & FMC2_CFGR_CCLKEN) { 791 val = setup ? clamp_val(setup - 1, 1, FMC2_CFGR_CLKDIV_MAX) : 1; 792 val = FIELD_PREP(FMC2_CFGR_CLKDIV, val); 793 regmap_update_bits(ebi->regmap, FMC2_CFGR, FMC2_CFGR_CLKDIV, val); 794 } else { 795 val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1; 796 val = FIELD_PREP(FMC2_BTR_CLKDIV, val); 797 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val); 798 } 799 800 return 0; 801 } 802 803 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi, 804 const struct stm32_fmc2_prop *prop, 805 int cs, u32 setup) 806 { 807 u32 val; 808 809 val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0; 810 val = FIELD_PREP(FMC2_BTR_DATLAT, val); 811 regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val); 812 813 return 0; 814 } 815 816 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, 817 const struct stm32_fmc2_prop *prop, 818 int cs, u32 setup) 819 { 820 u32 old_val, new_val, pcscntr; 821 int ret; 822 823 if (setup < 1) 824 return 0; 825 826 ret = regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr); 827 if (ret) 828 return ret; 829 830 /* Enable counter for the bank */ 831 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 832 FMC2_PCSCNTR_CNTBEN(cs), 833 FMC2_PCSCNTR_CNTBEN(cs)); 834 835 new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX); 836 old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr); 837 if (old_val && new_val > old_val) 838 /* Keep current counter value */ 839 return 0; 840 841 new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val); 842 regmap_update_bits(ebi->regmap, FMC2_PCSCNTR, 843 FMC2_PCSCNTR_CSCOUNT, new_val); 844 845 return 0; 846 } 847 848 static int stm32_fmc2_ebi_mp25_set_max_low_pulse(struct stm32_fmc2_ebi *ebi, 849 const struct stm32_fmc2_prop *prop, 850 int cs, u32 setup) 851 { 852 u32 val; 853 854 if (setup == FMC2_CSCOUNT_0) 855 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_0); 856 else if (setup == FMC2_CSCOUNT_1) 857 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_1); 858 else if (setup <= FMC2_CSCOUNT_64) 859 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_64); 860 else 861 val = FIELD_PREP(FMC2_BCR_CSCOUNT, FMC2_BCR_CSCOUNT_256); 862 863 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), 864 FMC2_BCR_CSCOUNT, val); 865 866 return 0; 867 } 868 869 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = { 870 /* st,fmc2-ebi-cs-trans-type must be the first property */ 871 { 872 .name = "st,fmc2-ebi-cs-transaction-type", 873 .mprop = true, 874 .set = stm32_fmc2_ebi_set_trans_type, 875 }, 876 { 877 .name = "st,fmc2-ebi-cs-cclk-enable", 878 .bprop = true, 879 .reg_type = FMC2_REG_BCR, 880 .reg_mask = FMC2_BCR1_CCLKEN, 881 .check = stm32_fmc2_ebi_check_cclk, 882 .set = stm32_fmc2_ebi_set_bit_field, 883 }, 884 { 885 .name = "st,fmc2-ebi-cs-mux-enable", 886 .bprop = true, 887 .reg_type = FMC2_REG_BCR, 888 .reg_mask = FMC2_BCR_MUXEN, 889 .check = stm32_fmc2_ebi_check_mux, 890 .set = stm32_fmc2_ebi_set_bit_field, 891 }, 892 { 893 .name = "st,fmc2-ebi-cs-buswidth", 894 .reset_val = FMC2_BUSWIDTH_16, 895 .set = stm32_fmc2_ebi_set_buswidth, 896 }, 897 { 898 .name = "st,fmc2-ebi-cs-waitpol-high", 899 .bprop = true, 900 .reg_type = FMC2_REG_BCR, 901 .reg_mask = FMC2_BCR_WAITPOL, 902 .set = stm32_fmc2_ebi_set_bit_field, 903 }, 904 { 905 .name = "st,fmc2-ebi-cs-waitcfg-enable", 906 .bprop = true, 907 .reg_type = FMC2_REG_BCR, 908 .reg_mask = FMC2_BCR_WAITCFG, 909 .check = stm32_fmc2_ebi_check_waitcfg, 910 .set = stm32_fmc2_ebi_set_bit_field, 911 }, 912 { 913 .name = "st,fmc2-ebi-cs-wait-enable", 914 .bprop = true, 915 .reg_type = FMC2_REG_BCR, 916 .reg_mask = FMC2_BCR_WAITEN, 917 .check = stm32_fmc2_ebi_check_sync_trans, 918 .set = stm32_fmc2_ebi_set_bit_field, 919 }, 920 { 921 .name = "st,fmc2-ebi-cs-asyncwait-enable", 922 .bprop = true, 923 .reg_type = FMC2_REG_BCR, 924 .reg_mask = FMC2_BCR_ASYNCWAIT, 925 .check = stm32_fmc2_ebi_check_async_trans, 926 .set = stm32_fmc2_ebi_set_bit_field, 927 }, 928 { 929 .name = "st,fmc2-ebi-cs-cpsize", 930 .check = stm32_fmc2_ebi_check_cpsize, 931 .set = stm32_fmc2_ebi_set_cpsize, 932 }, 933 { 934 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", 935 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 936 .set = stm32_fmc2_ebi_set_bl_setup, 937 }, 938 { 939 .name = "st,fmc2-ebi-cs-address-setup-ns", 940 .reg_type = FMC2_REG_BTR, 941 .reset_val = FMC2_BXTR_ADDSET_MAX, 942 .check = stm32_fmc2_ebi_check_async_trans, 943 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 944 .set = stm32_fmc2_ebi_set_address_setup, 945 }, 946 { 947 .name = "st,fmc2-ebi-cs-address-hold-ns", 948 .reg_type = FMC2_REG_BTR, 949 .reset_val = FMC2_BXTR_ADDHLD_MAX, 950 .check = stm32_fmc2_ebi_check_address_hold, 951 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 952 .set = stm32_fmc2_ebi_set_address_hold, 953 }, 954 { 955 .name = "st,fmc2-ebi-cs-data-setup-ns", 956 .reg_type = FMC2_REG_BTR, 957 .reset_val = FMC2_BXTR_DATAST_MAX, 958 .check = stm32_fmc2_ebi_check_async_trans, 959 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 960 .set = stm32_fmc2_ebi_set_data_setup, 961 }, 962 { 963 .name = "st,fmc2-ebi-cs-bus-turnaround-ns", 964 .reg_type = FMC2_REG_BTR, 965 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 966 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 967 .set = stm32_fmc2_ebi_set_bus_turnaround, 968 }, 969 { 970 .name = "st,fmc2-ebi-cs-data-hold-ns", 971 .reg_type = FMC2_REG_BTR, 972 .check = stm32_fmc2_ebi_check_async_trans, 973 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 974 .set = stm32_fmc2_ebi_set_data_hold, 975 }, 976 { 977 .name = "st,fmc2-ebi-cs-clk-period-ns", 978 .reset_val = FMC2_BTR_CLKDIV_MAX + 1, 979 .check = stm32_fmc2_ebi_check_clk_period, 980 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 981 .set = stm32_fmc2_ebi_set_clk_period, 982 }, 983 { 984 .name = "st,fmc2-ebi-cs-data-latency-ns", 985 .check = stm32_fmc2_ebi_check_sync_trans, 986 .calculate = stm32_fmc2_ebi_ns_to_clk_period, 987 .set = stm32_fmc2_ebi_set_data_latency, 988 }, 989 { 990 .name = "st,fmc2-ebi-cs-write-address-setup-ns", 991 .reg_type = FMC2_REG_BWTR, 992 .reset_val = FMC2_BXTR_ADDSET_MAX, 993 .check = stm32_fmc2_ebi_check_async_trans, 994 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 995 .set = stm32_fmc2_ebi_set_address_setup, 996 }, 997 { 998 .name = "st,fmc2-ebi-cs-write-address-hold-ns", 999 .reg_type = FMC2_REG_BWTR, 1000 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1001 .check = stm32_fmc2_ebi_check_address_hold, 1002 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1003 .set = stm32_fmc2_ebi_set_address_hold, 1004 }, 1005 { 1006 .name = "st,fmc2-ebi-cs-write-data-setup-ns", 1007 .reg_type = FMC2_REG_BWTR, 1008 .reset_val = FMC2_BXTR_DATAST_MAX, 1009 .check = stm32_fmc2_ebi_check_async_trans, 1010 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1011 .set = stm32_fmc2_ebi_set_data_setup, 1012 }, 1013 { 1014 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", 1015 .reg_type = FMC2_REG_BWTR, 1016 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1017 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1018 .set = stm32_fmc2_ebi_set_bus_turnaround, 1019 }, 1020 { 1021 .name = "st,fmc2-ebi-cs-write-data-hold-ns", 1022 .reg_type = FMC2_REG_BWTR, 1023 .check = stm32_fmc2_ebi_check_async_trans, 1024 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1025 .set = stm32_fmc2_ebi_set_data_hold, 1026 }, 1027 { 1028 .name = "st,fmc2-ebi-cs-max-low-pulse-ns", 1029 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1030 .set = stm32_fmc2_ebi_set_max_low_pulse, 1031 }, 1032 }; 1033 1034 static const struct stm32_fmc2_prop stm32_fmc2_mp25_child_props[] = { 1035 /* st,fmc2-ebi-cs-trans-type must be the first property */ 1036 { 1037 .name = "st,fmc2-ebi-cs-transaction-type", 1038 .mprop = true, 1039 .set = stm32_fmc2_ebi_set_trans_type, 1040 }, 1041 { 1042 .name = "st,fmc2-ebi-cs-cclk-enable", 1043 .bprop = true, 1044 .reg_type = FMC2_REG_CFGR, 1045 .reg_mask = FMC2_CFGR_CCLKEN, 1046 .check = stm32_fmc2_ebi_check_sync_trans, 1047 .set = stm32_fmc2_ebi_set_bit_field, 1048 }, 1049 { 1050 .name = "st,fmc2-ebi-cs-mux-enable", 1051 .bprop = true, 1052 .reg_type = FMC2_REG_BCR, 1053 .reg_mask = FMC2_BCR_MUXEN, 1054 .check = stm32_fmc2_ebi_check_mux, 1055 .set = stm32_fmc2_ebi_set_bit_field, 1056 }, 1057 { 1058 .name = "st,fmc2-ebi-cs-buswidth", 1059 .reset_val = FMC2_BUSWIDTH_16, 1060 .set = stm32_fmc2_ebi_set_buswidth, 1061 }, 1062 { 1063 .name = "st,fmc2-ebi-cs-waitpol-high", 1064 .bprop = true, 1065 .reg_type = FMC2_REG_BCR, 1066 .reg_mask = FMC2_BCR_WAITPOL, 1067 .set = stm32_fmc2_ebi_set_bit_field, 1068 }, 1069 { 1070 .name = "st,fmc2-ebi-cs-waitcfg-enable", 1071 .bprop = true, 1072 .reg_type = FMC2_REG_BCR, 1073 .reg_mask = FMC2_BCR_WAITCFG, 1074 .check = stm32_fmc2_ebi_check_waitcfg, 1075 .set = stm32_fmc2_ebi_set_bit_field, 1076 }, 1077 { 1078 .name = "st,fmc2-ebi-cs-wait-enable", 1079 .bprop = true, 1080 .reg_type = FMC2_REG_BCR, 1081 .reg_mask = FMC2_BCR_WAITEN, 1082 .check = stm32_fmc2_ebi_check_sync_trans, 1083 .set = stm32_fmc2_ebi_set_bit_field, 1084 }, 1085 { 1086 .name = "st,fmc2-ebi-cs-asyncwait-enable", 1087 .bprop = true, 1088 .reg_type = FMC2_REG_BCR, 1089 .reg_mask = FMC2_BCR_ASYNCWAIT, 1090 .check = stm32_fmc2_ebi_check_async_trans, 1091 .set = stm32_fmc2_ebi_set_bit_field, 1092 }, 1093 { 1094 .name = "st,fmc2-ebi-cs-cpsize", 1095 .check = stm32_fmc2_ebi_check_cpsize, 1096 .set = stm32_fmc2_ebi_set_cpsize, 1097 }, 1098 { 1099 .name = "st,fmc2-ebi-cs-byte-lane-setup-ns", 1100 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1101 .set = stm32_fmc2_ebi_set_bl_setup, 1102 }, 1103 { 1104 .name = "st,fmc2-ebi-cs-address-setup-ns", 1105 .reg_type = FMC2_REG_BTR, 1106 .reset_val = FMC2_BXTR_ADDSET_MAX, 1107 .check = stm32_fmc2_ebi_check_async_trans, 1108 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1109 .set = stm32_fmc2_ebi_set_address_setup, 1110 }, 1111 { 1112 .name = "st,fmc2-ebi-cs-address-hold-ns", 1113 .reg_type = FMC2_REG_BTR, 1114 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1115 .check = stm32_fmc2_ebi_check_address_hold, 1116 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1117 .set = stm32_fmc2_ebi_set_address_hold, 1118 }, 1119 { 1120 .name = "st,fmc2-ebi-cs-data-setup-ns", 1121 .reg_type = FMC2_REG_BTR, 1122 .reset_val = FMC2_BXTR_DATAST_MAX, 1123 .check = stm32_fmc2_ebi_check_async_trans, 1124 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1125 .set = stm32_fmc2_ebi_set_data_setup, 1126 }, 1127 { 1128 .name = "st,fmc2-ebi-cs-bus-turnaround-ns", 1129 .reg_type = FMC2_REG_BTR, 1130 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1131 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1132 .set = stm32_fmc2_ebi_set_bus_turnaround, 1133 }, 1134 { 1135 .name = "st,fmc2-ebi-cs-data-hold-ns", 1136 .reg_type = FMC2_REG_BTR, 1137 .check = stm32_fmc2_ebi_check_async_trans, 1138 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1139 .set = stm32_fmc2_ebi_set_data_hold, 1140 }, 1141 { 1142 .name = "st,fmc2-ebi-cs-clk-period-ns", 1143 .reset_val = FMC2_CFGR_CLKDIV_MAX + 1, 1144 .check = stm32_fmc2_ebi_check_sync_trans, 1145 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1146 .set = stm32_fmc2_ebi_mp25_set_clk_period, 1147 }, 1148 { 1149 .name = "st,fmc2-ebi-cs-data-latency-ns", 1150 .check = stm32_fmc2_ebi_check_sync_trans, 1151 .calculate = stm32_fmc2_ebi_mp25_ns_to_clk_period, 1152 .set = stm32_fmc2_ebi_set_data_latency, 1153 }, 1154 { 1155 .name = "st,fmc2-ebi-cs-write-address-setup-ns", 1156 .reg_type = FMC2_REG_BWTR, 1157 .reset_val = FMC2_BXTR_ADDSET_MAX, 1158 .check = stm32_fmc2_ebi_check_async_trans, 1159 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1160 .set = stm32_fmc2_ebi_set_address_setup, 1161 }, 1162 { 1163 .name = "st,fmc2-ebi-cs-write-address-hold-ns", 1164 .reg_type = FMC2_REG_BWTR, 1165 .reset_val = FMC2_BXTR_ADDHLD_MAX, 1166 .check = stm32_fmc2_ebi_check_address_hold, 1167 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1168 .set = stm32_fmc2_ebi_set_address_hold, 1169 }, 1170 { 1171 .name = "st,fmc2-ebi-cs-write-data-setup-ns", 1172 .reg_type = FMC2_REG_BWTR, 1173 .reset_val = FMC2_BXTR_DATAST_MAX, 1174 .check = stm32_fmc2_ebi_check_async_trans, 1175 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1176 .set = stm32_fmc2_ebi_set_data_setup, 1177 }, 1178 { 1179 .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns", 1180 .reg_type = FMC2_REG_BWTR, 1181 .reset_val = FMC2_BXTR_BUSTURN_MAX + 1, 1182 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1183 .set = stm32_fmc2_ebi_set_bus_turnaround, 1184 }, 1185 { 1186 .name = "st,fmc2-ebi-cs-write-data-hold-ns", 1187 .reg_type = FMC2_REG_BWTR, 1188 .check = stm32_fmc2_ebi_check_async_trans, 1189 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1190 .set = stm32_fmc2_ebi_set_data_hold, 1191 }, 1192 { 1193 .name = "st,fmc2-ebi-cs-max-low-pulse-ns", 1194 .calculate = stm32_fmc2_ebi_ns_to_clock_cycles, 1195 .set = stm32_fmc2_ebi_mp25_set_max_low_pulse, 1196 }, 1197 }; 1198 1199 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi, 1200 struct device_node *dev_node, 1201 const struct stm32_fmc2_prop *prop, 1202 int cs) 1203 { 1204 struct device *dev = ebi->dev; 1205 u32 setup = 0; 1206 1207 if (!prop->set) { 1208 dev_err(dev, "property %s is not well defined\n", prop->name); 1209 return -EINVAL; 1210 } 1211 1212 if (prop->check && prop->check(ebi, prop, cs)) 1213 /* Skeep this property */ 1214 return 0; 1215 1216 if (prop->bprop) { 1217 bool bprop; 1218 1219 bprop = of_property_read_bool(dev_node, prop->name); 1220 if (prop->mprop && !bprop) { 1221 dev_err(dev, "mandatory property %s not defined in the device tree\n", 1222 prop->name); 1223 return -EINVAL; 1224 } 1225 1226 if (bprop) 1227 setup = 1; 1228 } else { 1229 u32 val; 1230 int ret; 1231 1232 ret = of_property_read_u32(dev_node, prop->name, &val); 1233 if (prop->mprop && ret) { 1234 dev_err(dev, "mandatory property %s not defined in the device tree\n", 1235 prop->name); 1236 return ret; 1237 } 1238 1239 if (ret) 1240 setup = prop->reset_val; 1241 else if (prop->calculate) 1242 setup = prop->calculate(ebi, cs, val); 1243 else 1244 setup = val; 1245 } 1246 1247 return prop->set(ebi, prop, cs, setup); 1248 } 1249 1250 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs) 1251 { 1252 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), 1253 FMC2_BCR_MBKEN, FMC2_BCR_MBKEN); 1254 } 1255 1256 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs) 1257 { 1258 regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0); 1259 } 1260 1261 static int stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi) 1262 { 1263 unsigned int cs; 1264 int ret; 1265 1266 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1267 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]); 1268 ret |= regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]); 1269 ret |= regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]); 1270 if (ret) 1271 return ret; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static int stm32_fmc2_ebi_mp1_save_setup(struct stm32_fmc2_ebi *ebi) 1278 { 1279 int ret; 1280 1281 ret = stm32_fmc2_ebi_save_setup(ebi); 1282 if (ret) 1283 return ret; 1284 1285 return regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr); 1286 } 1287 1288 static int stm32_fmc2_ebi_mp25_save_setup(struct stm32_fmc2_ebi *ebi) 1289 { 1290 int ret; 1291 1292 ret = stm32_fmc2_ebi_save_setup(ebi); 1293 if (ret) 1294 return ret; 1295 1296 return regmap_read(ebi->regmap, FMC2_CFGR, &ebi->cfgr); 1297 } 1298 1299 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi) 1300 { 1301 unsigned int cs; 1302 1303 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1304 regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]); 1305 regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]); 1306 regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]); 1307 } 1308 } 1309 1310 static void stm32_fmc2_ebi_mp1_set_setup(struct stm32_fmc2_ebi *ebi) 1311 { 1312 stm32_fmc2_ebi_set_setup(ebi); 1313 regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr); 1314 } 1315 1316 static void stm32_fmc2_ebi_mp25_set_setup(struct stm32_fmc2_ebi *ebi) 1317 { 1318 stm32_fmc2_ebi_set_setup(ebi); 1319 regmap_write(ebi->regmap, FMC2_CFGR, ebi->cfgr); 1320 } 1321 1322 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi) 1323 { 1324 unsigned int cs; 1325 1326 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1327 if (!(ebi->bank_assigned & BIT(cs))) 1328 continue; 1329 1330 stm32_fmc2_ebi_disable_bank(ebi, cs); 1331 } 1332 } 1333 1334 /* NWAIT signal can not be connected to EBI controller and NAND controller */ 1335 static int stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi) 1336 { 1337 struct device *dev = ebi->dev; 1338 unsigned int cs; 1339 u32 bcr; 1340 int ret; 1341 1342 for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) { 1343 if (!(ebi->bank_assigned & BIT(cs))) 1344 continue; 1345 1346 ret = regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr); 1347 if (ret) 1348 return ret; 1349 1350 if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) && 1351 ebi->bank_assigned & BIT(FMC2_NAND)) { 1352 dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n"); 1353 return -EINVAL; 1354 } 1355 } 1356 1357 return 0; 1358 } 1359 1360 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi) 1361 { 1362 regmap_update_bits(ebi->regmap, ebi->data->fmc2_enable_reg, 1363 ebi->data->fmc2_enable_bit, 1364 ebi->data->fmc2_enable_bit); 1365 } 1366 1367 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi) 1368 { 1369 regmap_update_bits(ebi->regmap, ebi->data->fmc2_enable_reg, 1370 ebi->data->fmc2_enable_bit, 0); 1371 } 1372 1373 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi, 1374 struct device_node *dev_node, 1375 u32 cs) 1376 { 1377 unsigned int i; 1378 int ret; 1379 1380 stm32_fmc2_ebi_disable_bank(ebi, cs); 1381 1382 for (i = 0; i < ebi->data->nb_child_props; i++) { 1383 const struct stm32_fmc2_prop *p = &ebi->data->child_props[i]; 1384 1385 ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs); 1386 if (ret) { 1387 dev_err(ebi->dev, "property %s could not be set: %d\n", 1388 p->name, ret); 1389 return ret; 1390 } 1391 } 1392 1393 stm32_fmc2_ebi_enable_bank(ebi, cs); 1394 1395 return 0; 1396 } 1397 1398 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi) 1399 { 1400 struct device *dev = ebi->dev; 1401 struct device_node *child; 1402 bool child_found = false; 1403 u32 bank; 1404 int ret; 1405 1406 for_each_available_child_of_node(dev->of_node, child) { 1407 ret = of_property_read_u32(child, "reg", &bank); 1408 if (ret) { 1409 dev_err(dev, "could not retrieve reg property: %d\n", 1410 ret); 1411 of_node_put(child); 1412 return ret; 1413 } 1414 1415 if (bank >= FMC2_MAX_BANKS) { 1416 dev_err(dev, "invalid reg value: %d\n", bank); 1417 of_node_put(child); 1418 return -EINVAL; 1419 } 1420 1421 if (ebi->bank_assigned & BIT(bank)) { 1422 dev_err(dev, "bank already assigned: %d\n", bank); 1423 of_node_put(child); 1424 return -EINVAL; 1425 } 1426 1427 if (bank < FMC2_MAX_EBI_CE) { 1428 ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank); 1429 if (ret) { 1430 dev_err(dev, "setup chip select %d failed: %d\n", 1431 bank, ret); 1432 of_node_put(child); 1433 return ret; 1434 } 1435 } 1436 1437 ebi->bank_assigned |= BIT(bank); 1438 child_found = true; 1439 } 1440 1441 if (!child_found) { 1442 dev_warn(dev, "no subnodes found, disable the driver.\n"); 1443 return -ENODEV; 1444 } 1445 1446 if (ebi->data->nwait_used_by_ctrls) { 1447 ret = ebi->data->nwait_used_by_ctrls(ebi); 1448 if (ret) 1449 return ret; 1450 } 1451 1452 stm32_fmc2_ebi_enable(ebi); 1453 1454 return of_platform_populate(dev->of_node, NULL, NULL, dev); 1455 } 1456 1457 static int stm32_fmc2_ebi_probe(struct platform_device *pdev) 1458 { 1459 struct device *dev = &pdev->dev; 1460 struct stm32_fmc2_ebi *ebi; 1461 struct reset_control *rstc; 1462 int ret; 1463 1464 ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL); 1465 if (!ebi) 1466 return -ENOMEM; 1467 1468 ebi->dev = dev; 1469 1470 ebi->data = of_device_get_match_data(dev); 1471 if (!ebi->data) 1472 return -EINVAL; 1473 1474 ebi->regmap = device_node_to_regmap(dev->of_node); 1475 if (IS_ERR(ebi->regmap)) 1476 return PTR_ERR(ebi->regmap); 1477 1478 ebi->clk = devm_clk_get(dev, NULL); 1479 if (IS_ERR(ebi->clk)) 1480 return PTR_ERR(ebi->clk); 1481 1482 rstc = devm_reset_control_get(dev, NULL); 1483 if (PTR_ERR(rstc) == -EPROBE_DEFER) 1484 return -EPROBE_DEFER; 1485 1486 ret = clk_prepare_enable(ebi->clk); 1487 if (ret) 1488 return ret; 1489 1490 if (!IS_ERR(rstc)) { 1491 reset_control_assert(rstc); 1492 reset_control_deassert(rstc); 1493 } 1494 1495 ret = stm32_fmc2_ebi_parse_dt(ebi); 1496 if (ret) 1497 goto err_release; 1498 1499 ret = ebi->data->save_setup(ebi); 1500 if (ret) 1501 goto err_release; 1502 1503 platform_set_drvdata(pdev, ebi); 1504 1505 return 0; 1506 1507 err_release: 1508 stm32_fmc2_ebi_disable_banks(ebi); 1509 stm32_fmc2_ebi_disable(ebi); 1510 clk_disable_unprepare(ebi->clk); 1511 1512 return ret; 1513 } 1514 1515 static void stm32_fmc2_ebi_remove(struct platform_device *pdev) 1516 { 1517 struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev); 1518 1519 of_platform_depopulate(&pdev->dev); 1520 stm32_fmc2_ebi_disable_banks(ebi); 1521 stm32_fmc2_ebi_disable(ebi); 1522 clk_disable_unprepare(ebi->clk); 1523 } 1524 1525 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev) 1526 { 1527 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1528 1529 stm32_fmc2_ebi_disable(ebi); 1530 clk_disable_unprepare(ebi->clk); 1531 pinctrl_pm_select_sleep_state(dev); 1532 1533 return 0; 1534 } 1535 1536 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) 1537 { 1538 struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev); 1539 int ret; 1540 1541 pinctrl_pm_select_default_state(dev); 1542 1543 ret = clk_prepare_enable(ebi->clk); 1544 if (ret) 1545 return ret; 1546 1547 ebi->data->set_setup(ebi); 1548 stm32_fmc2_ebi_enable(ebi); 1549 1550 return 0; 1551 } 1552 1553 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend, 1554 stm32_fmc2_ebi_resume); 1555 1556 static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp1_data = { 1557 .child_props = stm32_fmc2_child_props, 1558 .nb_child_props = ARRAY_SIZE(stm32_fmc2_child_props), 1559 .fmc2_enable_reg = FMC2_BCR1, 1560 .fmc2_enable_bit = FMC2_BCR1_FMC2EN, 1561 .nwait_used_by_ctrls = stm32_fmc2_ebi_nwait_used_by_ctrls, 1562 .set_setup = stm32_fmc2_ebi_mp1_set_setup, 1563 .save_setup = stm32_fmc2_ebi_mp1_save_setup, 1564 }; 1565 1566 static const struct stm32_fmc2_ebi_data stm32_fmc2_ebi_mp25_data = { 1567 .child_props = stm32_fmc2_mp25_child_props, 1568 .nb_child_props = ARRAY_SIZE(stm32_fmc2_mp25_child_props), 1569 .fmc2_enable_reg = FMC2_CFGR, 1570 .fmc2_enable_bit = FMC2_CFGR_FMC2EN, 1571 .set_setup = stm32_fmc2_ebi_mp25_set_setup, 1572 .save_setup = stm32_fmc2_ebi_mp25_save_setup, 1573 }; 1574 1575 static const struct of_device_id stm32_fmc2_ebi_match[] = { 1576 { 1577 .compatible = "st,stm32mp1-fmc2-ebi", 1578 .data = &stm32_fmc2_ebi_mp1_data, 1579 }, 1580 { 1581 .compatible = "st,stm32mp25-fmc2-ebi", 1582 .data = &stm32_fmc2_ebi_mp25_data, 1583 }, 1584 {} 1585 }; 1586 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match); 1587 1588 static struct platform_driver stm32_fmc2_ebi_driver = { 1589 .probe = stm32_fmc2_ebi_probe, 1590 .remove_new = stm32_fmc2_ebi_remove, 1591 .driver = { 1592 .name = "stm32_fmc2_ebi", 1593 .of_match_table = stm32_fmc2_ebi_match, 1594 .pm = &stm32_fmc2_ebi_pm_ops, 1595 }, 1596 }; 1597 module_platform_driver(stm32_fmc2_ebi_driver); 1598 1599 MODULE_ALIAS("platform:stm32_fmc2_ebi"); 1600 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>"); 1601 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver"); 1602 MODULE_LICENSE("GPL v2"); 1603