1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RPC-IF core driver 4 * 5 * Copyright (C) 2018-2019 Renesas Solutions Corp. 6 * Copyright (C) 2019 Macronix International Co., Ltd. 7 * Copyright (C) 2019-2020 Cogent Embedded, Inc. 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <memory/renesas-rpc-if.h> 20 21 #include "renesas-rpc-if-regs.h" 22 #include "renesas-xspi-if-regs.h" 23 24 static const struct regmap_range rpcif_volatile_ranges[] = { 25 regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1), 26 regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1), 27 regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR), 28 }; 29 30 static const struct regmap_access_table rpcif_volatile_table = { 31 .yes_ranges = rpcif_volatile_ranges, 32 .n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges), 33 }; 34 35 static const struct regmap_range xspi_volatile_ranges[] = { 36 regmap_reg_range(XSPI_CDD0BUF0, XSPI_CDD0BUF0), 37 regmap_reg_range(XSPI_CDD1BUF0, XSPI_CDD1BUF0), 38 }; 39 40 static const struct regmap_access_table xspi_volatile_table = { 41 .yes_ranges = xspi_volatile_ranges, 42 .n_yes_ranges = ARRAY_SIZE(xspi_volatile_ranges), 43 }; 44 45 struct rpcif_priv; 46 47 struct rpcif_impl { 48 int (*hw_init)(struct rpcif_priv *rpc, bool hyperflash); 49 void (*prepare)(struct rpcif_priv *rpc, const struct rpcif_op *op, 50 u64 *offs, size_t *len); 51 int (*manual_xfer)(struct rpcif_priv *rpc); 52 size_t (*dirmap_read)(struct rpcif_priv *rpc, u64 offs, size_t len, 53 void *buf); 54 u32 status_reg; 55 u32 status_mask; 56 }; 57 58 struct rpcif_info { 59 const struct regmap_config *regmap_config; 60 const struct rpcif_impl *impl; 61 enum rpcif_type type; 62 u8 strtim; 63 }; 64 65 struct rpcif_priv { 66 struct device *dev; 67 void __iomem *base; 68 void __iomem *dirmap; 69 struct regmap *regmap; 70 struct reset_control *rstc; 71 struct clk *spi_clk; 72 struct clk *spix2_clk; 73 struct platform_device *vdev; 74 size_t size; 75 const struct rpcif_info *info; 76 enum rpcif_data_dir dir; 77 u8 bus_size; 78 u8 xfer_size; 79 u8 addr_nbytes; /* Specified for xSPI */ 80 u32 proto; /* Specified for xSPI */ 81 void *buffer; 82 u32 xferlen; 83 u32 smcr; 84 u32 smadr; 85 u32 command; /* DRCMR or SMCMR */ 86 u32 option; /* DROPR or SMOPR */ 87 u32 enable; /* DRENR or SMENR */ 88 u32 dummy; /* DRDMCR or SMDMCR */ 89 u32 ddr; /* DRDRENR or SMDRENR */ 90 }; 91 92 /* 93 * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with 94 * proper width. Requires rpcif_priv.xfer_size to be correctly set before! 95 */ 96 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val) 97 { 98 struct rpcif_priv *rpc = context; 99 100 switch (reg) { 101 case RPCIF_SMRDR0: 102 case RPCIF_SMWDR0: 103 switch (rpc->xfer_size) { 104 case 1: 105 *val = readb(rpc->base + reg); 106 return 0; 107 108 case 2: 109 *val = readw(rpc->base + reg); 110 return 0; 111 112 case 4: 113 case 8: 114 *val = readl(rpc->base + reg); 115 return 0; 116 117 default: 118 return -EILSEQ; 119 } 120 121 case RPCIF_SMRDR1: 122 case RPCIF_SMWDR1: 123 if (rpc->xfer_size != 8) 124 return -EILSEQ; 125 break; 126 } 127 128 *val = readl(rpc->base + reg); 129 return 0; 130 } 131 132 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val) 133 { 134 struct rpcif_priv *rpc = context; 135 136 switch (reg) { 137 case RPCIF_SMWDR0: 138 switch (rpc->xfer_size) { 139 case 1: 140 writeb(val, rpc->base + reg); 141 return 0; 142 143 case 2: 144 writew(val, rpc->base + reg); 145 return 0; 146 147 case 4: 148 case 8: 149 writel(val, rpc->base + reg); 150 return 0; 151 152 default: 153 return -EILSEQ; 154 } 155 156 case RPCIF_SMWDR1: 157 if (rpc->xfer_size != 8) 158 return -EILSEQ; 159 break; 160 161 case RPCIF_SMRDR0: 162 case RPCIF_SMRDR1: 163 return -EPERM; 164 } 165 166 writel(val, rpc->base + reg); 167 return 0; 168 } 169 170 static const struct regmap_config rpcif_regmap_config = { 171 .reg_bits = 32, 172 .val_bits = 32, 173 .reg_stride = 4, 174 .reg_read = rpcif_reg_read, 175 .reg_write = rpcif_reg_write, 176 .fast_io = true, 177 .max_register = RPCIF_PHYINT, 178 .volatile_table = &rpcif_volatile_table, 179 }; 180 181 static int xspi_reg_read(void *context, unsigned int reg, unsigned int *val) 182 { 183 struct rpcif_priv *xspi = context; 184 185 *val = readl(xspi->base + reg); 186 return 0; 187 } 188 189 static int xspi_reg_write(void *context, unsigned int reg, unsigned int val) 190 { 191 struct rpcif_priv *xspi = context; 192 193 writel(val, xspi->base + reg); 194 return 0; 195 } 196 197 static const struct regmap_config xspi_regmap_config = { 198 .reg_bits = 32, 199 .val_bits = 32, 200 .reg_stride = 4, 201 .reg_read = xspi_reg_read, 202 .reg_write = xspi_reg_write, 203 .fast_io = true, 204 .max_register = XSPI_INTE, 205 .volatile_table = &xspi_volatile_table, 206 }; 207 208 int rpcif_sw_init(struct rpcif *rpcif, struct device *dev) 209 { 210 struct rpcif_priv *rpc = dev_get_drvdata(dev); 211 212 rpcif->dev = dev; 213 rpcif->dirmap = rpc->dirmap; 214 rpcif->size = rpc->size; 215 rpcif->xspi = rpc->info->type == XSPI_RZ_G3E; 216 return 0; 217 } 218 EXPORT_SYMBOL(rpcif_sw_init); 219 220 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc) 221 { 222 regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000); 223 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000); 224 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 225 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022); 226 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080); 227 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024); 228 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3), 229 RPCIF_PHYCNT_CKSEL(3)); 230 regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030); 231 regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032); 232 } 233 234 static int rpcif_hw_init_impl(struct rpcif_priv *rpc, bool hyperflash) 235 { 236 u32 dummy; 237 int ret; 238 239 if (rpc->info->type == RPCIF_RZ_G2L) { 240 ret = reset_control_reset(rpc->rstc); 241 if (ret) 242 return ret; 243 usleep_range(200, 300); 244 rpcif_rzg2l_timing_adjust_sdr(rpc); 245 } 246 247 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK, 248 RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0)); 249 250 /* DMA Transfer is not supported */ 251 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_HS, 0); 252 253 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 254 /* create mask with all affected bits set */ 255 RPCIF_PHYCNT_STRTIM(BIT(fls(rpc->info->strtim)) - 1), 256 RPCIF_PHYCNT_STRTIM(rpc->info->strtim)); 257 258 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3), 259 RPCIF_PHYOFFSET1_DDRTMG(3)); 260 regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7), 261 RPCIF_PHYOFFSET2_OCTTMG(4)); 262 263 if (hyperflash) 264 regmap_update_bits(rpc->regmap, RPCIF_PHYINT, 265 RPCIF_PHYINT_WPVAL, 0); 266 267 if (rpc->info->type == RPCIF_RZ_G2L) 268 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 269 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | 270 RPCIF_CMNCR_BSZ(3), 271 RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) | 272 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 273 else 274 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 275 RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3), 276 RPCIF_CMNCR_MOIIO(3) | 277 RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); 278 279 /* Set RCF after BSZ update */ 280 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 281 /* Dummy read according to spec */ 282 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 283 regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) | 284 RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7)); 285 286 rpc->bus_size = hyperflash ? 2 : 1; 287 288 return 0; 289 } 290 291 static int xspi_hw_init_impl(struct rpcif_priv *xspi, bool hyperflash) 292 { 293 int ret; 294 295 ret = reset_control_reset(xspi->rstc); 296 if (ret) 297 return ret; 298 299 regmap_write(xspi->regmap, XSPI_WRAPCFG, 0x0); 300 301 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, 302 XSPI_LIOCFG_PRTMD(0x3ff) | XSPI_LIOCFG_CSMIN(0xf) | 303 XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX, 304 XSPI_LIOCFG_PRTMD(0) | XSPI_LIOCFG_CSMIN(0) | 305 XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX); 306 307 regmap_update_bits(xspi->regmap, XSPI_CCCTL0CS0, XSPI_CCCTL0_CAEN, 0); 308 309 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 310 XSPI_CDCTL0_TRREQ | XSPI_CDCTL0_CSSEL, 0); 311 312 regmap_update_bits(xspi->regmap, XSPI_INTE, XSPI_INTE_CMDCMPE, 313 XSPI_INTE_CMDCMPE); 314 315 regmap_update_bits(xspi->regmap, XSPI_BMCTL0, 316 XSPI_BMCTL0_CS0ACC(0xff), XSPI_BMCTL0_CS0ACC(0x03)); 317 318 regmap_update_bits(xspi->regmap, XSPI_BMCFG, 319 XSPI_BMCFG_WRMD | XSPI_BMCFG_MWRCOMB | 320 XSPI_BMCFG_MWRSIZE(0xff) | XSPI_BMCFG_PREEN, 321 0 | XSPI_BMCFG_MWRCOMB | XSPI_BMCFG_MWRSIZE(0x0f) | 322 XSPI_BMCFG_PREEN); 323 return 0; 324 } 325 326 int rpcif_hw_init(struct device *dev, bool hyperflash) 327 { 328 struct rpcif_priv *rpc = dev_get_drvdata(dev); 329 int ret; 330 331 ret = pm_runtime_resume_and_get(dev); 332 if (ret) 333 return ret; 334 335 ret = rpc->info->impl->hw_init(rpc, hyperflash); 336 337 pm_runtime_put(dev); 338 339 return ret; 340 } 341 EXPORT_SYMBOL(rpcif_hw_init); 342 343 static int wait_msg_xfer_end(struct rpcif_priv *rpc) 344 { 345 u32 sts; 346 347 return regmap_read_poll_timeout(rpc->regmap, rpc->info->impl->status_reg, 348 sts, sts & rpc->info->impl->status_mask, 349 0, USEC_PER_SEC); 350 } 351 352 static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes) 353 { 354 if (rpc->bus_size == 2) 355 nbytes /= 2; 356 nbytes = clamp(nbytes, 1U, 4U); 357 return GENMASK(3, 4 - nbytes); 358 } 359 360 static u8 rpcif_bit_size(u8 buswidth) 361 { 362 return buswidth > 4 ? 2 : ilog2(buswidth); 363 } 364 365 static void rpcif_prepare_impl(struct rpcif_priv *rpc, const struct rpcif_op *op, 366 u64 *offs, size_t *len) 367 { 368 rpc->smcr = 0; 369 rpc->smadr = 0; 370 rpc->enable = 0; 371 rpc->command = 0; 372 rpc->option = 0; 373 rpc->dummy = 0; 374 rpc->ddr = 0; 375 rpc->xferlen = 0; 376 377 if (op->cmd.buswidth) { 378 rpc->enable = RPCIF_SMENR_CDE | 379 RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth)); 380 rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode); 381 if (op->cmd.ddr) 382 rpc->ddr = RPCIF_SMDRENR_HYPE(0x5); 383 } 384 if (op->ocmd.buswidth) { 385 rpc->enable |= RPCIF_SMENR_OCDE | 386 RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth)); 387 rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode); 388 } 389 390 if (op->addr.buswidth) { 391 rpc->enable |= 392 RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth)); 393 if (op->addr.nbytes == 4) 394 rpc->enable |= RPCIF_SMENR_ADE(0xF); 395 else 396 rpc->enable |= RPCIF_SMENR_ADE(GENMASK( 397 2, 3 - op->addr.nbytes)); 398 if (op->addr.ddr) 399 rpc->ddr |= RPCIF_SMDRENR_ADDRE; 400 401 if (offs && len) 402 rpc->smadr = *offs; 403 else 404 rpc->smadr = op->addr.val; 405 } 406 407 if (op->dummy.buswidth) { 408 rpc->enable |= RPCIF_SMENR_DME; 409 rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles); 410 } 411 412 if (op->option.buswidth) { 413 rpc->enable |= RPCIF_SMENR_OPDE( 414 rpcif_bits_set(rpc, op->option.nbytes)) | 415 RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth)); 416 if (op->option.ddr) 417 rpc->ddr |= RPCIF_SMDRENR_OPDRE; 418 rpc->option = op->option.val; 419 } 420 421 rpc->dir = op->data.dir; 422 if (op->data.buswidth) { 423 u32 nbytes; 424 425 rpc->buffer = op->data.buf.in; 426 switch (op->data.dir) { 427 case RPCIF_DATA_IN: 428 rpc->smcr = RPCIF_SMCR_SPIRE; 429 break; 430 case RPCIF_DATA_OUT: 431 rpc->smcr = RPCIF_SMCR_SPIWE; 432 break; 433 default: 434 break; 435 } 436 if (op->data.ddr) 437 rpc->ddr |= RPCIF_SMDRENR_SPIDRE; 438 439 if (offs && len) 440 nbytes = *len; 441 else 442 nbytes = op->data.nbytes; 443 rpc->xferlen = nbytes; 444 445 rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth)); 446 } 447 } 448 449 static void xspi_prepare_impl(struct rpcif_priv *xspi, const struct rpcif_op *op, 450 u64 *offs, size_t *len) 451 { 452 xspi->smadr = 0; 453 xspi->addr_nbytes = 0; 454 xspi->command = 0; 455 xspi->option = 0; 456 xspi->dummy = 0; 457 xspi->xferlen = 0; 458 xspi->proto = 0; 459 460 if (op->cmd.buswidth) 461 xspi->command = op->cmd.opcode; 462 463 if (op->ocmd.buswidth) 464 xspi->command = (xspi->command << 8) | op->ocmd.opcode; 465 466 if (op->addr.buswidth) { 467 xspi->addr_nbytes = op->addr.nbytes; 468 if (offs && len) 469 xspi->smadr = *offs; 470 else 471 xspi->smadr = op->addr.val; 472 } 473 474 if (op->dummy.buswidth) 475 xspi->dummy = op->dummy.ncycles; 476 477 xspi->dir = op->data.dir; 478 if (op->data.buswidth) { 479 u32 nbytes; 480 481 xspi->buffer = op->data.buf.in; 482 483 if (offs && len) 484 nbytes = *len; 485 else 486 nbytes = op->data.nbytes; 487 xspi->xferlen = nbytes; 488 } 489 490 if (op->cmd.buswidth == 1) { 491 if (op->addr.buswidth == 2 || op->data.buswidth == 2) 492 xspi->proto = PROTO_1S_2S_2S; 493 else if (op->addr.buswidth == 4 || op->data.buswidth == 4) 494 xspi->proto = PROTO_1S_4S_4S; 495 } else if (op->cmd.buswidth == 2 && 496 (op->addr.buswidth == 2 || op->data.buswidth == 2)) { 497 xspi->proto = PROTO_2S_2S_2S; 498 } else if (op->cmd.buswidth == 4 && 499 (op->addr.buswidth == 4 || op->data.buswidth == 4)) { 500 xspi->proto = PROTO_4S_4S_4S; 501 } 502 } 503 504 void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs, 505 size_t *len) 506 { 507 struct rpcif_priv *rpc = dev_get_drvdata(dev); 508 509 rpc->info->impl->prepare(rpc, op, offs, len); 510 } 511 EXPORT_SYMBOL(rpcif_prepare); 512 513 static int rpcif_manual_xfer_impl(struct rpcif_priv *rpc) 514 { 515 u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4; 516 int ret = 0; 517 518 regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, 519 RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL); 520 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 521 RPCIF_CMNCR_MD, RPCIF_CMNCR_MD); 522 regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command); 523 regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option); 524 regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy); 525 regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr); 526 regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr); 527 smenr = rpc->enable; 528 529 switch (rpc->dir) { 530 case RPCIF_DATA_OUT: 531 while (pos < rpc->xferlen) { 532 u32 bytes_left = rpc->xferlen - pos; 533 u32 nbytes, data[2], *p = data; 534 535 smcr = rpc->smcr | RPCIF_SMCR_SPIE; 536 537 /* nbytes may only be 1, 2, 4, or 8 */ 538 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 539 if (bytes_left > nbytes) 540 smcr |= RPCIF_SMCR_SSLKP; 541 542 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 543 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 544 rpc->xfer_size = nbytes; 545 546 memcpy(data, rpc->buffer + pos, nbytes); 547 if (nbytes == 8) 548 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++); 549 regmap_write(rpc->regmap, RPCIF_SMWDR0, *p); 550 551 regmap_write(rpc->regmap, RPCIF_SMCR, smcr); 552 ret = wait_msg_xfer_end(rpc); 553 if (ret) 554 goto err_out; 555 556 pos += nbytes; 557 smenr = rpc->enable & 558 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF); 559 } 560 break; 561 case RPCIF_DATA_IN: 562 /* 563 * RPC-IF spoils the data for the commands without an address 564 * phase (like RDID) in the manual mode, so we'll have to work 565 * around this issue by using the external address space read 566 * mode instead. 567 */ 568 if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) { 569 u32 dummy; 570 571 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, 572 RPCIF_CMNCR_MD, 0); 573 regmap_write(rpc->regmap, RPCIF_DRCR, 574 RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE); 575 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 576 regmap_write(rpc->regmap, RPCIF_DREAR, 577 RPCIF_DREAR_EAC(1)); 578 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 579 regmap_write(rpc->regmap, RPCIF_DRENR, 580 smenr & ~RPCIF_SMENR_SPIDE(0xF)); 581 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 582 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 583 memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen); 584 regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF); 585 /* Dummy read according to spec */ 586 regmap_read(rpc->regmap, RPCIF_DRCR, &dummy); 587 break; 588 } 589 while (pos < rpc->xferlen) { 590 u32 bytes_left = rpc->xferlen - pos; 591 u32 nbytes, data[2], *p = data; 592 593 /* nbytes may only be 1, 2, 4, or 8 */ 594 nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left)); 595 596 regmap_write(rpc->regmap, RPCIF_SMADR, 597 rpc->smadr + pos); 598 smenr &= ~RPCIF_SMENR_SPIDE(0xF); 599 smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes)); 600 regmap_write(rpc->regmap, RPCIF_SMENR, smenr); 601 regmap_write(rpc->regmap, RPCIF_SMCR, 602 rpc->smcr | RPCIF_SMCR_SPIE); 603 rpc->xfer_size = nbytes; 604 ret = wait_msg_xfer_end(rpc); 605 if (ret) 606 goto err_out; 607 608 if (nbytes == 8) 609 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++); 610 regmap_read(rpc->regmap, RPCIF_SMRDR0, p); 611 memcpy(rpc->buffer + pos, data, nbytes); 612 613 pos += nbytes; 614 } 615 break; 616 default: 617 regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable); 618 regmap_write(rpc->regmap, RPCIF_SMCR, 619 rpc->smcr | RPCIF_SMCR_SPIE); 620 ret = wait_msg_xfer_end(rpc); 621 if (ret) 622 goto err_out; 623 } 624 625 return ret; 626 627 err_out: 628 if (reset_control_reset(rpc->rstc)) 629 dev_err(rpc->dev, "Failed to reset HW\n"); 630 rpcif_hw_init_impl(rpc, rpc->bus_size == 2); 631 return ret; 632 } 633 634 static int xspi_manual_xfer_impl(struct rpcif_priv *xspi) 635 { 636 u32 pos = 0, max = 8; 637 int ret = 0; 638 639 /* Clear transaction number and request */ 640 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 641 XSPI_CDCTL0_TRNUM(0x3) | XSPI_CDCTL0_TRREQ, 642 XSPI_CDCTL0_TRNUM(0)); 643 644 regmap_write(xspi->regmap, XSPI_CDTBUF0, 645 XSPI_CDTBUF_CMDSIZE(0x1) | XSPI_CDTBUF_CMD_FIELD(xspi->command) | 646 XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes)); 647 648 regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr); 649 650 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 651 XSPI_LIOCFG_PRTMD(xspi->proto)); 652 653 switch (xspi->dir) { 654 case RPCIF_DATA_OUT: 655 while (pos < xspi->xferlen) { 656 u32 bytes_left = xspi->xferlen - pos; 657 u32 nbytes, data[2], *p = data; 658 659 nbytes = bytes_left >= max ? max : bytes_left; 660 661 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 662 XSPI_CDTBUF_TRTYPE | XSPI_CDTBUF_DATASIZE(0xf) | 663 XSPI_CDTBUF_ADDSIZE(0x7), 664 XSPI_CDTBUF_TRTYPE | XSPI_CDTBUF_DATASIZE(nbytes) | 665 XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes)); 666 667 memcpy(data, xspi->buffer + pos, nbytes); 668 669 if (nbytes > 4) { 670 regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p++); 671 regmap_write(xspi->regmap, XSPI_CDD1BUF0, *p); 672 } else { 673 regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p); 674 } 675 676 regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr + pos); 677 678 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 679 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 680 681 ret = wait_msg_xfer_end(xspi); 682 if (ret) 683 goto err_out; 684 685 regmap_update_bits(xspi->regmap, XSPI_INTC, 686 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 687 688 pos += nbytes; 689 } 690 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRREQ, 0); 691 break; 692 case RPCIF_DATA_IN: 693 while (pos < xspi->xferlen) { 694 u32 bytes_left = xspi->xferlen - pos; 695 u32 nbytes, data[2], *p = data; 696 u32 cdtbuf0_mask, cdtbuf0_val; 697 698 /* nbytes can be up to 8 bytes */ 699 nbytes = bytes_left >= max ? max : bytes_left; 700 701 /* clear TRTYPE */ 702 cdtbuf0_mask = XSPI_CDTBUF_TRTYPE; 703 cdtbuf0_val = 0; 704 705 /* program DATASIZE */ 706 cdtbuf0_mask |= XSPI_CDTBUF_DATASIZE(0xf); 707 cdtbuf0_val |= XSPI_CDTBUF_DATASIZE(nbytes); 708 709 /* program ADDSIZE */ 710 cdtbuf0_mask |= XSPI_CDTBUF_ADDSIZE(0x7); 711 cdtbuf0_val |= XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes); 712 713 /* program LATE */ 714 cdtbuf0_mask |= XSPI_CDTBUF_LATE(0x1f); 715 cdtbuf0_val |= XSPI_CDTBUF_LATE(xspi->dummy); 716 717 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, cdtbuf0_mask, cdtbuf0_val); 718 719 if (xspi->addr_nbytes) 720 regmap_write(xspi->regmap, XSPI_CDABUF0, 721 xspi->smadr + pos); 722 723 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 724 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 725 726 ret = wait_msg_xfer_end(xspi); 727 if (ret) 728 goto err_out; 729 730 if (nbytes > 4) { 731 regmap_read(xspi->regmap, XSPI_CDD0BUF0, p++); 732 regmap_read(xspi->regmap, XSPI_CDD1BUF0, p); 733 } else { 734 regmap_read(xspi->regmap, XSPI_CDD0BUF0, p); 735 } 736 737 memcpy(xspi->buffer + pos, data, nbytes); 738 739 regmap_update_bits(xspi->regmap, XSPI_INTC, 740 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 741 742 pos += nbytes; 743 } 744 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 745 XSPI_CDCTL0_TRREQ, 0); 746 break; 747 default: 748 regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, 749 XSPI_CDTBUF_TRTYPE, XSPI_CDTBUF_TRTYPE); 750 regmap_update_bits(xspi->regmap, XSPI_CDCTL0, 751 XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ); 752 753 ret = wait_msg_xfer_end(xspi); 754 if (ret) 755 goto err_out; 756 757 regmap_update_bits(xspi->regmap, XSPI_INTC, 758 XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC); 759 } 760 761 return ret; 762 763 err_out: 764 xspi_hw_init_impl(xspi, false); 765 return ret; 766 } 767 768 int rpcif_manual_xfer(struct device *dev) 769 { 770 struct rpcif_priv *rpc = dev_get_drvdata(dev); 771 int ret; 772 773 ret = pm_runtime_resume_and_get(dev); 774 if (ret) 775 return ret; 776 777 ret = rpc->info->impl->manual_xfer(rpc); 778 779 pm_runtime_put_autosuspend(dev); 780 781 return ret; 782 } 783 EXPORT_SYMBOL(rpcif_manual_xfer); 784 785 static void memcpy_fromio_readw(void *to, 786 const void __iomem *from, 787 size_t count) 788 { 789 const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4; 790 u8 buf[2]; 791 792 if (count && ((unsigned long)from & 1)) { 793 *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1)); 794 *(u8 *)to = buf[1]; 795 from++; 796 to++; 797 count--; 798 } 799 while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) { 800 *(u16 *)to = __raw_readw(from); 801 from += 2; 802 to += 2; 803 count -= 2; 804 } 805 while (count >= maxw) { 806 #ifdef CONFIG_64BIT 807 *(u64 *)to = __raw_readq(from); 808 #else 809 *(u32 *)to = __raw_readl(from); 810 #endif 811 from += maxw; 812 to += maxw; 813 count -= maxw; 814 } 815 while (count >= 2) { 816 *(u16 *)to = __raw_readw(from); 817 from += 2; 818 to += 2; 819 count -= 2; 820 } 821 if (count) { 822 *(u16 *)buf = __raw_readw(from); 823 *(u8 *)to = buf[0]; 824 } 825 } 826 827 static size_t rpcif_dirmap_read_impl(struct rpcif_priv *rpc, u64 offs, 828 size_t len, void *buf) 829 { 830 loff_t from = offs & (rpc->size - 1); 831 size_t size = rpc->size - from; 832 833 if (len > size) 834 len = size; 835 836 regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0); 837 regmap_write(rpc->regmap, RPCIF_DRCR, 0); 838 regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command); 839 regmap_write(rpc->regmap, RPCIF_DREAR, 840 RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1)); 841 regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option); 842 regmap_write(rpc->regmap, RPCIF_DRENR, 843 rpc->enable & ~RPCIF_SMENR_SPIDE(0xF)); 844 regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy); 845 regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr); 846 847 if (rpc->bus_size == 2) 848 memcpy_fromio_readw(buf, rpc->dirmap + from, len); 849 else 850 memcpy_fromio(buf, rpc->dirmap + from, len); 851 852 return len; 853 } 854 855 static size_t xspi_dirmap_read_impl(struct rpcif_priv *xspi, u64 offs, 856 size_t len, void *buf) 857 { 858 loff_t from = offs & (xspi->size - 1); 859 size_t size = xspi->size - from; 860 u8 addsize = xspi->addr_nbytes - 1; 861 862 if (len > size) 863 len = size; 864 865 regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0, 866 XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3), 867 XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize)); 868 869 regmap_update_bits(xspi->regmap, XSPI_CMCFG1CS0, 870 XSPI_CMCFG1_RDCMD(0xffff) | XSPI_CMCFG1_RDLATE(0x1f), 871 XSPI_CMCFG1_RDCMD_UPPER_BYTE(xspi->command) | 872 XSPI_CMCFG1_RDLATE(xspi->dummy)); 873 874 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 875 XSPI_LIOCFG_PRTMD(xspi->proto)); 876 877 memcpy_fromio(buf, xspi->dirmap + from, len); 878 879 return len; 880 } 881 882 ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf) 883 { 884 struct rpcif_priv *rpc = dev_get_drvdata(dev); 885 size_t read; 886 int ret; 887 888 ret = pm_runtime_resume_and_get(dev); 889 if (ret) 890 return ret; 891 892 read = rpc->info->impl->dirmap_read(rpc, offs, len, buf); 893 894 pm_runtime_put_autosuspend(dev); 895 896 return read; 897 } 898 EXPORT_SYMBOL(rpcif_dirmap_read); 899 900 /** 901 * xspi_dirmap_write - Write data to xspi memory. 902 * @dev: xspi device 903 * @offs: offset 904 * @len: Number of bytes to be written. 905 * @buf: Buffer holding write data. 906 * 907 * This function writes data into xspi memory. 908 * 909 * Returns number of bytes written on success, else negative errno. 910 */ 911 ssize_t xspi_dirmap_write(struct device *dev, u64 offs, size_t len, const void *buf) 912 { 913 struct rpcif_priv *xspi = dev_get_drvdata(dev); 914 loff_t from = offs & (xspi->size - 1); 915 u8 addsize = xspi->addr_nbytes - 1; 916 size_t size = xspi->size - from; 917 ssize_t writebytes; 918 int ret; 919 920 ret = pm_runtime_resume_and_get(dev); 921 if (ret) 922 return ret; 923 924 if (len > size) 925 len = size; 926 927 if (len > MWRSIZE_MAX) 928 writebytes = MWRSIZE_MAX; 929 else 930 writebytes = len; 931 932 regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0, 933 XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3), 934 XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize)); 935 936 regmap_update_bits(xspi->regmap, XSPI_CMCFG2CS0, 937 XSPI_CMCFG2_WRCMD_UPPER(0xff) | XSPI_CMCFG2_WRLATE(0x1f), 938 XSPI_CMCFG2_WRCMD_UPPER(xspi->command) | 939 XSPI_CMCFG2_WRLATE(xspi->dummy)); 940 941 regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff), 942 XSPI_LIOCFG_PRTMD(xspi->proto)); 943 944 memcpy_toio(xspi->dirmap + from, buf, writebytes); 945 946 /* Request to push the pending data */ 947 if (writebytes < MWRSIZE_MAX) 948 regmap_update_bits(xspi->regmap, XSPI_BMCTL1, 949 XSPI_BMCTL1_MWRPUSH, XSPI_BMCTL1_MWRPUSH); 950 951 pm_runtime_put_autosuspend(dev); 952 953 return writebytes; 954 } 955 EXPORT_SYMBOL_GPL(xspi_dirmap_write); 956 957 static int rpcif_probe(struct platform_device *pdev) 958 { 959 struct device *dev = &pdev->dev; 960 struct platform_device *vdev; 961 struct device_node *flash; 962 struct rpcif_priv *rpc; 963 struct resource *res; 964 const char *name; 965 int ret; 966 967 flash = of_get_next_child(dev->of_node, NULL); 968 if (!flash) { 969 dev_warn(dev, "no flash node found\n"); 970 return -ENODEV; 971 } 972 973 if (of_device_is_compatible(flash, "jedec,spi-nor")) { 974 name = "rpc-if-spi"; 975 } else if (of_device_is_compatible(flash, "cfi-flash")) { 976 name = "rpc-if-hyperflash"; 977 } else { 978 of_node_put(flash); 979 dev_warn(dev, "unknown flash type\n"); 980 return -ENODEV; 981 } 982 of_node_put(flash); 983 984 rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL); 985 if (!rpc) 986 return -ENOMEM; 987 988 rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs"); 989 if (IS_ERR(rpc->base)) 990 return PTR_ERR(rpc->base); 991 rpc->info = of_device_get_match_data(dev); 992 rpc->regmap = devm_regmap_init(dev, NULL, rpc, rpc->info->regmap_config); 993 if (IS_ERR(rpc->regmap)) 994 return dev_err_probe(dev, PTR_ERR(rpc->regmap), 995 "failed to init regmap for rpcif\n"); 996 997 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); 998 rpc->dirmap = devm_ioremap_resource(dev, res); 999 if (IS_ERR(rpc->dirmap)) 1000 return PTR_ERR(rpc->dirmap); 1001 1002 rpc->size = resource_size(res); 1003 rpc->rstc = devm_reset_control_array_get_exclusive(dev); 1004 if (IS_ERR(rpc->rstc)) 1005 return PTR_ERR(rpc->rstc); 1006 1007 /* 1008 * The enabling/disabling of spi/spix2 clocks at runtime leading to 1009 * flash write failure. So, enable these clocks during probe() and 1010 * disable it in remove(). 1011 */ 1012 rpc->spix2_clk = devm_clk_get_optional_enabled(dev, "spix2"); 1013 if (IS_ERR(rpc->spix2_clk)) 1014 return dev_err_probe(dev, PTR_ERR(rpc->spix2_clk), 1015 "cannot get enabled spix2 clk\n"); 1016 1017 rpc->spi_clk = devm_clk_get_optional_enabled(dev, "spi"); 1018 if (IS_ERR(rpc->spi_clk)) 1019 return dev_err_probe(dev, PTR_ERR(rpc->spi_clk), 1020 "cannot get enabled spi clk\n"); 1021 1022 vdev = platform_device_alloc(name, PLATFORM_DEVID_AUTO); 1023 if (!vdev) 1024 return -ENOMEM; 1025 vdev->dev.parent = dev; 1026 1027 rpc->dev = dev; 1028 rpc->vdev = vdev; 1029 platform_set_drvdata(pdev, rpc); 1030 1031 ret = platform_device_add(vdev); 1032 if (ret) { 1033 platform_device_put(vdev); 1034 return ret; 1035 } 1036 1037 return 0; 1038 } 1039 1040 static void rpcif_remove(struct platform_device *pdev) 1041 { 1042 struct rpcif_priv *rpc = platform_get_drvdata(pdev); 1043 1044 platform_device_unregister(rpc->vdev); 1045 } 1046 1047 static int rpcif_suspend(struct device *dev) 1048 { 1049 struct rpcif_priv *rpc = dev_get_drvdata(dev); 1050 1051 clk_disable_unprepare(rpc->spi_clk); 1052 clk_disable_unprepare(rpc->spix2_clk); 1053 1054 return 0; 1055 } 1056 1057 static int rpcif_resume(struct device *dev) 1058 { 1059 struct rpcif_priv *rpc = dev_get_drvdata(dev); 1060 int ret; 1061 1062 ret = clk_prepare_enable(rpc->spix2_clk); 1063 if (ret) { 1064 dev_err(dev, "failed to enable spix2 clock: %pe\n", ERR_PTR(ret)); 1065 return ret; 1066 } 1067 1068 ret = clk_prepare_enable(rpc->spi_clk); 1069 if (ret) { 1070 clk_disable_unprepare(rpc->spix2_clk); 1071 dev_err(dev, "failed to enable spi clock: %pe\n", ERR_PTR(ret)); 1072 return ret; 1073 } 1074 1075 return 0; 1076 } 1077 1078 static const struct rpcif_impl rpcif_impl = { 1079 .hw_init = rpcif_hw_init_impl, 1080 .prepare = rpcif_prepare_impl, 1081 .manual_xfer = rpcif_manual_xfer_impl, 1082 .dirmap_read = rpcif_dirmap_read_impl, 1083 .status_reg = RPCIF_CMNSR, 1084 .status_mask = RPCIF_CMNSR_TEND, 1085 }; 1086 1087 static const struct rpcif_impl xspi_impl = { 1088 .hw_init = xspi_hw_init_impl, 1089 .prepare = xspi_prepare_impl, 1090 .manual_xfer = xspi_manual_xfer_impl, 1091 .dirmap_read = xspi_dirmap_read_impl, 1092 .status_reg = XSPI_INTS, 1093 .status_mask = XSPI_INTS_CMDCMP, 1094 }; 1095 1096 static const struct rpcif_info rpcif_info_r8a7796 = { 1097 .regmap_config = &rpcif_regmap_config, 1098 .impl = &rpcif_impl, 1099 .type = RPCIF_RCAR_GEN3, 1100 .strtim = 6, 1101 }; 1102 1103 static const struct rpcif_info rpcif_info_gen3 = { 1104 .regmap_config = &rpcif_regmap_config, 1105 .impl = &rpcif_impl, 1106 .type = RPCIF_RCAR_GEN3, 1107 .strtim = 7, 1108 }; 1109 1110 static const struct rpcif_info rpcif_info_rz_g2l = { 1111 .regmap_config = &rpcif_regmap_config, 1112 .impl = &rpcif_impl, 1113 .type = RPCIF_RZ_G2L, 1114 .strtim = 7, 1115 }; 1116 1117 static const struct rpcif_info rpcif_info_gen4 = { 1118 .regmap_config = &rpcif_regmap_config, 1119 .impl = &rpcif_impl, 1120 .type = RPCIF_RCAR_GEN4, 1121 .strtim = 15, 1122 }; 1123 1124 static const struct rpcif_info xspi_info_r9a09g047 = { 1125 .regmap_config = &xspi_regmap_config, 1126 .impl = &xspi_impl, 1127 .type = XSPI_RZ_G3E, 1128 }; 1129 1130 static const struct of_device_id rpcif_of_match[] = { 1131 { .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 }, 1132 { .compatible = "renesas,r9a09g047-xspi", .data = &xspi_info_r9a09g047 }, 1133 { .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 }, 1134 { .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 }, 1135 { .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l }, 1136 {}, 1137 }; 1138 MODULE_DEVICE_TABLE(of, rpcif_of_match); 1139 1140 static DEFINE_SIMPLE_DEV_PM_OPS(rpcif_pm_ops, rpcif_suspend, rpcif_resume); 1141 1142 static struct platform_driver rpcif_driver = { 1143 .probe = rpcif_probe, 1144 .remove = rpcif_remove, 1145 .driver = { 1146 .name = "rpc-if", 1147 .of_match_table = rpcif_of_match, 1148 .pm = pm_sleep_ptr(&rpcif_pm_ops), 1149 }, 1150 }; 1151 module_platform_driver(rpcif_driver); 1152 1153 MODULE_DESCRIPTION("Renesas RPC-IF core driver"); 1154 MODULE_LICENSE("GPL v2"); 1155