1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPMC support functions 4 * 5 * Copyright (C) 2005-2006 Nokia Corporation 6 * 7 * Author: Juha Yrjola 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 */ 12 #include <linux/irq.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/ioport.h> 18 #include <linux/spinlock.h> 19 #include <linux/io.h> 20 #include <linux/gpio/driver.h> 21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */ 22 #include <linux/gpio/machine.h> 23 #include <linux/interrupt.h> 24 #include <linux/irqdomain.h> 25 #include <linux/platform_device.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_device.h> 29 #include <linux/of_platform.h> 30 #include <linux/omap-gpmc.h> 31 #include <linux/pm_runtime.h> 32 33 #include <linux/platform_data/mtd-nand-omap2.h> 34 35 #include <asm/mach-types.h> 36 37 #define DEVICE_NAME "omap-gpmc" 38 39 /* GPMC register offsets */ 40 #define GPMC_REVISION 0x00 41 #define GPMC_SYSCONFIG 0x10 42 #define GPMC_SYSSTATUS 0x14 43 #define GPMC_IRQSTATUS 0x18 44 #define GPMC_IRQENABLE 0x1c 45 #define GPMC_TIMEOUT_CONTROL 0x40 46 #define GPMC_ERR_ADDRESS 0x44 47 #define GPMC_ERR_TYPE 0x48 48 #define GPMC_CONFIG 0x50 49 #define GPMC_STATUS 0x54 50 #define GPMC_PREFETCH_CONFIG1 0x1e0 51 #define GPMC_PREFETCH_CONFIG2 0x1e4 52 #define GPMC_PREFETCH_CONTROL 0x1ec 53 #define GPMC_PREFETCH_STATUS 0x1f0 54 #define GPMC_ECC_CONFIG 0x1f4 55 #define GPMC_ECC_CONTROL 0x1f8 56 #define GPMC_ECC_SIZE_CONFIG 0x1fc 57 #define GPMC_ECC1_RESULT 0x200 58 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 59 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ 60 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ 61 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ 62 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ 63 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ 64 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ 65 66 /* GPMC ECC control settings */ 67 #define GPMC_ECC_CTRL_ECCCLEAR 0x100 68 #define GPMC_ECC_CTRL_ECCDISABLE 0x000 69 #define GPMC_ECC_CTRL_ECCREG1 0x001 70 #define GPMC_ECC_CTRL_ECCREG2 0x002 71 #define GPMC_ECC_CTRL_ECCREG3 0x003 72 #define GPMC_ECC_CTRL_ECCREG4 0x004 73 #define GPMC_ECC_CTRL_ECCREG5 0x005 74 #define GPMC_ECC_CTRL_ECCREG6 0x006 75 #define GPMC_ECC_CTRL_ECCREG7 0x007 76 #define GPMC_ECC_CTRL_ECCREG8 0x008 77 #define GPMC_ECC_CTRL_ECCREG9 0x009 78 79 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) 80 81 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) 82 83 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 84 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 85 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 86 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) 87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) 88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) 89 90 #define GPMC_CS0_OFFSET 0x60 91 #define GPMC_CS_SIZE 0x30 92 #define GPMC_BCH_SIZE 0x10 93 94 /* 95 * The first 1MB of GPMC address space is typically mapped to 96 * the internal ROM. Never allocate the first page, to 97 * facilitate bug detection; even if we didn't boot from ROM. 98 * As GPMC minimum partition size is 16MB we can only start from 99 * there. 100 */ 101 #define GPMC_MEM_START 0x1000000 102 #define GPMC_MEM_END 0x3FFFFFFF 103 104 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 105 #define GPMC_SECTION_SHIFT 28 /* 128 MB */ 106 107 #define CS_NUM_SHIFT 24 108 #define ENABLE_PREFETCH (0x1 << 7) 109 #define DMA_MPU_MODE 2 110 111 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) 112 #define GPMC_REVISION_MINOR(l) (l & 0xf) 113 114 #define GPMC_HAS_WR_ACCESS 0x1 115 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 116 #define GPMC_HAS_MUX_AAD 0x4 117 118 #define GPMC_NR_WAITPINS 4 119 120 #define GPMC_CS_CONFIG1 0x00 121 #define GPMC_CS_CONFIG2 0x04 122 #define GPMC_CS_CONFIG3 0x08 123 #define GPMC_CS_CONFIG4 0x0c 124 #define GPMC_CS_CONFIG5 0x10 125 #define GPMC_CS_CONFIG6 0x14 126 #define GPMC_CS_CONFIG7 0x18 127 #define GPMC_CS_NAND_COMMAND 0x1c 128 #define GPMC_CS_NAND_ADDRESS 0x20 129 #define GPMC_CS_NAND_DATA 0x24 130 131 /* Control Commands */ 132 #define GPMC_CONFIG_RDY_BSY 0x00000001 133 #define GPMC_CONFIG_DEV_SIZE 0x00000002 134 #define GPMC_CONFIG_DEV_TYPE 0x00000003 135 136 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 137 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 138 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 139 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 140 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 141 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 142 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 143 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) 144 /** CLKACTIVATIONTIME Max Ticks */ 145 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 146 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) 147 /** ATTACHEDDEVICEPAGELENGTH Max Value */ 148 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 149 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 150 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 151 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18) 152 /** WAITMONITORINGTIME Max Ticks */ 153 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 154 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) 155 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) 156 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 157 /** DEVICESIZE Max Value */ 158 #define GPMC_CONFIG1_DEVICESIZE_MAX 1 159 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) 160 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 161 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8) 162 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 163 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) 164 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 165 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 166 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 167 #define GPMC_CONFIG7_CSVALID (1 << 6) 168 169 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f 170 #define GPMC_CONFIG7_CSVALID_MASK BIT(6) 171 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 172 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) 173 /* All CONFIG7 bits except reserved bits */ 174 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ 175 GPMC_CONFIG7_CSVALID_MASK | \ 176 GPMC_CONFIG7_MASKADDRESS_MASK) 177 178 #define GPMC_DEVICETYPE_NOR 0 179 #define GPMC_DEVICETYPE_NAND 2 180 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 181 #define WR_RD_PIN_MONITORING 0x00600000 182 183 /* ECC commands */ 184 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 185 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 186 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 187 188 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */ 189 190 enum gpmc_clk_domain { 191 GPMC_CD_FCLK, 192 GPMC_CD_CLK 193 }; 194 195 struct gpmc_cs_data { 196 const char *name; 197 198 #define GPMC_CS_RESERVED (1 << 0) 199 u32 flags; 200 201 struct resource mem; 202 }; 203 204 /* Structure to save gpmc cs context */ 205 struct gpmc_cs_config { 206 u32 config1; 207 u32 config2; 208 u32 config3; 209 u32 config4; 210 u32 config5; 211 u32 config6; 212 u32 config7; 213 int is_valid; 214 }; 215 216 /* 217 * Structure to save/restore gpmc context 218 * to support core off on OMAP3 219 */ 220 struct omap3_gpmc_regs { 221 u32 sysconfig; 222 u32 irqenable; 223 u32 timeout_ctrl; 224 u32 config; 225 u32 prefetch_config1; 226 u32 prefetch_config2; 227 u32 prefetch_control; 228 struct gpmc_cs_config cs_context[GPMC_CS_NUM]; 229 }; 230 231 struct gpmc_device { 232 struct device *dev; 233 int irq; 234 struct irq_chip irq_chip; 235 struct gpio_chip gpio_chip; 236 int nirqs; 237 }; 238 239 static struct irq_domain *gpmc_irq_domain; 240 241 static struct resource gpmc_mem_root; 242 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; 243 static DEFINE_SPINLOCK(gpmc_mem_lock); 244 /* Define chip-selects as reserved by default until probe completes */ 245 static unsigned int gpmc_cs_num = GPMC_CS_NUM; 246 static unsigned int gpmc_nr_waitpins; 247 static resource_size_t phys_base, mem_size; 248 static unsigned gpmc_capability; 249 static void __iomem *gpmc_base; 250 251 static struct clk *gpmc_l3_clk; 252 253 static irqreturn_t gpmc_handle_irq(int irq, void *dev); 254 255 static void gpmc_write_reg(int idx, u32 val) 256 { 257 writel_relaxed(val, gpmc_base + idx); 258 } 259 260 static u32 gpmc_read_reg(int idx) 261 { 262 return readl_relaxed(gpmc_base + idx); 263 } 264 265 void gpmc_cs_write_reg(int cs, int idx, u32 val) 266 { 267 void __iomem *reg_addr; 268 269 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 270 writel_relaxed(val, reg_addr); 271 } 272 273 static u32 gpmc_cs_read_reg(int cs, int idx) 274 { 275 void __iomem *reg_addr; 276 277 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 278 return readl_relaxed(reg_addr); 279 } 280 281 /* TODO: Add support for gpmc_fck to clock framework and use it */ 282 static unsigned long gpmc_get_fclk_period(void) 283 { 284 unsigned long rate = clk_get_rate(gpmc_l3_clk); 285 286 rate /= 1000; 287 rate = 1000000000 / rate; /* In picoseconds */ 288 289 return rate; 290 } 291 292 /** 293 * gpmc_get_clk_period - get period of selected clock domain in ps 294 * @cs Chip Select Region. 295 * @cd Clock Domain. 296 * 297 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup 298 * prior to calling this function with GPMC_CD_CLK. 299 */ 300 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) 301 { 302 303 unsigned long tick_ps = gpmc_get_fclk_period(); 304 u32 l; 305 int div; 306 307 switch (cd) { 308 case GPMC_CD_CLK: 309 /* get current clk divider */ 310 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 311 div = (l & 0x03) + 1; 312 /* get GPMC_CLK period */ 313 tick_ps *= div; 314 break; 315 case GPMC_CD_FCLK: 316 /* FALL-THROUGH */ 317 default: 318 break; 319 } 320 321 return tick_ps; 322 323 } 324 325 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, 326 enum gpmc_clk_domain cd) 327 { 328 unsigned long tick_ps; 329 330 /* Calculate in picosecs to yield more exact results */ 331 tick_ps = gpmc_get_clk_period(cs, cd); 332 333 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 334 } 335 336 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 337 { 338 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); 339 } 340 341 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 342 { 343 unsigned long tick_ps; 344 345 /* Calculate in picosecs to yield more exact results */ 346 tick_ps = gpmc_get_fclk_period(); 347 348 return (time_ps + tick_ps - 1) / tick_ps; 349 } 350 351 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, 352 enum gpmc_clk_domain cd) 353 { 354 return ticks * gpmc_get_clk_period(cs, cd) / 1000; 355 } 356 357 unsigned int gpmc_ticks_to_ns(unsigned int ticks) 358 { 359 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); 360 } 361 362 static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 363 { 364 return ticks * gpmc_get_fclk_period(); 365 } 366 367 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) 368 { 369 unsigned long ticks = gpmc_ps_to_ticks(time_ps); 370 371 return ticks * gpmc_get_fclk_period(); 372 } 373 374 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) 375 { 376 u32 l; 377 378 l = gpmc_cs_read_reg(cs, reg); 379 if (value) 380 l |= mask; 381 else 382 l &= ~mask; 383 gpmc_cs_write_reg(cs, reg, l); 384 } 385 386 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) 387 { 388 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, 389 GPMC_CONFIG1_TIME_PARA_GRAN, 390 p->time_para_granularity); 391 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, 392 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); 393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, 394 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); 395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 396 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 397 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 398 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); 399 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 400 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 401 p->cycle2cyclesamecsen); 402 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 403 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, 404 p->cycle2cyclediffcsen); 405 } 406 407 #ifdef CONFIG_OMAP_GPMC_DEBUG 408 /** 409 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. 410 * @cs: Chip Select Region 411 * @reg: GPMC_CS_CONFIGn register offset. 412 * @st_bit: Start Bit 413 * @end_bit: End Bit. Must be >= @st_bit. 414 * @ma:x Maximum parameter value (before optional @shift). 415 * If 0, maximum is as high as @st_bit and @end_bit allow. 416 * @name: DTS node name, w/o "gpmc," 417 * @cd: Clock Domain of timing parameter. 418 * @shift: Parameter value left shifts @shift, which is then printed instead of value. 419 * @raw: Raw Format Option. 420 * raw format: gpmc,name = <value> 421 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ 422 * Where x ns -- y ns result in the same tick value. 423 * When @max is exceeded, "invalid" is printed inside comment. 424 * @noval: Parameter values equal to 0 are not printed. 425 * @return: Specified timing parameter (after optional @shift). 426 * 427 */ 428 static int get_gpmc_timing_reg( 429 /* timing specifiers */ 430 int cs, int reg, int st_bit, int end_bit, int max, 431 const char *name, const enum gpmc_clk_domain cd, 432 /* value transform */ 433 int shift, 434 /* format specifiers */ 435 bool raw, bool noval) 436 { 437 u32 l; 438 int nr_bits; 439 int mask; 440 bool invalid; 441 442 l = gpmc_cs_read_reg(cs, reg); 443 nr_bits = end_bit - st_bit + 1; 444 mask = (1 << nr_bits) - 1; 445 l = (l >> st_bit) & mask; 446 if (!max) 447 max = mask; 448 invalid = l > max; 449 if (shift) 450 l = (shift << l); 451 if (noval && (l == 0)) 452 return 0; 453 if (!raw) { 454 /* DTS tick format for timings in ns */ 455 unsigned int time_ns; 456 unsigned int time_ns_min = 0; 457 458 if (l) 459 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; 460 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); 461 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", 462 name, time_ns, time_ns_min, time_ns, l, 463 invalid ? "; invalid " : " "); 464 } else { 465 /* raw format */ 466 pr_info("gpmc,%s = <%u>;%s\n", name, l, 467 invalid ? " /* invalid */" : ""); 468 } 469 470 return l; 471 } 472 473 #define GPMC_PRINT_CONFIG(cs, config) \ 474 pr_info("cs%i %s: 0x%08x\n", cs, #config, \ 475 gpmc_cs_read_reg(cs, config)) 476 #define GPMC_GET_RAW(reg, st, end, field) \ 477 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) 478 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ 479 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) 480 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ 481 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) 482 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ 483 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) 484 #define GPMC_GET_TICKS(reg, st, end, field) \ 485 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) 486 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ 487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) 488 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ 489 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) 490 491 static void gpmc_show_regs(int cs, const char *desc) 492 { 493 pr_info("gpmc cs%i %s:\n", cs, desc); 494 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); 495 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); 496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); 497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); 498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); 499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); 500 } 501 502 /* 503 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, 504 * see commit c9fb809. 505 */ 506 static void gpmc_cs_show_timings(int cs, const char *desc) 507 { 508 gpmc_show_regs(cs, desc); 509 510 pr_info("gpmc cs%i access configuration:\n", cs); 511 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); 512 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); 513 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, 514 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); 515 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); 516 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); 517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); 518 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, 519 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, 520 "burst-length"); 521 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); 522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); 523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); 524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); 525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); 526 527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); 528 529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); 530 531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); 532 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); 533 534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); 535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); 536 537 pr_info("gpmc cs%i timings configuration:\n", cs); 538 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); 539 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); 540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); 541 542 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); 543 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); 544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); 545 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); 547 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, 548 "adv-aad-mux-rd-off-ns"); 549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, 550 "adv-aad-mux-wr-off-ns"); 551 } 552 553 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); 554 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); 555 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); 557 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); 558 } 559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); 560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); 561 562 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); 563 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); 564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); 565 566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); 567 568 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); 569 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); 570 571 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 572 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 573 "wait-monitoring-ns", GPMC_CD_CLK); 574 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 575 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 576 "clk-activation-ns", GPMC_CD_FCLK); 577 578 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); 579 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); 580 } 581 #else 582 static inline void gpmc_cs_show_timings(int cs, const char *desc) 583 { 584 } 585 #endif 586 587 /** 588 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. 589 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER 590 * prior to calling this function with @cd equal to GPMC_CD_CLK. 591 * 592 * @cs: Chip Select Region. 593 * @reg: GPMC_CS_CONFIGn register offset. 594 * @st_bit: Start Bit 595 * @end_bit: End Bit. Must be >= @st_bit. 596 * @max: Maximum parameter value. 597 * If 0, maximum is as high as @st_bit and @end_bit allow. 598 * @time: Timing parameter in ns. 599 * @cd: Timing parameter clock domain. 600 * @name: Timing parameter name. 601 * @return: 0 on success, -1 on error. 602 */ 603 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, 604 int time, enum gpmc_clk_domain cd, const char *name) 605 { 606 u32 l; 607 int ticks, mask, nr_bits; 608 609 if (time == 0) 610 ticks = 0; 611 else 612 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); 613 nr_bits = end_bit - st_bit + 1; 614 mask = (1 << nr_bits) - 1; 615 616 if (!max) 617 max = mask; 618 619 if (ticks > max) { 620 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", 621 __func__, cs, name, time, ticks, max); 622 623 return -1; 624 } 625 626 l = gpmc_cs_read_reg(cs, reg); 627 #ifdef CONFIG_OMAP_GPMC_DEBUG 628 pr_info( 629 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", 630 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, 631 (l >> st_bit) & mask, time); 632 #endif 633 l &= ~(mask << st_bit); 634 l |= ticks << st_bit; 635 gpmc_cs_write_reg(cs, reg, l); 636 637 return 0; 638 } 639 640 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \ 641 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \ 642 t->field, (cd), #field) < 0) \ 643 return -1 644 645 #define GPMC_SET_ONE(reg, st, end, field) \ 646 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK) 647 648 /** 649 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME 650 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. 651 * read --> don't sample bus too early 652 * write --> data is longer on bus 653 * 654 * Formula: 655 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) 656 * / waitmonitoring_ticks) 657 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by 658 * div <= 0 check. 659 * 660 * @wait_monitoring: WAITMONITORINGTIME in ns. 661 * @return: -1 on failure to scale, else proper divider > 0. 662 */ 663 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) 664 { 665 666 int div = gpmc_ns_to_ticks(wait_monitoring); 667 668 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; 669 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; 670 671 if (div > 4) 672 return -1; 673 if (div <= 0) 674 div = 1; 675 676 return div; 677 678 } 679 680 /** 681 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. 682 * @sync_clk: GPMC_CLK period in ps. 683 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. 684 * Else, returns -1. 685 */ 686 int gpmc_calc_divider(unsigned int sync_clk) 687 { 688 int div = gpmc_ps_to_ticks(sync_clk); 689 690 if (div > 4) 691 return -1; 692 if (div <= 0) 693 div = 1; 694 695 return div; 696 } 697 698 /** 699 * gpmc_cs_set_timings - program timing parameters for Chip Select Region. 700 * @cs: Chip Select Region. 701 * @t: GPMC timing parameters. 702 * @s: GPMC timing settings. 703 * @return: 0 on success, -1 on error. 704 */ 705 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, 706 const struct gpmc_settings *s) 707 { 708 int div; 709 u32 l; 710 711 div = gpmc_calc_divider(t->sync_clk); 712 if (div < 0) 713 return div; 714 715 /* 716 * See if we need to change the divider for waitmonitoringtime. 717 * 718 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for 719 * pure asynchronous accesses, i.e. both read and write asynchronous. 720 * However, only do so if WAITMONITORINGTIME is actually used, i.e. 721 * either WAITREADMONITORING or WAITWRITEMONITORING is set. 722 * 723 * This statement must not change div to scale async WAITMONITORINGTIME 724 * to protect mixed synchronous and asynchronous accesses. 725 * 726 * We raise an error later if WAITMONITORINGTIME does not fit. 727 */ 728 if (!s->sync_read && !s->sync_write && 729 (s->wait_on_read || s->wait_on_write) 730 ) { 731 732 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); 733 if (div < 0) { 734 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", 735 __func__, 736 t->wait_monitoring 737 ); 738 return -1; 739 } 740 } 741 742 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); 743 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); 744 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); 745 746 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); 747 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); 748 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); 749 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on); 751 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off); 752 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off); 753 } 754 755 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); 756 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); 757 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on); 759 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off); 760 } 761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); 762 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); 763 764 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); 765 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); 766 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); 767 768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); 769 770 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); 771 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); 772 773 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 774 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); 775 if (gpmc_capability & GPMC_HAS_WR_ACCESS) 776 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); 777 778 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 779 l &= ~0x03; 780 l |= (div - 1); 781 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); 782 783 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 784 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 785 wait_monitoring, GPMC_CD_CLK); 786 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 787 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 788 clk_activation, GPMC_CD_FCLK); 789 790 #ifdef CONFIG_OMAP_GPMC_DEBUG 791 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", 792 cs, (div * gpmc_get_fclk_period()) / 1000, div); 793 #endif 794 795 gpmc_cs_bool_timings(cs, &t->bool_timings); 796 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); 797 798 return 0; 799 } 800 801 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) 802 { 803 u32 l; 804 u32 mask; 805 806 /* 807 * Ensure that base address is aligned on a 808 * boundary equal to or greater than size. 809 */ 810 if (base & (size - 1)) 811 return -EINVAL; 812 813 base >>= GPMC_CHUNK_SHIFT; 814 mask = (1 << GPMC_SECTION_SHIFT) - size; 815 mask >>= GPMC_CHUNK_SHIFT; 816 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; 817 818 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 819 l &= ~GPMC_CONFIG7_MASK; 820 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; 821 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; 822 l |= GPMC_CONFIG7_CSVALID; 823 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 824 825 return 0; 826 } 827 828 static void gpmc_cs_enable_mem(int cs) 829 { 830 u32 l; 831 832 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 833 l |= GPMC_CONFIG7_CSVALID; 834 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 835 } 836 837 static void gpmc_cs_disable_mem(int cs) 838 { 839 u32 l; 840 841 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 842 l &= ~GPMC_CONFIG7_CSVALID; 843 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 844 } 845 846 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) 847 { 848 u32 l; 849 u32 mask; 850 851 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 852 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; 853 mask = (l >> 8) & 0x0f; 854 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); 855 } 856 857 static int gpmc_cs_mem_enabled(int cs) 858 { 859 u32 l; 860 861 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 862 return l & GPMC_CONFIG7_CSVALID; 863 } 864 865 static void gpmc_cs_set_reserved(int cs, int reserved) 866 { 867 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 868 869 gpmc->flags |= GPMC_CS_RESERVED; 870 } 871 872 static bool gpmc_cs_reserved(int cs) 873 { 874 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 875 876 return gpmc->flags & GPMC_CS_RESERVED; 877 } 878 879 static void gpmc_cs_set_name(int cs, const char *name) 880 { 881 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 882 883 gpmc->name = name; 884 } 885 886 static const char *gpmc_cs_get_name(int cs) 887 { 888 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 889 890 return gpmc->name; 891 } 892 893 static unsigned long gpmc_mem_align(unsigned long size) 894 { 895 int order; 896 897 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); 898 order = GPMC_CHUNK_SHIFT - 1; 899 do { 900 size >>= 1; 901 order++; 902 } while (size); 903 size = 1 << order; 904 return size; 905 } 906 907 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 908 { 909 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 910 struct resource *res = &gpmc->mem; 911 int r; 912 913 size = gpmc_mem_align(size); 914 spin_lock(&gpmc_mem_lock); 915 res->start = base; 916 res->end = base + size - 1; 917 r = request_resource(&gpmc_mem_root, res); 918 spin_unlock(&gpmc_mem_lock); 919 920 return r; 921 } 922 923 static int gpmc_cs_delete_mem(int cs) 924 { 925 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 926 struct resource *res = &gpmc->mem; 927 int r; 928 929 spin_lock(&gpmc_mem_lock); 930 r = release_resource(res); 931 res->start = 0; 932 res->end = 0; 933 spin_unlock(&gpmc_mem_lock); 934 935 return r; 936 } 937 938 /** 939 * gpmc_cs_remap - remaps a chip-select physical base address 940 * @cs: chip-select to remap 941 * @base: physical base address to re-map chip-select to 942 * 943 * Re-maps a chip-select to a new physical base address specified by 944 * "base". Returns 0 on success and appropriate negative error code 945 * on failure. 946 */ 947 static int gpmc_cs_remap(int cs, u32 base) 948 { 949 int ret; 950 u32 old_base, size; 951 952 if (cs > gpmc_cs_num) { 953 pr_err("%s: requested chip-select is disabled\n", __func__); 954 return -ENODEV; 955 } 956 957 /* 958 * Make sure we ignore any device offsets from the GPMC partition 959 * allocated for the chip select and that the new base confirms 960 * to the GPMC 16MB minimum granularity. 961 */ 962 base &= ~(SZ_16M - 1); 963 964 gpmc_cs_get_memconf(cs, &old_base, &size); 965 if (base == old_base) 966 return 0; 967 968 ret = gpmc_cs_delete_mem(cs); 969 if (ret < 0) 970 return ret; 971 972 ret = gpmc_cs_insert_mem(cs, base, size); 973 if (ret < 0) 974 return ret; 975 976 ret = gpmc_cs_set_memconf(cs, base, size); 977 978 return ret; 979 } 980 981 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 982 { 983 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 984 struct resource *res = &gpmc->mem; 985 int r = -1; 986 987 if (cs > gpmc_cs_num) { 988 pr_err("%s: requested chip-select is disabled\n", __func__); 989 return -ENODEV; 990 } 991 size = gpmc_mem_align(size); 992 if (size > (1 << GPMC_SECTION_SHIFT)) 993 return -ENOMEM; 994 995 spin_lock(&gpmc_mem_lock); 996 if (gpmc_cs_reserved(cs)) { 997 r = -EBUSY; 998 goto out; 999 } 1000 if (gpmc_cs_mem_enabled(cs)) 1001 r = adjust_resource(res, res->start & ~(size - 1), size); 1002 if (r < 0) 1003 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, 1004 size, NULL, NULL); 1005 if (r < 0) 1006 goto out; 1007 1008 /* Disable CS while changing base address and size mask */ 1009 gpmc_cs_disable_mem(cs); 1010 1011 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); 1012 if (r < 0) { 1013 release_resource(res); 1014 goto out; 1015 } 1016 1017 /* Enable CS */ 1018 gpmc_cs_enable_mem(cs); 1019 *base = res->start; 1020 gpmc_cs_set_reserved(cs, 1); 1021 out: 1022 spin_unlock(&gpmc_mem_lock); 1023 return r; 1024 } 1025 EXPORT_SYMBOL(gpmc_cs_request); 1026 1027 void gpmc_cs_free(int cs) 1028 { 1029 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1030 struct resource *res = &gpmc->mem; 1031 1032 spin_lock(&gpmc_mem_lock); 1033 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 1034 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); 1035 BUG(); 1036 spin_unlock(&gpmc_mem_lock); 1037 return; 1038 } 1039 gpmc_cs_disable_mem(cs); 1040 if (res->flags) 1041 release_resource(res); 1042 gpmc_cs_set_reserved(cs, 0); 1043 spin_unlock(&gpmc_mem_lock); 1044 } 1045 EXPORT_SYMBOL(gpmc_cs_free); 1046 1047 /** 1048 * gpmc_configure - write request to configure gpmc 1049 * @cmd: command type 1050 * @wval: value to write 1051 * @return status of the operation 1052 */ 1053 int gpmc_configure(int cmd, int wval) 1054 { 1055 u32 regval; 1056 1057 switch (cmd) { 1058 case GPMC_CONFIG_WP: 1059 regval = gpmc_read_reg(GPMC_CONFIG); 1060 if (wval) 1061 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ 1062 else 1063 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ 1064 gpmc_write_reg(GPMC_CONFIG, regval); 1065 break; 1066 1067 default: 1068 pr_err("%s: command not supported\n", __func__); 1069 return -EINVAL; 1070 } 1071 1072 return 0; 1073 } 1074 EXPORT_SYMBOL(gpmc_configure); 1075 1076 static bool gpmc_nand_writebuffer_empty(void) 1077 { 1078 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) 1079 return true; 1080 1081 return false; 1082 } 1083 1084 static struct gpmc_nand_ops nand_ops = { 1085 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, 1086 }; 1087 1088 /** 1089 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface 1090 * @regs: the GPMC NAND register map exclusive for NAND use. 1091 * @cs: GPMC chip select number on which the NAND sits. The 1092 * register map returned will be specific to this chip select. 1093 * 1094 * Returns NULL on error e.g. invalid cs. 1095 */ 1096 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) 1097 { 1098 int i; 1099 1100 if (cs >= gpmc_cs_num) 1101 return NULL; 1102 1103 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 1104 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 1105 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + 1106 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; 1107 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + 1108 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; 1109 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; 1110 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; 1111 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; 1112 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; 1113 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; 1114 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 1115 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 1116 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 1117 1118 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { 1119 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + 1120 GPMC_BCH_SIZE * i; 1121 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + 1122 GPMC_BCH_SIZE * i; 1123 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + 1124 GPMC_BCH_SIZE * i; 1125 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + 1126 GPMC_BCH_SIZE * i; 1127 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + 1128 i * GPMC_BCH_SIZE; 1129 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + 1130 i * GPMC_BCH_SIZE; 1131 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + 1132 i * GPMC_BCH_SIZE; 1133 } 1134 1135 return &nand_ops; 1136 } 1137 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); 1138 1139 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t, 1140 struct gpmc_settings *s, 1141 int freq, int latency) 1142 { 1143 struct gpmc_device_timings dev_t; 1144 const int t_cer = 15; 1145 const int t_avdp = 12; 1146 const int t_cez = 20; /* max of t_cez, t_oez */ 1147 const int t_wpl = 40; 1148 const int t_wph = 30; 1149 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 1150 1151 switch (freq) { 1152 case 104: 1153 min_gpmc_clk_period = 9600; /* 104 MHz */ 1154 t_ces = 3; 1155 t_avds = 4; 1156 t_avdh = 2; 1157 t_ach = 3; 1158 t_aavdh = 6; 1159 t_rdyo = 6; 1160 break; 1161 case 83: 1162 min_gpmc_clk_period = 12000; /* 83 MHz */ 1163 t_ces = 5; 1164 t_avds = 4; 1165 t_avdh = 2; 1166 t_ach = 6; 1167 t_aavdh = 6; 1168 t_rdyo = 9; 1169 break; 1170 case 66: 1171 min_gpmc_clk_period = 15000; /* 66 MHz */ 1172 t_ces = 6; 1173 t_avds = 5; 1174 t_avdh = 2; 1175 t_ach = 6; 1176 t_aavdh = 6; 1177 t_rdyo = 11; 1178 break; 1179 default: 1180 min_gpmc_clk_period = 18500; /* 54 MHz */ 1181 t_ces = 7; 1182 t_avds = 7; 1183 t_avdh = 7; 1184 t_ach = 9; 1185 t_aavdh = 7; 1186 t_rdyo = 15; 1187 break; 1188 } 1189 1190 /* Set synchronous read timings */ 1191 memset(&dev_t, 0, sizeof(dev_t)); 1192 1193 if (!s->sync_write) { 1194 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; 1195 dev_t.t_wpl = t_wpl * 1000; 1196 dev_t.t_wph = t_wph * 1000; 1197 dev_t.t_aavdh = t_aavdh * 1000; 1198 } 1199 dev_t.ce_xdelay = true; 1200 dev_t.avd_xdelay = true; 1201 dev_t.oe_xdelay = true; 1202 dev_t.we_xdelay = true; 1203 dev_t.clk = min_gpmc_clk_period; 1204 dev_t.t_bacc = dev_t.clk; 1205 dev_t.t_ces = t_ces * 1000; 1206 dev_t.t_avds = t_avds * 1000; 1207 dev_t.t_avdh = t_avdh * 1000; 1208 dev_t.t_ach = t_ach * 1000; 1209 dev_t.cyc_iaa = (latency + 1); 1210 dev_t.t_cez_r = t_cez * 1000; 1211 dev_t.t_cez_w = dev_t.t_cez_r; 1212 dev_t.cyc_aavdh_oe = 1; 1213 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; 1214 1215 gpmc_calc_timings(t, s, &dev_t); 1216 } 1217 1218 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, 1219 int latency, 1220 struct gpmc_onenand_info *info) 1221 { 1222 int ret; 1223 struct gpmc_timings gpmc_t; 1224 struct gpmc_settings gpmc_s; 1225 1226 gpmc_read_settings_dt(dev->of_node, &gpmc_s); 1227 1228 info->sync_read = gpmc_s.sync_read; 1229 info->sync_write = gpmc_s.sync_write; 1230 info->burst_len = gpmc_s.burst_len; 1231 1232 if (!gpmc_s.sync_read && !gpmc_s.sync_write) 1233 return 0; 1234 1235 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency); 1236 1237 ret = gpmc_cs_program_settings(cs, &gpmc_s); 1238 if (ret < 0) 1239 return ret; 1240 1241 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 1242 } 1243 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings); 1244 1245 int gpmc_get_client_irq(unsigned irq_config) 1246 { 1247 if (!gpmc_irq_domain) { 1248 pr_warn("%s called before GPMC IRQ domain available\n", 1249 __func__); 1250 return 0; 1251 } 1252 1253 /* we restrict this to NAND IRQs only */ 1254 if (irq_config >= GPMC_NR_NAND_IRQS) 1255 return 0; 1256 1257 return irq_create_mapping(gpmc_irq_domain, irq_config); 1258 } 1259 1260 static int gpmc_irq_endis(unsigned long hwirq, bool endis) 1261 { 1262 u32 regval; 1263 1264 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */ 1265 if (hwirq >= GPMC_NR_NAND_IRQS) 1266 hwirq += 8 - GPMC_NR_NAND_IRQS; 1267 1268 regval = gpmc_read_reg(GPMC_IRQENABLE); 1269 if (endis) 1270 regval |= BIT(hwirq); 1271 else 1272 regval &= ~BIT(hwirq); 1273 gpmc_write_reg(GPMC_IRQENABLE, regval); 1274 1275 return 0; 1276 } 1277 1278 static void gpmc_irq_disable(struct irq_data *p) 1279 { 1280 gpmc_irq_endis(p->hwirq, false); 1281 } 1282 1283 static void gpmc_irq_enable(struct irq_data *p) 1284 { 1285 gpmc_irq_endis(p->hwirq, true); 1286 } 1287 1288 static void gpmc_irq_mask(struct irq_data *d) 1289 { 1290 gpmc_irq_endis(d->hwirq, false); 1291 } 1292 1293 static void gpmc_irq_unmask(struct irq_data *d) 1294 { 1295 gpmc_irq_endis(d->hwirq, true); 1296 } 1297 1298 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge) 1299 { 1300 u32 regval; 1301 1302 /* NAND IRQs polarity is not configurable */ 1303 if (hwirq < GPMC_NR_NAND_IRQS) 1304 return; 1305 1306 /* WAITPIN starts at BIT 8 */ 1307 hwirq += 8 - GPMC_NR_NAND_IRQS; 1308 1309 regval = gpmc_read_reg(GPMC_CONFIG); 1310 if (rising_edge) 1311 regval &= ~BIT(hwirq); 1312 else 1313 regval |= BIT(hwirq); 1314 1315 gpmc_write_reg(GPMC_CONFIG, regval); 1316 } 1317 1318 static void gpmc_irq_ack(struct irq_data *d) 1319 { 1320 unsigned int hwirq = d->hwirq; 1321 1322 /* skip reserved bits */ 1323 if (hwirq >= GPMC_NR_NAND_IRQS) 1324 hwirq += 8 - GPMC_NR_NAND_IRQS; 1325 1326 /* Setting bit to 1 clears (or Acks) the interrupt */ 1327 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); 1328 } 1329 1330 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger) 1331 { 1332 /* can't set type for NAND IRQs */ 1333 if (d->hwirq < GPMC_NR_NAND_IRQS) 1334 return -EINVAL; 1335 1336 /* We can support either rising or falling edge at a time */ 1337 if (trigger == IRQ_TYPE_EDGE_FALLING) 1338 gpmc_irq_edge_config(d->hwirq, false); 1339 else if (trigger == IRQ_TYPE_EDGE_RISING) 1340 gpmc_irq_edge_config(d->hwirq, true); 1341 else 1342 return -EINVAL; 1343 1344 return 0; 1345 } 1346 1347 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, 1348 irq_hw_number_t hw) 1349 { 1350 struct gpmc_device *gpmc = d->host_data; 1351 1352 irq_set_chip_data(virq, gpmc); 1353 if (hw < GPMC_NR_NAND_IRQS) { 1354 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); 1355 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1356 handle_simple_irq); 1357 } else { 1358 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1359 handle_edge_irq); 1360 } 1361 1362 return 0; 1363 } 1364 1365 static const struct irq_domain_ops gpmc_irq_domain_ops = { 1366 .map = gpmc_irq_map, 1367 .xlate = irq_domain_xlate_twocell, 1368 }; 1369 1370 static irqreturn_t gpmc_handle_irq(int irq, void *data) 1371 { 1372 int hwirq, virq; 1373 u32 regval, regvalx; 1374 struct gpmc_device *gpmc = data; 1375 1376 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1377 regvalx = regval; 1378 1379 if (!regval) 1380 return IRQ_NONE; 1381 1382 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { 1383 /* skip reserved status bits */ 1384 if (hwirq == GPMC_NR_NAND_IRQS) 1385 regvalx >>= 8 - GPMC_NR_NAND_IRQS; 1386 1387 if (regvalx & BIT(hwirq)) { 1388 virq = irq_find_mapping(gpmc_irq_domain, hwirq); 1389 if (!virq) { 1390 dev_warn(gpmc->dev, 1391 "spurious irq detected hwirq %d, virq %d\n", 1392 hwirq, virq); 1393 } 1394 1395 generic_handle_irq(virq); 1396 } 1397 } 1398 1399 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1400 1401 return IRQ_HANDLED; 1402 } 1403 1404 static int gpmc_setup_irq(struct gpmc_device *gpmc) 1405 { 1406 u32 regval; 1407 int rc; 1408 1409 /* Disable interrupts */ 1410 gpmc_write_reg(GPMC_IRQENABLE, 0); 1411 1412 /* clear interrupts */ 1413 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1414 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1415 1416 gpmc->irq_chip.name = "gpmc"; 1417 gpmc->irq_chip.irq_enable = gpmc_irq_enable; 1418 gpmc->irq_chip.irq_disable = gpmc_irq_disable; 1419 gpmc->irq_chip.irq_ack = gpmc_irq_ack; 1420 gpmc->irq_chip.irq_mask = gpmc_irq_mask; 1421 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; 1422 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; 1423 1424 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, 1425 gpmc->nirqs, 1426 &gpmc_irq_domain_ops, 1427 gpmc); 1428 if (!gpmc_irq_domain) { 1429 dev_err(gpmc->dev, "IRQ domain add failed\n"); 1430 return -ENODEV; 1431 } 1432 1433 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); 1434 if (rc) { 1435 dev_err(gpmc->dev, "failed to request irq %d: %d\n", 1436 gpmc->irq, rc); 1437 irq_domain_remove(gpmc_irq_domain); 1438 gpmc_irq_domain = NULL; 1439 } 1440 1441 return rc; 1442 } 1443 1444 static int gpmc_free_irq(struct gpmc_device *gpmc) 1445 { 1446 int hwirq; 1447 1448 free_irq(gpmc->irq, gpmc); 1449 1450 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) 1451 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); 1452 1453 irq_domain_remove(gpmc_irq_domain); 1454 gpmc_irq_domain = NULL; 1455 1456 return 0; 1457 } 1458 1459 static void gpmc_mem_exit(void) 1460 { 1461 int cs; 1462 1463 for (cs = 0; cs < gpmc_cs_num; cs++) { 1464 if (!gpmc_cs_mem_enabled(cs)) 1465 continue; 1466 gpmc_cs_delete_mem(cs); 1467 } 1468 1469 } 1470 1471 static void gpmc_mem_init(void) 1472 { 1473 int cs; 1474 1475 gpmc_mem_root.start = GPMC_MEM_START; 1476 gpmc_mem_root.end = GPMC_MEM_END; 1477 1478 /* Reserve all regions that has been set up by bootloader */ 1479 for (cs = 0; cs < gpmc_cs_num; cs++) { 1480 u32 base, size; 1481 1482 if (!gpmc_cs_mem_enabled(cs)) 1483 continue; 1484 gpmc_cs_get_memconf(cs, &base, &size); 1485 if (gpmc_cs_insert_mem(cs, base, size)) { 1486 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", 1487 __func__, cs, base, base + size); 1488 gpmc_cs_disable_mem(cs); 1489 } 1490 } 1491 } 1492 1493 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 1494 { 1495 u32 temp; 1496 int div; 1497 1498 div = gpmc_calc_divider(sync_clk); 1499 temp = gpmc_ps_to_ticks(time_ps); 1500 temp = (temp + div - 1) / div; 1501 return gpmc_ticks_to_ps(temp * div); 1502 } 1503 1504 /* XXX: can the cycles be avoided ? */ 1505 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 1506 struct gpmc_device_timings *dev_t, 1507 bool mux) 1508 { 1509 u32 temp; 1510 1511 /* adv_rd_off */ 1512 temp = dev_t->t_avdp_r; 1513 /* XXX: mux check required ? */ 1514 if (mux) { 1515 /* XXX: t_avdp not to be required for sync, only added for tusb 1516 * this indirectly necessitates requirement of t_avdp_r and 1517 * t_avdp_w instead of having a single t_avdp 1518 */ 1519 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); 1520 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1521 } 1522 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1523 1524 /* oe_on */ 1525 temp = dev_t->t_oeasu; /* XXX: remove this ? */ 1526 if (mux) { 1527 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); 1528 temp = max_t(u32, temp, gpmc_t->adv_rd_off + 1529 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); 1530 } 1531 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1532 1533 /* access */ 1534 /* XXX: any scope for improvement ?, by combining oe_on 1535 * and clk_activation, need to check whether 1536 * access = clk_activation + round to sync clk ? 1537 */ 1538 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); 1539 temp += gpmc_t->clk_activation; 1540 if (dev_t->cyc_oe) 1541 temp = max_t(u32, temp, gpmc_t->oe_on + 1542 gpmc_ticks_to_ps(dev_t->cyc_oe)); 1543 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1544 1545 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1546 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1547 1548 /* rd_cycle */ 1549 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); 1550 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + 1551 gpmc_t->access; 1552 /* XXX: barter t_ce_rdyz with t_cez_r ? */ 1553 if (dev_t->t_ce_rdyz) 1554 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); 1555 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1556 1557 return 0; 1558 } 1559 1560 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 1561 struct gpmc_device_timings *dev_t, 1562 bool mux) 1563 { 1564 u32 temp; 1565 1566 /* adv_wr_off */ 1567 temp = dev_t->t_avdp_w; 1568 if (mux) { 1569 temp = max_t(u32, temp, 1570 gpmc_t->clk_activation + dev_t->t_avdh); 1571 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1572 } 1573 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1574 1575 /* wr_data_mux_bus */ 1576 temp = max_t(u32, dev_t->t_weasu, 1577 gpmc_t->clk_activation + dev_t->t_rdyo); 1578 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, 1579 * and in that case remember to handle we_on properly 1580 */ 1581 if (mux) { 1582 temp = max_t(u32, temp, 1583 gpmc_t->adv_wr_off + dev_t->t_aavdh); 1584 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1585 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1586 } 1587 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1588 1589 /* we_on */ 1590 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1591 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1592 else 1593 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1594 1595 /* wr_access */ 1596 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ 1597 gpmc_t->wr_access = gpmc_t->access; 1598 1599 /* we_off */ 1600 temp = gpmc_t->we_on + dev_t->t_wpl; 1601 temp = max_t(u32, temp, 1602 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); 1603 temp = max_t(u32, temp, 1604 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); 1605 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1606 1607 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1608 dev_t->t_wph); 1609 1610 /* wr_cycle */ 1611 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); 1612 temp += gpmc_t->wr_access; 1613 /* XXX: barter t_ce_rdyz with t_cez_w ? */ 1614 if (dev_t->t_ce_rdyz) 1615 temp = max_t(u32, temp, 1616 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); 1617 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1618 1619 return 0; 1620 } 1621 1622 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 1623 struct gpmc_device_timings *dev_t, 1624 bool mux) 1625 { 1626 u32 temp; 1627 1628 /* adv_rd_off */ 1629 temp = dev_t->t_avdp_r; 1630 if (mux) 1631 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1632 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1633 1634 /* oe_on */ 1635 temp = dev_t->t_oeasu; 1636 if (mux) 1637 temp = max_t(u32, temp, 1638 gpmc_t->adv_rd_off + dev_t->t_aavdh); 1639 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1640 1641 /* access */ 1642 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ 1643 gpmc_t->oe_on + dev_t->t_oe); 1644 temp = max_t(u32, temp, 1645 gpmc_t->cs_on + dev_t->t_ce); 1646 temp = max_t(u32, temp, 1647 gpmc_t->adv_on + dev_t->t_aa); 1648 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1649 1650 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1651 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1652 1653 /* rd_cycle */ 1654 temp = max_t(u32, dev_t->t_rd_cycle, 1655 gpmc_t->cs_rd_off + dev_t->t_cez_r); 1656 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); 1657 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1658 1659 return 0; 1660 } 1661 1662 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 1663 struct gpmc_device_timings *dev_t, 1664 bool mux) 1665 { 1666 u32 temp; 1667 1668 /* adv_wr_off */ 1669 temp = dev_t->t_avdp_w; 1670 if (mux) 1671 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1672 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1673 1674 /* wr_data_mux_bus */ 1675 temp = dev_t->t_weasu; 1676 if (mux) { 1677 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); 1678 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1679 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1680 } 1681 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1682 1683 /* we_on */ 1684 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1685 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1686 else 1687 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1688 1689 /* we_off */ 1690 temp = gpmc_t->we_on + dev_t->t_wpl; 1691 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1692 1693 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1694 dev_t->t_wph); 1695 1696 /* wr_cycle */ 1697 temp = max_t(u32, dev_t->t_wr_cycle, 1698 gpmc_t->cs_wr_off + dev_t->t_cez_w); 1699 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1700 1701 return 0; 1702 } 1703 1704 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, 1705 struct gpmc_device_timings *dev_t) 1706 { 1707 u32 temp; 1708 1709 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * 1710 gpmc_get_fclk_period(); 1711 1712 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( 1713 dev_t->t_bacc, 1714 gpmc_t->sync_clk); 1715 1716 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); 1717 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); 1718 1719 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) 1720 return 0; 1721 1722 if (dev_t->ce_xdelay) 1723 gpmc_t->bool_timings.cs_extra_delay = true; 1724 if (dev_t->avd_xdelay) 1725 gpmc_t->bool_timings.adv_extra_delay = true; 1726 if (dev_t->oe_xdelay) 1727 gpmc_t->bool_timings.oe_extra_delay = true; 1728 if (dev_t->we_xdelay) 1729 gpmc_t->bool_timings.we_extra_delay = true; 1730 1731 return 0; 1732 } 1733 1734 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1735 struct gpmc_device_timings *dev_t, 1736 bool sync) 1737 { 1738 u32 temp; 1739 1740 /* cs_on */ 1741 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); 1742 1743 /* adv_on */ 1744 temp = dev_t->t_avdasu; 1745 if (dev_t->t_ce_avd) 1746 temp = max_t(u32, temp, 1747 gpmc_t->cs_on + dev_t->t_ce_avd); 1748 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1749 1750 if (sync) 1751 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1752 1753 return 0; 1754 } 1755 1756 /* TODO: remove this function once all peripherals are confirmed to 1757 * work with generic timing. Simultaneously gpmc_cs_set_timings() 1758 * has to be modified to handle timings in ps instead of ns 1759 */ 1760 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) 1761 { 1762 t->cs_on /= 1000; 1763 t->cs_rd_off /= 1000; 1764 t->cs_wr_off /= 1000; 1765 t->adv_on /= 1000; 1766 t->adv_rd_off /= 1000; 1767 t->adv_wr_off /= 1000; 1768 t->we_on /= 1000; 1769 t->we_off /= 1000; 1770 t->oe_on /= 1000; 1771 t->oe_off /= 1000; 1772 t->page_burst_access /= 1000; 1773 t->access /= 1000; 1774 t->rd_cycle /= 1000; 1775 t->wr_cycle /= 1000; 1776 t->bus_turnaround /= 1000; 1777 t->cycle2cycle_delay /= 1000; 1778 t->wait_monitoring /= 1000; 1779 t->clk_activation /= 1000; 1780 t->wr_access /= 1000; 1781 t->wr_data_mux_bus /= 1000; 1782 } 1783 1784 int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1785 struct gpmc_settings *gpmc_s, 1786 struct gpmc_device_timings *dev_t) 1787 { 1788 bool mux = false, sync = false; 1789 1790 if (gpmc_s) { 1791 mux = gpmc_s->mux_add_data ? true : false; 1792 sync = (gpmc_s->sync_read || gpmc_s->sync_write); 1793 } 1794 1795 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1796 1797 gpmc_calc_common_timings(gpmc_t, dev_t, sync); 1798 1799 if (gpmc_s && gpmc_s->sync_read) 1800 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); 1801 else 1802 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); 1803 1804 if (gpmc_s && gpmc_s->sync_write) 1805 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); 1806 else 1807 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); 1808 1809 /* TODO: remove, see function definition */ 1810 gpmc_convert_ps_to_ns(gpmc_t); 1811 1812 return 0; 1813 } 1814 1815 /** 1816 * gpmc_cs_program_settings - programs non-timing related settings 1817 * @cs: GPMC chip-select to program 1818 * @p: pointer to GPMC settings structure 1819 * 1820 * Programs non-timing related settings for a GPMC chip-select, such as 1821 * bus-width, burst configuration, etc. Function should be called once 1822 * for each chip-select that is being used and must be called before 1823 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 1824 * register will be initialised to zero by this function. Returns 0 on 1825 * success and appropriate negative error code on failure. 1826 */ 1827 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) 1828 { 1829 u32 config1; 1830 1831 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { 1832 pr_err("%s: invalid width %d!", __func__, p->device_width); 1833 return -EINVAL; 1834 } 1835 1836 /* Address-data multiplexing not supported for NAND devices */ 1837 if (p->device_nand && p->mux_add_data) { 1838 pr_err("%s: invalid configuration!\n", __func__); 1839 return -EINVAL; 1840 } 1841 1842 if ((p->mux_add_data > GPMC_MUX_AD) || 1843 ((p->mux_add_data == GPMC_MUX_AAD) && 1844 !(gpmc_capability & GPMC_HAS_MUX_AAD))) { 1845 pr_err("%s: invalid multiplex configuration!\n", __func__); 1846 return -EINVAL; 1847 } 1848 1849 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ 1850 if (p->burst_read || p->burst_write) { 1851 switch (p->burst_len) { 1852 case GPMC_BURST_4: 1853 case GPMC_BURST_8: 1854 case GPMC_BURST_16: 1855 break; 1856 default: 1857 pr_err("%s: invalid page/burst-length (%d)\n", 1858 __func__, p->burst_len); 1859 return -EINVAL; 1860 } 1861 } 1862 1863 if (p->wait_pin > gpmc_nr_waitpins) { 1864 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1865 return -EINVAL; 1866 } 1867 1868 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); 1869 1870 if (p->sync_read) 1871 config1 |= GPMC_CONFIG1_READTYPE_SYNC; 1872 if (p->sync_write) 1873 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; 1874 if (p->wait_on_read) 1875 config1 |= GPMC_CONFIG1_WAIT_READ_MON; 1876 if (p->wait_on_write) 1877 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; 1878 if (p->wait_on_read || p->wait_on_write) 1879 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); 1880 if (p->device_nand) 1881 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); 1882 if (p->mux_add_data) 1883 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); 1884 if (p->burst_read) 1885 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; 1886 if (p->burst_write) 1887 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; 1888 if (p->burst_read || p->burst_write) { 1889 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); 1890 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; 1891 } 1892 1893 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); 1894 1895 return 0; 1896 } 1897 1898 #ifdef CONFIG_OF 1899 static const struct of_device_id gpmc_dt_ids[] = { 1900 { .compatible = "ti,omap2420-gpmc" }, 1901 { .compatible = "ti,omap2430-gpmc" }, 1902 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 1903 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ 1904 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ 1905 { } 1906 }; 1907 1908 /** 1909 * gpmc_read_settings_dt - read gpmc settings from device-tree 1910 * @np: pointer to device-tree node for a gpmc child device 1911 * @p: pointer to gpmc settings structure 1912 * 1913 * Reads the GPMC settings for a GPMC child device from device-tree and 1914 * stores them in the GPMC settings structure passed. The GPMC settings 1915 * structure is initialised to zero by this function and so any 1916 * previously stored settings will be cleared. 1917 */ 1918 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 1919 { 1920 memset(p, 0, sizeof(struct gpmc_settings)); 1921 1922 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 1923 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 1924 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 1925 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 1926 1927 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { 1928 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); 1929 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); 1930 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); 1931 if (!p->burst_read && !p->burst_write) 1932 pr_warn("%s: page/burst-length set but not used!\n", 1933 __func__); 1934 } 1935 1936 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { 1937 p->wait_on_read = of_property_read_bool(np, 1938 "gpmc,wait-on-read"); 1939 p->wait_on_write = of_property_read_bool(np, 1940 "gpmc,wait-on-write"); 1941 if (!p->wait_on_read && !p->wait_on_write) 1942 pr_debug("%s: rd/wr wait monitoring not enabled!\n", 1943 __func__); 1944 } 1945 } 1946 1947 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 1948 struct gpmc_timings *gpmc_t) 1949 { 1950 struct gpmc_bool_timings *p; 1951 1952 if (!np || !gpmc_t) 1953 return; 1954 1955 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1956 1957 /* minimum clock period for syncronous mode */ 1958 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); 1959 1960 /* chip select timtings */ 1961 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); 1962 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); 1963 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); 1964 1965 /* ADV signal timings */ 1966 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); 1967 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); 1968 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); 1969 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", 1970 &gpmc_t->adv_aad_mux_on); 1971 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", 1972 &gpmc_t->adv_aad_mux_rd_off); 1973 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", 1974 &gpmc_t->adv_aad_mux_wr_off); 1975 1976 /* WE signal timings */ 1977 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); 1978 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); 1979 1980 /* OE signal timings */ 1981 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); 1982 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); 1983 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", 1984 &gpmc_t->oe_aad_mux_on); 1985 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", 1986 &gpmc_t->oe_aad_mux_off); 1987 1988 /* access and cycle timings */ 1989 of_property_read_u32(np, "gpmc,page-burst-access-ns", 1990 &gpmc_t->page_burst_access); 1991 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); 1992 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); 1993 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); 1994 of_property_read_u32(np, "gpmc,bus-turnaround-ns", 1995 &gpmc_t->bus_turnaround); 1996 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", 1997 &gpmc_t->cycle2cycle_delay); 1998 of_property_read_u32(np, "gpmc,wait-monitoring-ns", 1999 &gpmc_t->wait_monitoring); 2000 of_property_read_u32(np, "gpmc,clk-activation-ns", 2001 &gpmc_t->clk_activation); 2002 2003 /* only applicable to OMAP3+ */ 2004 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); 2005 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", 2006 &gpmc_t->wr_data_mux_bus); 2007 2008 /* bool timing parameters */ 2009 p = &gpmc_t->bool_timings; 2010 2011 p->cycle2cyclediffcsen = 2012 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); 2013 p->cycle2cyclesamecsen = 2014 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); 2015 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); 2016 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); 2017 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); 2018 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); 2019 p->time_para_granularity = 2020 of_property_read_bool(np, "gpmc,time-para-granularity"); 2021 } 2022 2023 /** 2024 * gpmc_probe_generic_child - configures the gpmc for a child device 2025 * @pdev: pointer to gpmc platform device 2026 * @child: pointer to device-tree node for child device 2027 * 2028 * Allocates and configures a GPMC chip-select for a child device. 2029 * Returns 0 on success and appropriate negative error code on failure. 2030 */ 2031 static int gpmc_probe_generic_child(struct platform_device *pdev, 2032 struct device_node *child) 2033 { 2034 struct gpmc_settings gpmc_s; 2035 struct gpmc_timings gpmc_t; 2036 struct resource res; 2037 unsigned long base; 2038 const char *name; 2039 int ret, cs; 2040 u32 val; 2041 struct gpio_desc *waitpin_desc = NULL; 2042 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2043 2044 if (of_property_read_u32(child, "reg", &cs) < 0) { 2045 dev_err(&pdev->dev, "%pOF has no 'reg' property\n", 2046 child); 2047 return -ENODEV; 2048 } 2049 2050 if (of_address_to_resource(child, 0, &res) < 0) { 2051 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n", 2052 child); 2053 return -ENODEV; 2054 } 2055 2056 /* 2057 * Check if we have multiple instances of the same device 2058 * on a single chip select. If so, use the already initialized 2059 * timings. 2060 */ 2061 name = gpmc_cs_get_name(cs); 2062 if (name && of_node_name_eq(child, name)) 2063 goto no_timings; 2064 2065 ret = gpmc_cs_request(cs, resource_size(&res), &base); 2066 if (ret < 0) { 2067 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 2068 return ret; 2069 } 2070 gpmc_cs_set_name(cs, child->full_name); 2071 2072 gpmc_read_settings_dt(child, &gpmc_s); 2073 gpmc_read_timings_dt(child, &gpmc_t); 2074 2075 /* 2076 * For some GPMC devices we still need to rely on the bootloader 2077 * timings because the devices can be connected via FPGA. 2078 * REVISIT: Add timing support from slls644g.pdf. 2079 */ 2080 if (!gpmc_t.cs_rd_off) { 2081 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", 2082 cs); 2083 gpmc_cs_show_timings(cs, 2084 "please add GPMC bootloader timings to .dts"); 2085 goto no_timings; 2086 } 2087 2088 /* CS must be disabled while making changes to gpmc configuration */ 2089 gpmc_cs_disable_mem(cs); 2090 2091 /* 2092 * FIXME: gpmc_cs_request() will map the CS to an arbitary 2093 * location in the gpmc address space. When booting with 2094 * device-tree we want the NOR flash to be mapped to the 2095 * location specified in the device-tree blob. So remap the 2096 * CS to this location. Once DT migration is complete should 2097 * just make gpmc_cs_request() map a specific address. 2098 */ 2099 ret = gpmc_cs_remap(cs, res.start); 2100 if (ret < 0) { 2101 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", 2102 cs, &res.start); 2103 if (res.start < GPMC_MEM_START) { 2104 dev_info(&pdev->dev, 2105 "GPMC CS %d start cannot be lesser than 0x%x\n", 2106 cs, GPMC_MEM_START); 2107 } else if (res.end > GPMC_MEM_END) { 2108 dev_info(&pdev->dev, 2109 "GPMC CS %d end cannot be greater than 0x%x\n", 2110 cs, GPMC_MEM_END); 2111 } 2112 goto err; 2113 } 2114 2115 if (of_node_name_eq(child, "nand")) { 2116 /* Warn about older DT blobs with no compatible property */ 2117 if (!of_property_read_bool(child, "compatible")) { 2118 dev_warn(&pdev->dev, 2119 "Incompatible NAND node: missing compatible"); 2120 ret = -EINVAL; 2121 goto err; 2122 } 2123 } 2124 2125 if (of_node_name_eq(child, "onenand")) { 2126 /* Warn about older DT blobs with no compatible property */ 2127 if (!of_property_read_bool(child, "compatible")) { 2128 dev_warn(&pdev->dev, 2129 "Incompatible OneNAND node: missing compatible"); 2130 ret = -EINVAL; 2131 goto err; 2132 } 2133 } 2134 2135 if (of_device_is_compatible(child, "ti,omap2-nand")) { 2136 /* NAND specific setup */ 2137 val = 8; 2138 of_property_read_u32(child, "nand-bus-width", &val); 2139 switch (val) { 2140 case 8: 2141 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; 2142 break; 2143 case 16: 2144 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; 2145 break; 2146 default: 2147 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n", 2148 child); 2149 ret = -EINVAL; 2150 goto err; 2151 } 2152 2153 /* disable write protect */ 2154 gpmc_configure(GPMC_CONFIG_WP, 0); 2155 gpmc_s.device_nand = true; 2156 } else { 2157 ret = of_property_read_u32(child, "bank-width", 2158 &gpmc_s.device_width); 2159 if (ret < 0 && !gpmc_s.device_width) { 2160 dev_err(&pdev->dev, 2161 "%pOF has no 'gpmc,device-width' property\n", 2162 child); 2163 goto err; 2164 } 2165 } 2166 2167 /* Reserve wait pin if it is required and valid */ 2168 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { 2169 unsigned int wait_pin = gpmc_s.wait_pin; 2170 2171 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, 2172 wait_pin, "WAITPIN", 2173 GPIO_ACTIVE_HIGH, 2174 GPIOD_IN); 2175 if (IS_ERR(waitpin_desc)) { 2176 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin); 2177 ret = PTR_ERR(waitpin_desc); 2178 goto err; 2179 } 2180 } 2181 2182 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); 2183 2184 ret = gpmc_cs_program_settings(cs, &gpmc_s); 2185 if (ret < 0) 2186 goto err_cs; 2187 2188 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 2189 if (ret) { 2190 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n", 2191 child); 2192 goto err_cs; 2193 } 2194 2195 /* Clear limited address i.e. enable A26-A11 */ 2196 val = gpmc_read_reg(GPMC_CONFIG); 2197 val &= ~GPMC_CONFIG_LIMITEDADDRESS; 2198 gpmc_write_reg(GPMC_CONFIG, val); 2199 2200 /* Enable CS region */ 2201 gpmc_cs_enable_mem(cs); 2202 2203 no_timings: 2204 2205 /* create platform device, NULL on error or when disabled */ 2206 if (!of_platform_device_create(child, NULL, &pdev->dev)) 2207 goto err_child_fail; 2208 2209 /* is child a common bus? */ 2210 if (of_match_node(of_default_bus_match_table, child)) 2211 /* create children and other common bus children */ 2212 if (of_platform_default_populate(child, NULL, &pdev->dev)) 2213 goto err_child_fail; 2214 2215 return 0; 2216 2217 err_child_fail: 2218 2219 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child); 2220 ret = -ENODEV; 2221 2222 err_cs: 2223 gpiochip_free_own_desc(waitpin_desc); 2224 err: 2225 gpmc_cs_free(cs); 2226 2227 return ret; 2228 } 2229 2230 static int gpmc_probe_dt(struct platform_device *pdev) 2231 { 2232 int ret; 2233 const struct of_device_id *of_id = 2234 of_match_device(gpmc_dt_ids, &pdev->dev); 2235 2236 if (!of_id) 2237 return 0; 2238 2239 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 2240 &gpmc_cs_num); 2241 if (ret < 0) { 2242 pr_err("%s: number of chip-selects not defined\n", __func__); 2243 return ret; 2244 } else if (gpmc_cs_num < 1) { 2245 pr_err("%s: all chip-selects are disabled\n", __func__); 2246 return -EINVAL; 2247 } else if (gpmc_cs_num > GPMC_CS_NUM) { 2248 pr_err("%s: number of supported chip-selects cannot be > %d\n", 2249 __func__, GPMC_CS_NUM); 2250 return -EINVAL; 2251 } 2252 2253 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 2254 &gpmc_nr_waitpins); 2255 if (ret < 0) { 2256 pr_err("%s: number of wait pins not found!\n", __func__); 2257 return ret; 2258 } 2259 2260 return 0; 2261 } 2262 2263 static void gpmc_probe_dt_children(struct platform_device *pdev) 2264 { 2265 int ret; 2266 struct device_node *child; 2267 2268 for_each_available_child_of_node(pdev->dev.of_node, child) { 2269 ret = gpmc_probe_generic_child(pdev, child); 2270 if (ret) { 2271 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n", 2272 child, ret); 2273 } 2274 } 2275 } 2276 #else 2277 static int gpmc_probe_dt(struct platform_device *pdev) 2278 { 2279 return 0; 2280 } 2281 2282 static void gpmc_probe_dt_children(struct platform_device *pdev) 2283 { 2284 } 2285 #endif /* CONFIG_OF */ 2286 2287 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 2288 { 2289 return 1; /* we're input only */ 2290 } 2291 2292 static int gpmc_gpio_direction_input(struct gpio_chip *chip, 2293 unsigned int offset) 2294 { 2295 return 0; /* we're input only */ 2296 } 2297 2298 static int gpmc_gpio_direction_output(struct gpio_chip *chip, 2299 unsigned int offset, int value) 2300 { 2301 return -EINVAL; /* we're input only */ 2302 } 2303 2304 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset, 2305 int value) 2306 { 2307 } 2308 2309 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) 2310 { 2311 u32 reg; 2312 2313 offset += 8; 2314 2315 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); 2316 2317 return !!reg; 2318 } 2319 2320 static int gpmc_gpio_init(struct gpmc_device *gpmc) 2321 { 2322 int ret; 2323 2324 gpmc->gpio_chip.parent = gpmc->dev; 2325 gpmc->gpio_chip.owner = THIS_MODULE; 2326 gpmc->gpio_chip.label = DEVICE_NAME; 2327 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; 2328 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; 2329 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; 2330 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; 2331 gpmc->gpio_chip.set = gpmc_gpio_set; 2332 gpmc->gpio_chip.get = gpmc_gpio_get; 2333 gpmc->gpio_chip.base = -1; 2334 2335 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); 2336 if (ret < 0) { 2337 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); 2338 return ret; 2339 } 2340 2341 return 0; 2342 } 2343 2344 static int gpmc_probe(struct platform_device *pdev) 2345 { 2346 int rc; 2347 u32 l; 2348 struct resource *res; 2349 struct gpmc_device *gpmc; 2350 2351 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); 2352 if (!gpmc) 2353 return -ENOMEM; 2354 2355 gpmc->dev = &pdev->dev; 2356 platform_set_drvdata(pdev, gpmc); 2357 2358 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2359 if (res == NULL) 2360 return -ENOENT; 2361 2362 phys_base = res->start; 2363 mem_size = resource_size(res); 2364 2365 gpmc_base = devm_ioremap_resource(&pdev->dev, res); 2366 if (IS_ERR(gpmc_base)) 2367 return PTR_ERR(gpmc_base); 2368 2369 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 2370 if (!res) { 2371 dev_err(&pdev->dev, "Failed to get resource: irq\n"); 2372 return -ENOENT; 2373 } 2374 2375 gpmc->irq = res->start; 2376 2377 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); 2378 if (IS_ERR(gpmc_l3_clk)) { 2379 dev_err(&pdev->dev, "Failed to get GPMC fck\n"); 2380 return PTR_ERR(gpmc_l3_clk); 2381 } 2382 2383 if (!clk_get_rate(gpmc_l3_clk)) { 2384 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); 2385 return -EINVAL; 2386 } 2387 2388 if (pdev->dev.of_node) { 2389 rc = gpmc_probe_dt(pdev); 2390 if (rc) 2391 return rc; 2392 } else { 2393 gpmc_cs_num = GPMC_CS_NUM; 2394 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 2395 } 2396 2397 pm_runtime_enable(&pdev->dev); 2398 pm_runtime_get_sync(&pdev->dev); 2399 2400 l = gpmc_read_reg(GPMC_REVISION); 2401 2402 /* 2403 * FIXME: Once device-tree migration is complete the below flags 2404 * should be populated based upon the device-tree compatible 2405 * string. For now just use the IP revision. OMAP3+ devices have 2406 * the wr_access and wr_data_mux_bus register fields. OMAP4+ 2407 * devices support the addr-addr-data multiplex protocol. 2408 * 2409 * GPMC IP revisions: 2410 * - OMAP24xx = 2.0 2411 * - OMAP3xxx = 5.0 2412 * - OMAP44xx/54xx/AM335x = 6.0 2413 */ 2414 if (GPMC_REVISION_MAJOR(l) > 0x4) 2415 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 2416 if (GPMC_REVISION_MAJOR(l) > 0x5) 2417 gpmc_capability |= GPMC_HAS_MUX_AAD; 2418 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 2419 GPMC_REVISION_MINOR(l)); 2420 2421 gpmc_mem_init(); 2422 rc = gpmc_gpio_init(gpmc); 2423 if (rc) 2424 goto gpio_init_failed; 2425 2426 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; 2427 rc = gpmc_setup_irq(gpmc); 2428 if (rc) { 2429 dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); 2430 goto gpio_init_failed; 2431 } 2432 2433 gpmc_probe_dt_children(pdev); 2434 2435 return 0; 2436 2437 gpio_init_failed: 2438 gpmc_mem_exit(); 2439 pm_runtime_put_sync(&pdev->dev); 2440 pm_runtime_disable(&pdev->dev); 2441 2442 return rc; 2443 } 2444 2445 static int gpmc_remove(struct platform_device *pdev) 2446 { 2447 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2448 2449 gpmc_free_irq(gpmc); 2450 gpmc_mem_exit(); 2451 pm_runtime_put_sync(&pdev->dev); 2452 pm_runtime_disable(&pdev->dev); 2453 2454 return 0; 2455 } 2456 2457 #ifdef CONFIG_PM_SLEEP 2458 static int gpmc_suspend(struct device *dev) 2459 { 2460 omap3_gpmc_save_context(); 2461 pm_runtime_put_sync(dev); 2462 return 0; 2463 } 2464 2465 static int gpmc_resume(struct device *dev) 2466 { 2467 pm_runtime_get_sync(dev); 2468 omap3_gpmc_restore_context(); 2469 return 0; 2470 } 2471 #endif 2472 2473 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); 2474 2475 static struct platform_driver gpmc_driver = { 2476 .probe = gpmc_probe, 2477 .remove = gpmc_remove, 2478 .driver = { 2479 .name = DEVICE_NAME, 2480 .of_match_table = of_match_ptr(gpmc_dt_ids), 2481 .pm = &gpmc_pm_ops, 2482 }, 2483 }; 2484 2485 static __init int gpmc_init(void) 2486 { 2487 return platform_driver_register(&gpmc_driver); 2488 } 2489 postcore_initcall(gpmc_init); 2490 2491 static struct omap3_gpmc_regs gpmc_context; 2492 2493 void omap3_gpmc_save_context(void) 2494 { 2495 int i; 2496 2497 if (!gpmc_base) 2498 return; 2499 2500 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 2501 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); 2502 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); 2503 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); 2504 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 2505 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 2506 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 2507 for (i = 0; i < gpmc_cs_num; i++) { 2508 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 2509 if (gpmc_context.cs_context[i].is_valid) { 2510 gpmc_context.cs_context[i].config1 = 2511 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); 2512 gpmc_context.cs_context[i].config2 = 2513 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); 2514 gpmc_context.cs_context[i].config3 = 2515 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); 2516 gpmc_context.cs_context[i].config4 = 2517 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); 2518 gpmc_context.cs_context[i].config5 = 2519 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); 2520 gpmc_context.cs_context[i].config6 = 2521 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); 2522 gpmc_context.cs_context[i].config7 = 2523 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); 2524 } 2525 } 2526 } 2527 2528 void omap3_gpmc_restore_context(void) 2529 { 2530 int i; 2531 2532 if (!gpmc_base) 2533 return; 2534 2535 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); 2536 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); 2537 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); 2538 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); 2539 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); 2540 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); 2541 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); 2542 for (i = 0; i < gpmc_cs_num; i++) { 2543 if (gpmc_context.cs_context[i].is_valid) { 2544 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 2545 gpmc_context.cs_context[i].config1); 2546 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, 2547 gpmc_context.cs_context[i].config2); 2548 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, 2549 gpmc_context.cs_context[i].config3); 2550 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, 2551 gpmc_context.cs_context[i].config4); 2552 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, 2553 gpmc_context.cs_context[i].config5); 2554 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, 2555 gpmc_context.cs_context[i].config6); 2556 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 2557 gpmc_context.cs_context[i].config7); 2558 } 2559 } 2560 } 2561