xref: /linux/drivers/memory/omap-gpmc.c (revision 511bd85485c676744a4c3a22f26965926891b131)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GPMC support functions
4  *
5  * Copyright (C) 2005-2006 Nokia Corporation
6  *
7  * Author: Juha Yrjola
8  *
9  * Copyright (C) 2009 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  */
12 #include <linux/irq.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/err.h>
16 #include <linux/clk.h>
17 #include <linux/ioport.h>
18 #include <linux/spinlock.h>
19 #include <linux/io.h>
20 #include <linux/gpio/driver.h>
21 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
22 #include <linux/gpio/machine.h>
23 #include <linux/interrupt.h>
24 #include <linux/irqdomain.h>
25 #include <linux/platform_device.h>
26 #include <linux/of.h>
27 #include <linux/of_address.h>
28 #include <linux/of_device.h>
29 #include <linux/of_platform.h>
30 #include <linux/omap-gpmc.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/sizes.h>
33 
34 #include <linux/platform_data/mtd-nand-omap2.h>
35 
36 #include <asm/mach-types.h>
37 
38 #define	DEVICE_NAME		"omap-gpmc"
39 
40 /* GPMC register offsets */
41 #define GPMC_REVISION		0x00
42 #define GPMC_SYSCONFIG		0x10
43 #define GPMC_SYSSTATUS		0x14
44 #define GPMC_IRQSTATUS		0x18
45 #define GPMC_IRQENABLE		0x1c
46 #define GPMC_TIMEOUT_CONTROL	0x40
47 #define GPMC_ERR_ADDRESS	0x44
48 #define GPMC_ERR_TYPE		0x48
49 #define GPMC_CONFIG		0x50
50 #define GPMC_STATUS		0x54
51 #define GPMC_PREFETCH_CONFIG1	0x1e0
52 #define GPMC_PREFETCH_CONFIG2	0x1e4
53 #define GPMC_PREFETCH_CONTROL	0x1ec
54 #define GPMC_PREFETCH_STATUS	0x1f0
55 #define GPMC_ECC_CONFIG		0x1f4
56 #define GPMC_ECC_CONTROL	0x1f8
57 #define GPMC_ECC_SIZE_CONFIG	0x1fc
58 #define GPMC_ECC1_RESULT        0x200
59 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
60 #define	GPMC_ECC_BCH_RESULT_1	0x244	/* not available on OMAP2 */
61 #define	GPMC_ECC_BCH_RESULT_2	0x248	/* not available on OMAP2 */
62 #define	GPMC_ECC_BCH_RESULT_3	0x24c	/* not available on OMAP2 */
63 #define	GPMC_ECC_BCH_RESULT_4	0x300	/* not available on OMAP2 */
64 #define	GPMC_ECC_BCH_RESULT_5	0x304	/* not available on OMAP2 */
65 #define	GPMC_ECC_BCH_RESULT_6	0x308	/* not available on OMAP2 */
66 
67 /* GPMC ECC control settings */
68 #define GPMC_ECC_CTRL_ECCCLEAR		0x100
69 #define GPMC_ECC_CTRL_ECCDISABLE	0x000
70 #define GPMC_ECC_CTRL_ECCREG1		0x001
71 #define GPMC_ECC_CTRL_ECCREG2		0x002
72 #define GPMC_ECC_CTRL_ECCREG3		0x003
73 #define GPMC_ECC_CTRL_ECCREG4		0x004
74 #define GPMC_ECC_CTRL_ECCREG5		0x005
75 #define GPMC_ECC_CTRL_ECCREG6		0x006
76 #define GPMC_ECC_CTRL_ECCREG7		0x007
77 #define GPMC_ECC_CTRL_ECCREG8		0x008
78 #define GPMC_ECC_CTRL_ECCREG9		0x009
79 
80 #define GPMC_CONFIG_LIMITEDADDRESS		BIT(1)
81 
82 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS	BIT(0)
83 
84 #define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)
85 #define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)
86 #define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)
87 #define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)
88 #define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)
89 #define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)
90 
91 #define GPMC_CS0_OFFSET		0x60
92 #define GPMC_CS_SIZE		0x30
93 #define	GPMC_BCH_SIZE		0x10
94 
95 /*
96  * The first 1MB of GPMC address space is typically mapped to
97  * the internal ROM. Never allocate the first page, to
98  * facilitate bug detection; even if we didn't boot from ROM.
99  * As GPMC minimum partition size is 16MB we can only start from
100  * there.
101  */
102 #define GPMC_MEM_START		0x1000000
103 #define GPMC_MEM_END		0x3FFFFFFF
104 
105 #define GPMC_CHUNK_SHIFT	24		/* 16 MB */
106 #define GPMC_SECTION_SHIFT	28		/* 128 MB */
107 
108 #define CS_NUM_SHIFT		24
109 #define ENABLE_PREFETCH		(0x1 << 7)
110 #define DMA_MPU_MODE		2
111 
112 #define	GPMC_REVISION_MAJOR(l)		(((l) >> 4) & 0xf)
113 #define	GPMC_REVISION_MINOR(l)		((l) & 0xf)
114 
115 #define	GPMC_HAS_WR_ACCESS		0x1
116 #define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
117 #define	GPMC_HAS_MUX_AAD		0x4
118 
119 #define GPMC_NR_WAITPINS		4
120 
121 #define GPMC_CS_CONFIG1		0x00
122 #define GPMC_CS_CONFIG2		0x04
123 #define GPMC_CS_CONFIG3		0x08
124 #define GPMC_CS_CONFIG4		0x0c
125 #define GPMC_CS_CONFIG5		0x10
126 #define GPMC_CS_CONFIG6		0x14
127 #define GPMC_CS_CONFIG7		0x18
128 #define GPMC_CS_NAND_COMMAND	0x1c
129 #define GPMC_CS_NAND_ADDRESS	0x20
130 #define GPMC_CS_NAND_DATA	0x24
131 
132 /* Control Commands */
133 #define GPMC_CONFIG_RDY_BSY	0x00000001
134 #define GPMC_CONFIG_DEV_SIZE	0x00000002
135 #define GPMC_CONFIG_DEV_TYPE	0x00000003
136 
137 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
138 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
139 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
140 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
141 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
142 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
143 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
144 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
145 /** CLKACTIVATIONTIME Max Ticks */
146 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
147 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
148 /** ATTACHEDDEVICEPAGELENGTH Max Value */
149 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
150 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
151 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
152 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
153 /** WAITMONITORINGTIME Max Ticks */
154 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
155 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
156 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
157 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
158 /** DEVICESIZE Max Value */
159 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
160 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
161 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
162 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
163 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
164 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
165 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
166 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
167 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
168 #define GPMC_CONFIG7_CSVALID		(1 << 6)
169 
170 #define GPMC_CONFIG7_BASEADDRESS_MASK	0x3f
171 #define GPMC_CONFIG7_CSVALID_MASK	BIT(6)
172 #define GPMC_CONFIG7_MASKADDRESS_OFFSET	8
173 #define GPMC_CONFIG7_MASKADDRESS_MASK	(0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
174 /* All CONFIG7 bits except reserved bits */
175 #define GPMC_CONFIG7_MASK		(GPMC_CONFIG7_BASEADDRESS_MASK | \
176 					 GPMC_CONFIG7_CSVALID_MASK |     \
177 					 GPMC_CONFIG7_MASKADDRESS_MASK)
178 
179 #define GPMC_DEVICETYPE_NOR		0
180 #define GPMC_DEVICETYPE_NAND		2
181 #define GPMC_CONFIG_WRITEPROTECT	0x00000010
182 #define WR_RD_PIN_MONITORING		0x00600000
183 
184 /* ECC commands */
185 #define GPMC_ECC_READ		0 /* Reset Hardware ECC for read */
186 #define GPMC_ECC_WRITE		1 /* Reset Hardware ECC for write */
187 #define GPMC_ECC_READSYN	2 /* Reset before syndrom is read back */
188 
189 #define	GPMC_NR_NAND_IRQS	2 /* number of NAND specific IRQs */
190 
191 enum gpmc_clk_domain {
192 	GPMC_CD_FCLK,
193 	GPMC_CD_CLK
194 };
195 
196 struct gpmc_cs_data {
197 	const char *name;
198 
199 #define GPMC_CS_RESERVED	(1 << 0)
200 	u32 flags;
201 
202 	struct resource mem;
203 };
204 
205 /* Structure to save gpmc cs context */
206 struct gpmc_cs_config {
207 	u32 config1;
208 	u32 config2;
209 	u32 config3;
210 	u32 config4;
211 	u32 config5;
212 	u32 config6;
213 	u32 config7;
214 	int is_valid;
215 };
216 
217 /*
218  * Structure to save/restore gpmc context
219  * to support core off on OMAP3
220  */
221 struct omap3_gpmc_regs {
222 	u32 sysconfig;
223 	u32 irqenable;
224 	u32 timeout_ctrl;
225 	u32 config;
226 	u32 prefetch_config1;
227 	u32 prefetch_config2;
228 	u32 prefetch_control;
229 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
230 };
231 
232 struct gpmc_device {
233 	struct device *dev;
234 	int irq;
235 	struct irq_chip irq_chip;
236 	struct gpio_chip gpio_chip;
237 	int nirqs;
238 };
239 
240 static struct irq_domain *gpmc_irq_domain;
241 
242 static struct resource	gpmc_mem_root;
243 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
244 static DEFINE_SPINLOCK(gpmc_mem_lock);
245 /* Define chip-selects as reserved by default until probe completes */
246 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
247 static unsigned int gpmc_nr_waitpins;
248 static resource_size_t phys_base, mem_size;
249 static unsigned int gpmc_capability;
250 static void __iomem *gpmc_base;
251 
252 static struct clk *gpmc_l3_clk;
253 
254 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
255 
256 static void gpmc_write_reg(int idx, u32 val)
257 {
258 	writel_relaxed(val, gpmc_base + idx);
259 }
260 
261 static u32 gpmc_read_reg(int idx)
262 {
263 	return readl_relaxed(gpmc_base + idx);
264 }
265 
266 void gpmc_cs_write_reg(int cs, int idx, u32 val)
267 {
268 	void __iomem *reg_addr;
269 
270 	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
271 	writel_relaxed(val, reg_addr);
272 }
273 
274 static u32 gpmc_cs_read_reg(int cs, int idx)
275 {
276 	void __iomem *reg_addr;
277 
278 	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
279 	return readl_relaxed(reg_addr);
280 }
281 
282 /* TODO: Add support for gpmc_fck to clock framework and use it */
283 static unsigned long gpmc_get_fclk_period(void)
284 {
285 	unsigned long rate = clk_get_rate(gpmc_l3_clk);
286 
287 	rate /= 1000;
288 	rate = 1000000000 / rate;	/* In picoseconds */
289 
290 	return rate;
291 }
292 
293 /**
294  * gpmc_get_clk_period - get period of selected clock domain in ps
295  * @cs: Chip Select Region.
296  * @cd: Clock Domain.
297  *
298  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
299  * prior to calling this function with GPMC_CD_CLK.
300  */
301 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
302 {
303 	unsigned long tick_ps = gpmc_get_fclk_period();
304 	u32 l;
305 	int div;
306 
307 	switch (cd) {
308 	case GPMC_CD_CLK:
309 		/* get current clk divider */
310 		l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
311 		div = (l & 0x03) + 1;
312 		/* get GPMC_CLK period */
313 		tick_ps *= div;
314 		break;
315 	case GPMC_CD_FCLK:
316 	default:
317 		break;
318 	}
319 
320 	return tick_ps;
321 }
322 
323 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
324 					 enum gpmc_clk_domain cd)
325 {
326 	unsigned long tick_ps;
327 
328 	/* Calculate in picosecs to yield more exact results */
329 	tick_ps = gpmc_get_clk_period(cs, cd);
330 
331 	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
332 }
333 
334 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
335 {
336 	return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
337 }
338 
339 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
340 {
341 	unsigned long tick_ps;
342 
343 	/* Calculate in picosecs to yield more exact results */
344 	tick_ps = gpmc_get_fclk_period();
345 
346 	return (time_ps + tick_ps - 1) / tick_ps;
347 }
348 
349 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
350 					 enum gpmc_clk_domain cd)
351 {
352 	return ticks * gpmc_get_clk_period(cs, cd) / 1000;
353 }
354 
355 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
356 {
357 	return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
358 }
359 
360 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
361 {
362 	return ticks * gpmc_get_fclk_period();
363 }
364 
365 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
366 {
367 	unsigned long ticks = gpmc_ps_to_ticks(time_ps);
368 
369 	return ticks * gpmc_get_fclk_period();
370 }
371 
372 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
373 {
374 	u32 l;
375 
376 	l = gpmc_cs_read_reg(cs, reg);
377 	if (value)
378 		l |= mask;
379 	else
380 		l &= ~mask;
381 	gpmc_cs_write_reg(cs, reg, l);
382 }
383 
384 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
385 {
386 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
387 			   GPMC_CONFIG1_TIME_PARA_GRAN,
388 			   p->time_para_granularity);
389 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
390 			   GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
391 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
392 			   GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
393 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
394 			   GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
395 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
396 			   GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
397 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
398 			   GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
399 			   p->cycle2cyclesamecsen);
400 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
401 			   GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
402 			   p->cycle2cyclediffcsen);
403 }
404 
405 #ifdef CONFIG_OMAP_GPMC_DEBUG
406 /**
407  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
408  * @cs:      Chip Select Region
409  * @reg:     GPMC_CS_CONFIGn register offset.
410  * @st_bit:  Start Bit
411  * @end_bit: End Bit. Must be >= @st_bit.
412  * @max:     Maximum parameter value (before optional @shift).
413  *           If 0, maximum is as high as @st_bit and @end_bit allow.
414  * @name:    DTS node name, w/o "gpmc,"
415  * @cd:      Clock Domain of timing parameter.
416  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
417  * @raw:     Raw Format Option.
418  *           raw format:  gpmc,name = <value>
419  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
420  *           Where x ns -- y ns result in the same tick value.
421  *           When @max is exceeded, "invalid" is printed inside comment.
422  * @noval:   Parameter values equal to 0 are not printed.
423  * @return:  Specified timing parameter (after optional @shift).
424  *
425  */
426 static int get_gpmc_timing_reg(
427 	/* timing specifiers */
428 	int cs, int reg, int st_bit, int end_bit, int max,
429 	const char *name, const enum gpmc_clk_domain cd,
430 	/* value transform */
431 	int shift,
432 	/* format specifiers */
433 	bool raw, bool noval)
434 {
435 	u32 l;
436 	int nr_bits;
437 	int mask;
438 	bool invalid;
439 
440 	l = gpmc_cs_read_reg(cs, reg);
441 	nr_bits = end_bit - st_bit + 1;
442 	mask = (1 << nr_bits) - 1;
443 	l = (l >> st_bit) & mask;
444 	if (!max)
445 		max = mask;
446 	invalid = l > max;
447 	if (shift)
448 		l = (shift << l);
449 	if (noval && (l == 0))
450 		return 0;
451 	if (!raw) {
452 		/* DTS tick format for timings in ns */
453 		unsigned int time_ns;
454 		unsigned int time_ns_min = 0;
455 
456 		if (l)
457 			time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
458 		time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
459 		pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
460 			name, time_ns, time_ns_min, time_ns, l,
461 			invalid ? "; invalid " : " ");
462 	} else {
463 		/* raw format */
464 		pr_info("gpmc,%s = <%u>;%s\n", name, l,
465 			invalid ? " /* invalid */" : "");
466 	}
467 
468 	return l;
469 }
470 
471 #define GPMC_PRINT_CONFIG(cs, config) \
472 	pr_info("cs%i %s: 0x%08x\n", cs, #config, \
473 		gpmc_cs_read_reg(cs, config))
474 #define GPMC_GET_RAW(reg, st, end, field) \
475 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
476 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
477 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
478 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
479 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
480 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
481 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
482 #define GPMC_GET_TICKS(reg, st, end, field) \
483 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
484 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
485 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
486 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
487 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
488 
489 static void gpmc_show_regs(int cs, const char *desc)
490 {
491 	pr_info("gpmc cs%i %s:\n", cs, desc);
492 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
493 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
494 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
495 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
496 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
497 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
498 }
499 
500 /*
501  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
502  * see commit c9fb809.
503  */
504 static void gpmc_cs_show_timings(int cs, const char *desc)
505 {
506 	gpmc_show_regs(cs, desc);
507 
508 	pr_info("gpmc cs%i access configuration:\n", cs);
509 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
510 	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
511 	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
512 			       GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
513 	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
514 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
515 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
516 	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
517 			       GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
518 			       "burst-length");
519 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
520 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
521 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
522 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
523 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
524 
525 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
526 
527 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
528 
529 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
530 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
531 
532 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
533 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
534 
535 	pr_info("gpmc cs%i timings configuration:\n", cs);
536 	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
537 	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
538 	GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
539 
540 	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
541 	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
542 	GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
543 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
544 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
545 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
546 				"adv-aad-mux-rd-off-ns");
547 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
548 				"adv-aad-mux-wr-off-ns");
549 	}
550 
551 	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
552 	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
553 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
554 		GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
555 		GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
556 	}
557 	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
558 	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
559 
560 	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
561 	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
562 	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
563 
564 	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
565 
566 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
567 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
568 
569 	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
570 			      GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
571 			      "wait-monitoring-ns", GPMC_CD_CLK);
572 	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
573 			      GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
574 			      "clk-activation-ns", GPMC_CD_FCLK);
575 
576 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
577 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
578 }
579 #else
580 static inline void gpmc_cs_show_timings(int cs, const char *desc)
581 {
582 }
583 #endif
584 
585 /**
586  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
587  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
588  * prior to calling this function with @cd equal to GPMC_CD_CLK.
589  *
590  * @cs:      Chip Select Region.
591  * @reg:     GPMC_CS_CONFIGn register offset.
592  * @st_bit:  Start Bit
593  * @end_bit: End Bit. Must be >= @st_bit.
594  * @max:     Maximum parameter value.
595  *           If 0, maximum is as high as @st_bit and @end_bit allow.
596  * @time:    Timing parameter in ns.
597  * @cd:      Timing parameter clock domain.
598  * @name:    Timing parameter name.
599  * @return:  0 on success, -1 on error.
600  */
601 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
602 			       int time, enum gpmc_clk_domain cd, const char *name)
603 {
604 	u32 l;
605 	int ticks, mask, nr_bits;
606 
607 	if (time == 0)
608 		ticks = 0;
609 	else
610 		ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
611 	nr_bits = end_bit - st_bit + 1;
612 	mask = (1 << nr_bits) - 1;
613 
614 	if (!max)
615 		max = mask;
616 
617 	if (ticks > max) {
618 		pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
619 		       __func__, cs, name, time, ticks, max);
620 
621 		return -1;
622 	}
623 
624 	l = gpmc_cs_read_reg(cs, reg);
625 #ifdef CONFIG_OMAP_GPMC_DEBUG
626 	pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
627 		cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
628 			(l >> st_bit) & mask, time);
629 #endif
630 	l &= ~(mask << st_bit);
631 	l |= ticks << st_bit;
632 	gpmc_cs_write_reg(cs, reg, l);
633 
634 	return 0;
635 }
636 
637 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
638 	if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
639 	    t->field, (cd), #field) < 0)                       \
640 		return -1
641 
642 #define GPMC_SET_ONE(reg, st, end, field) \
643 	GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
644 
645 /**
646  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
647  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
648  * read  --> don't sample bus too early
649  * write --> data is longer on bus
650  *
651  * Formula:
652  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
653  *                    / waitmonitoring_ticks)
654  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
655  * div <= 0 check.
656  *
657  * @wait_monitoring: WAITMONITORINGTIME in ns.
658  * @return:          -1 on failure to scale, else proper divider > 0.
659  */
660 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
661 {
662 	int div = gpmc_ns_to_ticks(wait_monitoring);
663 
664 	div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
665 	div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
666 
667 	if (div > 4)
668 		return -1;
669 	if (div <= 0)
670 		div = 1;
671 
672 	return div;
673 }
674 
675 /**
676  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
677  * @sync_clk: GPMC_CLK period in ps.
678  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
679  *            Else, returns -1.
680  */
681 int gpmc_calc_divider(unsigned int sync_clk)
682 {
683 	int div = gpmc_ps_to_ticks(sync_clk);
684 
685 	if (div > 4)
686 		return -1;
687 	if (div <= 0)
688 		div = 1;
689 
690 	return div;
691 }
692 
693 /**
694  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
695  * @cs:     Chip Select Region.
696  * @t:      GPMC timing parameters.
697  * @s:      GPMC timing settings.
698  * @return: 0 on success, -1 on error.
699  */
700 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
701 			const struct gpmc_settings *s)
702 {
703 	int div;
704 	u32 l;
705 
706 	div = gpmc_calc_divider(t->sync_clk);
707 	if (div < 0)
708 		return div;
709 
710 	/*
711 	 * See if we need to change the divider for waitmonitoringtime.
712 	 *
713 	 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
714 	 * pure asynchronous accesses, i.e. both read and write asynchronous.
715 	 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
716 	 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
717 	 *
718 	 * This statement must not change div to scale async WAITMONITORINGTIME
719 	 * to protect mixed synchronous and asynchronous accesses.
720 	 *
721 	 * We raise an error later if WAITMONITORINGTIME does not fit.
722 	 */
723 	if (!s->sync_read && !s->sync_write &&
724 	    (s->wait_on_read || s->wait_on_write)
725 	   ) {
726 		div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
727 		if (div < 0) {
728 			pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
729 			       __func__,
730 			       t->wait_monitoring
731 			       );
732 			return -1;
733 		}
734 	}
735 
736 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
737 	GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
738 	GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
739 
740 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
741 	GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
742 	GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
743 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
744 		GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
745 		GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
746 		GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
747 	}
748 
749 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
750 	GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
751 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
752 		GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
753 		GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
754 	}
755 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
756 	GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
757 
758 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
759 	GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
760 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
761 
762 	GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
763 
764 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
765 	GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
766 
767 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
768 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
769 	if (gpmc_capability & GPMC_HAS_WR_ACCESS)
770 		GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
771 
772 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
773 	l &= ~0x03;
774 	l |= (div - 1);
775 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
776 
777 	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
778 			    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
779 			    wait_monitoring, GPMC_CD_CLK);
780 	GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
781 			    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
782 			    clk_activation, GPMC_CD_FCLK);
783 
784 #ifdef CONFIG_OMAP_GPMC_DEBUG
785 	pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
786 			cs, (div * gpmc_get_fclk_period()) / 1000, div);
787 #endif
788 
789 	gpmc_cs_bool_timings(cs, &t->bool_timings);
790 	gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
791 
792 	return 0;
793 }
794 
795 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
796 {
797 	u32 l;
798 	u32 mask;
799 
800 	/*
801 	 * Ensure that base address is aligned on a
802 	 * boundary equal to or greater than size.
803 	 */
804 	if (base & (size - 1))
805 		return -EINVAL;
806 
807 	base >>= GPMC_CHUNK_SHIFT;
808 	mask = (1 << GPMC_SECTION_SHIFT) - size;
809 	mask >>= GPMC_CHUNK_SHIFT;
810 	mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
811 
812 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
813 	l &= ~GPMC_CONFIG7_MASK;
814 	l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
815 	l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
816 	l |= GPMC_CONFIG7_CSVALID;
817 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
818 
819 	return 0;
820 }
821 
822 static void gpmc_cs_enable_mem(int cs)
823 {
824 	u32 l;
825 
826 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
827 	l |= GPMC_CONFIG7_CSVALID;
828 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
829 }
830 
831 static void gpmc_cs_disable_mem(int cs)
832 {
833 	u32 l;
834 
835 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
836 	l &= ~GPMC_CONFIG7_CSVALID;
837 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
838 }
839 
840 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
841 {
842 	u32 l;
843 	u32 mask;
844 
845 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
846 	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
847 	mask = (l >> 8) & 0x0f;
848 	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
849 }
850 
851 static int gpmc_cs_mem_enabled(int cs)
852 {
853 	u32 l;
854 
855 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
856 	return l & GPMC_CONFIG7_CSVALID;
857 }
858 
859 static void gpmc_cs_set_reserved(int cs, int reserved)
860 {
861 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
862 
863 	gpmc->flags |= GPMC_CS_RESERVED;
864 }
865 
866 static bool gpmc_cs_reserved(int cs)
867 {
868 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
869 
870 	return gpmc->flags & GPMC_CS_RESERVED;
871 }
872 
873 static void gpmc_cs_set_name(int cs, const char *name)
874 {
875 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
876 
877 	gpmc->name = name;
878 }
879 
880 static const char *gpmc_cs_get_name(int cs)
881 {
882 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
883 
884 	return gpmc->name;
885 }
886 
887 static unsigned long gpmc_mem_align(unsigned long size)
888 {
889 	int order;
890 
891 	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
892 	order = GPMC_CHUNK_SHIFT - 1;
893 	do {
894 		size >>= 1;
895 		order++;
896 	} while (size);
897 	size = 1 << order;
898 	return size;
899 }
900 
901 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
902 {
903 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
904 	struct resource *res = &gpmc->mem;
905 	int r;
906 
907 	size = gpmc_mem_align(size);
908 	spin_lock(&gpmc_mem_lock);
909 	res->start = base;
910 	res->end = base + size - 1;
911 	r = request_resource(&gpmc_mem_root, res);
912 	spin_unlock(&gpmc_mem_lock);
913 
914 	return r;
915 }
916 
917 static int gpmc_cs_delete_mem(int cs)
918 {
919 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
920 	struct resource *res = &gpmc->mem;
921 	int r;
922 
923 	spin_lock(&gpmc_mem_lock);
924 	r = release_resource(res);
925 	res->start = 0;
926 	res->end = 0;
927 	spin_unlock(&gpmc_mem_lock);
928 
929 	return r;
930 }
931 
932 /**
933  * gpmc_cs_remap - remaps a chip-select physical base address
934  * @cs:		chip-select to remap
935  * @base:	physical base address to re-map chip-select to
936  *
937  * Re-maps a chip-select to a new physical base address specified by
938  * "base". Returns 0 on success and appropriate negative error code
939  * on failure.
940  */
941 static int gpmc_cs_remap(int cs, u32 base)
942 {
943 	int ret;
944 	u32 old_base, size;
945 
946 	if (cs > gpmc_cs_num) {
947 		pr_err("%s: requested chip-select is disabled\n", __func__);
948 		return -ENODEV;
949 	}
950 
951 	/*
952 	 * Make sure we ignore any device offsets from the GPMC partition
953 	 * allocated for the chip select and that the new base confirms
954 	 * to the GPMC 16MB minimum granularity.
955 	 */
956 	base &= ~(SZ_16M - 1);
957 
958 	gpmc_cs_get_memconf(cs, &old_base, &size);
959 	if (base == old_base)
960 		return 0;
961 
962 	ret = gpmc_cs_delete_mem(cs);
963 	if (ret < 0)
964 		return ret;
965 
966 	ret = gpmc_cs_insert_mem(cs, base, size);
967 	if (ret < 0)
968 		return ret;
969 
970 	ret = gpmc_cs_set_memconf(cs, base, size);
971 
972 	return ret;
973 }
974 
975 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
976 {
977 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
978 	struct resource *res = &gpmc->mem;
979 	int r = -1;
980 
981 	if (cs > gpmc_cs_num) {
982 		pr_err("%s: requested chip-select is disabled\n", __func__);
983 		return -ENODEV;
984 	}
985 	size = gpmc_mem_align(size);
986 	if (size > (1 << GPMC_SECTION_SHIFT))
987 		return -ENOMEM;
988 
989 	spin_lock(&gpmc_mem_lock);
990 	if (gpmc_cs_reserved(cs)) {
991 		r = -EBUSY;
992 		goto out;
993 	}
994 	if (gpmc_cs_mem_enabled(cs))
995 		r = adjust_resource(res, res->start & ~(size - 1), size);
996 	if (r < 0)
997 		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
998 				      size, NULL, NULL);
999 	if (r < 0)
1000 		goto out;
1001 
1002 	/* Disable CS while changing base address and size mask */
1003 	gpmc_cs_disable_mem(cs);
1004 
1005 	r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1006 	if (r < 0) {
1007 		release_resource(res);
1008 		goto out;
1009 	}
1010 
1011 	/* Enable CS */
1012 	gpmc_cs_enable_mem(cs);
1013 	*base = res->start;
1014 	gpmc_cs_set_reserved(cs, 1);
1015 out:
1016 	spin_unlock(&gpmc_mem_lock);
1017 	return r;
1018 }
1019 EXPORT_SYMBOL(gpmc_cs_request);
1020 
1021 void gpmc_cs_free(int cs)
1022 {
1023 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1024 	struct resource *res = &gpmc->mem;
1025 
1026 	spin_lock(&gpmc_mem_lock);
1027 	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1028 		printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1029 		BUG();
1030 		spin_unlock(&gpmc_mem_lock);
1031 		return;
1032 	}
1033 	gpmc_cs_disable_mem(cs);
1034 	if (res->flags)
1035 		release_resource(res);
1036 	gpmc_cs_set_reserved(cs, 0);
1037 	spin_unlock(&gpmc_mem_lock);
1038 }
1039 EXPORT_SYMBOL(gpmc_cs_free);
1040 
1041 /**
1042  * gpmc_configure - write request to configure gpmc
1043  * @cmd: command type
1044  * @wval: value to write
1045  * @return status of the operation
1046  */
1047 int gpmc_configure(int cmd, int wval)
1048 {
1049 	u32 regval;
1050 
1051 	switch (cmd) {
1052 	case GPMC_CONFIG_WP:
1053 		regval = gpmc_read_reg(GPMC_CONFIG);
1054 		if (wval)
1055 			regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1056 		else
1057 			regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1058 		gpmc_write_reg(GPMC_CONFIG, regval);
1059 		break;
1060 
1061 	default:
1062 		pr_err("%s: command not supported\n", __func__);
1063 		return -EINVAL;
1064 	}
1065 
1066 	return 0;
1067 }
1068 EXPORT_SYMBOL(gpmc_configure);
1069 
1070 static bool gpmc_nand_writebuffer_empty(void)
1071 {
1072 	if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1073 		return true;
1074 
1075 	return false;
1076 }
1077 
1078 static struct gpmc_nand_ops nand_ops = {
1079 	.nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1080 };
1081 
1082 /**
1083  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1084  * @reg: the GPMC NAND register map exclusive for NAND use.
1085  * @cs: GPMC chip select number on which the NAND sits. The
1086  *      register map returned will be specific to this chip select.
1087  *
1088  * Returns NULL on error e.g. invalid cs.
1089  */
1090 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1091 {
1092 	int i;
1093 
1094 	if (cs >= gpmc_cs_num)
1095 		return NULL;
1096 
1097 	reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1098 				GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1099 	reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1100 				GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1101 	reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1102 				GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1103 	reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1104 	reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1105 	reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1106 	reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1107 	reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1108 	reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1109 	reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1110 	reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1111 
1112 	for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1113 		reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1114 					   GPMC_BCH_SIZE * i;
1115 		reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1116 					   GPMC_BCH_SIZE * i;
1117 		reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1118 					   GPMC_BCH_SIZE * i;
1119 		reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1120 					   GPMC_BCH_SIZE * i;
1121 		reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1122 					   i * GPMC_BCH_SIZE;
1123 		reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1124 					   i * GPMC_BCH_SIZE;
1125 		reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1126 					   i * GPMC_BCH_SIZE;
1127 	}
1128 
1129 	return &nand_ops;
1130 }
1131 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1132 
1133 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1134 						struct gpmc_settings *s,
1135 						int freq, int latency)
1136 {
1137 	struct gpmc_device_timings dev_t;
1138 	const int t_cer  = 15;
1139 	const int t_avdp = 12;
1140 	const int t_cez  = 20; /* max of t_cez, t_oez */
1141 	const int t_wpl  = 40;
1142 	const int t_wph  = 30;
1143 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1144 
1145 	switch (freq) {
1146 	case 104:
1147 		min_gpmc_clk_period = 9600; /* 104 MHz */
1148 		t_ces   = 3;
1149 		t_avds  = 4;
1150 		t_avdh  = 2;
1151 		t_ach   = 3;
1152 		t_aavdh = 6;
1153 		t_rdyo  = 6;
1154 		break;
1155 	case 83:
1156 		min_gpmc_clk_period = 12000; /* 83 MHz */
1157 		t_ces   = 5;
1158 		t_avds  = 4;
1159 		t_avdh  = 2;
1160 		t_ach   = 6;
1161 		t_aavdh = 6;
1162 		t_rdyo  = 9;
1163 		break;
1164 	case 66:
1165 		min_gpmc_clk_period = 15000; /* 66 MHz */
1166 		t_ces   = 6;
1167 		t_avds  = 5;
1168 		t_avdh  = 2;
1169 		t_ach   = 6;
1170 		t_aavdh = 6;
1171 		t_rdyo  = 11;
1172 		break;
1173 	default:
1174 		min_gpmc_clk_period = 18500; /* 54 MHz */
1175 		t_ces   = 7;
1176 		t_avds  = 7;
1177 		t_avdh  = 7;
1178 		t_ach   = 9;
1179 		t_aavdh = 7;
1180 		t_rdyo  = 15;
1181 		break;
1182 	}
1183 
1184 	/* Set synchronous read timings */
1185 	memset(&dev_t, 0, sizeof(dev_t));
1186 
1187 	if (!s->sync_write) {
1188 		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1189 		dev_t.t_wpl = t_wpl * 1000;
1190 		dev_t.t_wph = t_wph * 1000;
1191 		dev_t.t_aavdh = t_aavdh * 1000;
1192 	}
1193 	dev_t.ce_xdelay = true;
1194 	dev_t.avd_xdelay = true;
1195 	dev_t.oe_xdelay = true;
1196 	dev_t.we_xdelay = true;
1197 	dev_t.clk = min_gpmc_clk_period;
1198 	dev_t.t_bacc = dev_t.clk;
1199 	dev_t.t_ces = t_ces * 1000;
1200 	dev_t.t_avds = t_avds * 1000;
1201 	dev_t.t_avdh = t_avdh * 1000;
1202 	dev_t.t_ach = t_ach * 1000;
1203 	dev_t.cyc_iaa = (latency + 1);
1204 	dev_t.t_cez_r = t_cez * 1000;
1205 	dev_t.t_cez_w = dev_t.t_cez_r;
1206 	dev_t.cyc_aavdh_oe = 1;
1207 	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1208 
1209 	gpmc_calc_timings(t, s, &dev_t);
1210 }
1211 
1212 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1213 				  int latency,
1214 				  struct gpmc_onenand_info *info)
1215 {
1216 	int ret;
1217 	struct gpmc_timings gpmc_t;
1218 	struct gpmc_settings gpmc_s;
1219 
1220 	gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1221 
1222 	info->sync_read = gpmc_s.sync_read;
1223 	info->sync_write = gpmc_s.sync_write;
1224 	info->burst_len = gpmc_s.burst_len;
1225 
1226 	if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1227 		return 0;
1228 
1229 	gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1230 
1231 	ret = gpmc_cs_program_settings(cs, &gpmc_s);
1232 	if (ret < 0)
1233 		return ret;
1234 
1235 	return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1236 }
1237 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1238 
1239 int gpmc_get_client_irq(unsigned int irq_config)
1240 {
1241 	if (!gpmc_irq_domain) {
1242 		pr_warn("%s called before GPMC IRQ domain available\n",
1243 			__func__);
1244 		return 0;
1245 	}
1246 
1247 	/* we restrict this to NAND IRQs only */
1248 	if (irq_config >= GPMC_NR_NAND_IRQS)
1249 		return 0;
1250 
1251 	return irq_create_mapping(gpmc_irq_domain, irq_config);
1252 }
1253 
1254 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1255 {
1256 	u32 regval;
1257 
1258 	/* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1259 	if (hwirq >= GPMC_NR_NAND_IRQS)
1260 		hwirq += 8 - GPMC_NR_NAND_IRQS;
1261 
1262 	regval = gpmc_read_reg(GPMC_IRQENABLE);
1263 	if (endis)
1264 		regval |= BIT(hwirq);
1265 	else
1266 		regval &= ~BIT(hwirq);
1267 	gpmc_write_reg(GPMC_IRQENABLE, regval);
1268 
1269 	return 0;
1270 }
1271 
1272 static void gpmc_irq_disable(struct irq_data *p)
1273 {
1274 	gpmc_irq_endis(p->hwirq, false);
1275 }
1276 
1277 static void gpmc_irq_enable(struct irq_data *p)
1278 {
1279 	gpmc_irq_endis(p->hwirq, true);
1280 }
1281 
1282 static void gpmc_irq_mask(struct irq_data *d)
1283 {
1284 	gpmc_irq_endis(d->hwirq, false);
1285 }
1286 
1287 static void gpmc_irq_unmask(struct irq_data *d)
1288 {
1289 	gpmc_irq_endis(d->hwirq, true);
1290 }
1291 
1292 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1293 {
1294 	u32 regval;
1295 
1296 	/* NAND IRQs polarity is not configurable */
1297 	if (hwirq < GPMC_NR_NAND_IRQS)
1298 		return;
1299 
1300 	/* WAITPIN starts at BIT 8 */
1301 	hwirq += 8 - GPMC_NR_NAND_IRQS;
1302 
1303 	regval = gpmc_read_reg(GPMC_CONFIG);
1304 	if (rising_edge)
1305 		regval &= ~BIT(hwirq);
1306 	else
1307 		regval |= BIT(hwirq);
1308 
1309 	gpmc_write_reg(GPMC_CONFIG, regval);
1310 }
1311 
1312 static void gpmc_irq_ack(struct irq_data *d)
1313 {
1314 	unsigned int hwirq = d->hwirq;
1315 
1316 	/* skip reserved bits */
1317 	if (hwirq >= GPMC_NR_NAND_IRQS)
1318 		hwirq += 8 - GPMC_NR_NAND_IRQS;
1319 
1320 	/* Setting bit to 1 clears (or Acks) the interrupt */
1321 	gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1322 }
1323 
1324 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1325 {
1326 	/* can't set type for NAND IRQs */
1327 	if (d->hwirq < GPMC_NR_NAND_IRQS)
1328 		return -EINVAL;
1329 
1330 	/* We can support either rising or falling edge at a time */
1331 	if (trigger == IRQ_TYPE_EDGE_FALLING)
1332 		gpmc_irq_edge_config(d->hwirq, false);
1333 	else if (trigger == IRQ_TYPE_EDGE_RISING)
1334 		gpmc_irq_edge_config(d->hwirq, true);
1335 	else
1336 		return -EINVAL;
1337 
1338 	return 0;
1339 }
1340 
1341 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1342 			irq_hw_number_t hw)
1343 {
1344 	struct gpmc_device *gpmc = d->host_data;
1345 
1346 	irq_set_chip_data(virq, gpmc);
1347 	if (hw < GPMC_NR_NAND_IRQS) {
1348 		irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1349 		irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1350 					 handle_simple_irq);
1351 	} else {
1352 		irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1353 					 handle_edge_irq);
1354 	}
1355 
1356 	return 0;
1357 }
1358 
1359 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1360 	.map    = gpmc_irq_map,
1361 	.xlate  = irq_domain_xlate_twocell,
1362 };
1363 
1364 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1365 {
1366 	int hwirq, virq;
1367 	u32 regval, regvalx;
1368 	struct gpmc_device *gpmc = data;
1369 
1370 	regval = gpmc_read_reg(GPMC_IRQSTATUS);
1371 	regvalx = regval;
1372 
1373 	if (!regval)
1374 		return IRQ_NONE;
1375 
1376 	for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1377 		/* skip reserved status bits */
1378 		if (hwirq == GPMC_NR_NAND_IRQS)
1379 			regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1380 
1381 		if (regvalx & BIT(hwirq)) {
1382 			virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1383 			if (!virq) {
1384 				dev_warn(gpmc->dev,
1385 					 "spurious irq detected hwirq %d, virq %d\n",
1386 					 hwirq, virq);
1387 			}
1388 
1389 			generic_handle_irq(virq);
1390 		}
1391 	}
1392 
1393 	gpmc_write_reg(GPMC_IRQSTATUS, regval);
1394 
1395 	return IRQ_HANDLED;
1396 }
1397 
1398 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1399 {
1400 	u32 regval;
1401 	int rc;
1402 
1403 	/* Disable interrupts */
1404 	gpmc_write_reg(GPMC_IRQENABLE, 0);
1405 
1406 	/* clear interrupts */
1407 	regval = gpmc_read_reg(GPMC_IRQSTATUS);
1408 	gpmc_write_reg(GPMC_IRQSTATUS, regval);
1409 
1410 	gpmc->irq_chip.name = "gpmc";
1411 	gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1412 	gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1413 	gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1414 	gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1415 	gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1416 	gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1417 
1418 	gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1419 						gpmc->nirqs,
1420 						&gpmc_irq_domain_ops,
1421 						gpmc);
1422 	if (!gpmc_irq_domain) {
1423 		dev_err(gpmc->dev, "IRQ domain add failed\n");
1424 		return -ENODEV;
1425 	}
1426 
1427 	rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1428 	if (rc) {
1429 		dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1430 			gpmc->irq, rc);
1431 		irq_domain_remove(gpmc_irq_domain);
1432 		gpmc_irq_domain = NULL;
1433 	}
1434 
1435 	return rc;
1436 }
1437 
1438 static int gpmc_free_irq(struct gpmc_device *gpmc)
1439 {
1440 	int hwirq;
1441 
1442 	free_irq(gpmc->irq, gpmc);
1443 
1444 	for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1445 		irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1446 
1447 	irq_domain_remove(gpmc_irq_domain);
1448 	gpmc_irq_domain = NULL;
1449 
1450 	return 0;
1451 }
1452 
1453 static void gpmc_mem_exit(void)
1454 {
1455 	int cs;
1456 
1457 	for (cs = 0; cs < gpmc_cs_num; cs++) {
1458 		if (!gpmc_cs_mem_enabled(cs))
1459 			continue;
1460 		gpmc_cs_delete_mem(cs);
1461 	}
1462 }
1463 
1464 static void gpmc_mem_init(void)
1465 {
1466 	int cs;
1467 
1468 	gpmc_mem_root.start = GPMC_MEM_START;
1469 	gpmc_mem_root.end = GPMC_MEM_END;
1470 
1471 	/* Reserve all regions that has been set up by bootloader */
1472 	for (cs = 0; cs < gpmc_cs_num; cs++) {
1473 		u32 base, size;
1474 
1475 		if (!gpmc_cs_mem_enabled(cs))
1476 			continue;
1477 		gpmc_cs_get_memconf(cs, &base, &size);
1478 		if (gpmc_cs_insert_mem(cs, base, size)) {
1479 			pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1480 				__func__, cs, base, base + size);
1481 			gpmc_cs_disable_mem(cs);
1482 		}
1483 	}
1484 }
1485 
1486 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1487 {
1488 	u32 temp;
1489 	int div;
1490 
1491 	div = gpmc_calc_divider(sync_clk);
1492 	temp = gpmc_ps_to_ticks(time_ps);
1493 	temp = (temp + div - 1) / div;
1494 	return gpmc_ticks_to_ps(temp * div);
1495 }
1496 
1497 /* XXX: can the cycles be avoided ? */
1498 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1499 				       struct gpmc_device_timings *dev_t,
1500 				       bool mux)
1501 {
1502 	u32 temp;
1503 
1504 	/* adv_rd_off */
1505 	temp = dev_t->t_avdp_r;
1506 	/* XXX: mux check required ? */
1507 	if (mux) {
1508 		/* XXX: t_avdp not to be required for sync, only added for tusb
1509 		 * this indirectly necessitates requirement of t_avdp_r and
1510 		 * t_avdp_w instead of having a single t_avdp
1511 		 */
1512 		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_avdh);
1513 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1514 	}
1515 	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1516 
1517 	/* oe_on */
1518 	temp = dev_t->t_oeasu; /* XXX: remove this ? */
1519 	if (mux) {
1520 		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_ach);
1521 		temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1522 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1523 	}
1524 	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1525 
1526 	/* access */
1527 	/* XXX: any scope for improvement ?, by combining oe_on
1528 	 * and clk_activation, need to check whether
1529 	 * access = clk_activation + round to sync clk ?
1530 	 */
1531 	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);
1532 	temp += gpmc_t->clk_activation;
1533 	if (dev_t->cyc_oe)
1534 		temp = max_t(u32, temp, gpmc_t->oe_on +
1535 				gpmc_ticks_to_ps(dev_t->cyc_oe));
1536 	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1537 
1538 	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1539 	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1540 
1541 	/* rd_cycle */
1542 	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1543 	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1544 							gpmc_t->access;
1545 	/* XXX: barter t_ce_rdyz with t_cez_r ? */
1546 	if (dev_t->t_ce_rdyz)
1547 		temp = max_t(u32, temp,	gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1548 	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1549 
1550 	return 0;
1551 }
1552 
1553 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1554 					struct gpmc_device_timings *dev_t,
1555 					bool mux)
1556 {
1557 	u32 temp;
1558 
1559 	/* adv_wr_off */
1560 	temp = dev_t->t_avdp_w;
1561 	if (mux) {
1562 		temp = max_t(u32, temp,
1563 			gpmc_t->clk_activation + dev_t->t_avdh);
1564 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1565 	}
1566 	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1567 
1568 	/* wr_data_mux_bus */
1569 	temp = max_t(u32, dev_t->t_weasu,
1570 			gpmc_t->clk_activation + dev_t->t_rdyo);
1571 	/* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1572 	 * and in that case remember to handle we_on properly
1573 	 */
1574 	if (mux) {
1575 		temp = max_t(u32, temp,
1576 			gpmc_t->adv_wr_off + dev_t->t_aavdh);
1577 		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1578 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1579 	}
1580 	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1581 
1582 	/* we_on */
1583 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1584 		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1585 	else
1586 		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1587 
1588 	/* wr_access */
1589 	/* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1590 	gpmc_t->wr_access = gpmc_t->access;
1591 
1592 	/* we_off */
1593 	temp = gpmc_t->we_on + dev_t->t_wpl;
1594 	temp = max_t(u32, temp,
1595 			gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1596 	temp = max_t(u32, temp,
1597 		gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1598 	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1599 
1600 	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1601 							dev_t->t_wph);
1602 
1603 	/* wr_cycle */
1604 	temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1605 	temp += gpmc_t->wr_access;
1606 	/* XXX: barter t_ce_rdyz with t_cez_w ? */
1607 	if (dev_t->t_ce_rdyz)
1608 		temp = max_t(u32, temp,
1609 				 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1610 	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1611 
1612 	return 0;
1613 }
1614 
1615 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1616 					struct gpmc_device_timings *dev_t,
1617 					bool mux)
1618 {
1619 	u32 temp;
1620 
1621 	/* adv_rd_off */
1622 	temp = dev_t->t_avdp_r;
1623 	if (mux)
1624 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1625 	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1626 
1627 	/* oe_on */
1628 	temp = dev_t->t_oeasu;
1629 	if (mux)
1630 		temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1631 	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1632 
1633 	/* access */
1634 	temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1635 		     gpmc_t->oe_on + dev_t->t_oe);
1636 	temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1637 	temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1638 	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1639 
1640 	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1641 	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1642 
1643 	/* rd_cycle */
1644 	temp = max_t(u32, dev_t->t_rd_cycle,
1645 			gpmc_t->cs_rd_off + dev_t->t_cez_r);
1646 	temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1647 	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1648 
1649 	return 0;
1650 }
1651 
1652 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1653 					 struct gpmc_device_timings *dev_t,
1654 					 bool mux)
1655 {
1656 	u32 temp;
1657 
1658 	/* adv_wr_off */
1659 	temp = dev_t->t_avdp_w;
1660 	if (mux)
1661 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1662 	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1663 
1664 	/* wr_data_mux_bus */
1665 	temp = dev_t->t_weasu;
1666 	if (mux) {
1667 		temp = max_t(u32, temp,	gpmc_t->adv_wr_off + dev_t->t_aavdh);
1668 		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1669 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1670 	}
1671 	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1672 
1673 	/* we_on */
1674 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1675 		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1676 	else
1677 		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1678 
1679 	/* we_off */
1680 	temp = gpmc_t->we_on + dev_t->t_wpl;
1681 	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1682 
1683 	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1684 							dev_t->t_wph);
1685 
1686 	/* wr_cycle */
1687 	temp = max_t(u32, dev_t->t_wr_cycle,
1688 				gpmc_t->cs_wr_off + dev_t->t_cez_w);
1689 	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1690 
1691 	return 0;
1692 }
1693 
1694 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1695 			struct gpmc_device_timings *dev_t)
1696 {
1697 	u32 temp;
1698 
1699 	gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1700 						gpmc_get_fclk_period();
1701 
1702 	gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1703 					dev_t->t_bacc,
1704 					gpmc_t->sync_clk);
1705 
1706 	temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1707 	gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1708 
1709 	if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1710 		return 0;
1711 
1712 	if (dev_t->ce_xdelay)
1713 		gpmc_t->bool_timings.cs_extra_delay = true;
1714 	if (dev_t->avd_xdelay)
1715 		gpmc_t->bool_timings.adv_extra_delay = true;
1716 	if (dev_t->oe_xdelay)
1717 		gpmc_t->bool_timings.oe_extra_delay = true;
1718 	if (dev_t->we_xdelay)
1719 		gpmc_t->bool_timings.we_extra_delay = true;
1720 
1721 	return 0;
1722 }
1723 
1724 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1725 				    struct gpmc_device_timings *dev_t,
1726 				    bool sync)
1727 {
1728 	u32 temp;
1729 
1730 	/* cs_on */
1731 	gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1732 
1733 	/* adv_on */
1734 	temp = dev_t->t_avdasu;
1735 	if (dev_t->t_ce_avd)
1736 		temp = max_t(u32, temp,
1737 				gpmc_t->cs_on + dev_t->t_ce_avd);
1738 	gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1739 
1740 	if (sync)
1741 		gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1742 
1743 	return 0;
1744 }
1745 
1746 /*
1747  * TODO: remove this function once all peripherals are confirmed to
1748  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1749  * has to be modified to handle timings in ps instead of ns
1750  */
1751 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1752 {
1753 	t->cs_on /= 1000;
1754 	t->cs_rd_off /= 1000;
1755 	t->cs_wr_off /= 1000;
1756 	t->adv_on /= 1000;
1757 	t->adv_rd_off /= 1000;
1758 	t->adv_wr_off /= 1000;
1759 	t->we_on /= 1000;
1760 	t->we_off /= 1000;
1761 	t->oe_on /= 1000;
1762 	t->oe_off /= 1000;
1763 	t->page_burst_access /= 1000;
1764 	t->access /= 1000;
1765 	t->rd_cycle /= 1000;
1766 	t->wr_cycle /= 1000;
1767 	t->bus_turnaround /= 1000;
1768 	t->cycle2cycle_delay /= 1000;
1769 	t->wait_monitoring /= 1000;
1770 	t->clk_activation /= 1000;
1771 	t->wr_access /= 1000;
1772 	t->wr_data_mux_bus /= 1000;
1773 }
1774 
1775 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1776 		      struct gpmc_settings *gpmc_s,
1777 		      struct gpmc_device_timings *dev_t)
1778 {
1779 	bool mux = false, sync = false;
1780 
1781 	if (gpmc_s) {
1782 		mux = gpmc_s->mux_add_data ? true : false;
1783 		sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1784 	}
1785 
1786 	memset(gpmc_t, 0, sizeof(*gpmc_t));
1787 
1788 	gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1789 
1790 	if (gpmc_s && gpmc_s->sync_read)
1791 		gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1792 	else
1793 		gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1794 
1795 	if (gpmc_s && gpmc_s->sync_write)
1796 		gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1797 	else
1798 		gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1799 
1800 	/* TODO: remove, see function definition */
1801 	gpmc_convert_ps_to_ns(gpmc_t);
1802 
1803 	return 0;
1804 }
1805 
1806 /**
1807  * gpmc_cs_program_settings - programs non-timing related settings
1808  * @cs:		GPMC chip-select to program
1809  * @p:		pointer to GPMC settings structure
1810  *
1811  * Programs non-timing related settings for a GPMC chip-select, such as
1812  * bus-width, burst configuration, etc. Function should be called once
1813  * for each chip-select that is being used and must be called before
1814  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1815  * register will be initialised to zero by this function. Returns 0 on
1816  * success and appropriate negative error code on failure.
1817  */
1818 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1819 {
1820 	u32 config1;
1821 
1822 	if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1823 		pr_err("%s: invalid width %d!", __func__, p->device_width);
1824 		return -EINVAL;
1825 	}
1826 
1827 	/* Address-data multiplexing not supported for NAND devices */
1828 	if (p->device_nand && p->mux_add_data) {
1829 		pr_err("%s: invalid configuration!\n", __func__);
1830 		return -EINVAL;
1831 	}
1832 
1833 	if ((p->mux_add_data > GPMC_MUX_AD) ||
1834 	    ((p->mux_add_data == GPMC_MUX_AAD) &&
1835 	     !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1836 		pr_err("%s: invalid multiplex configuration!\n", __func__);
1837 		return -EINVAL;
1838 	}
1839 
1840 	/* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1841 	if (p->burst_read || p->burst_write) {
1842 		switch (p->burst_len) {
1843 		case GPMC_BURST_4:
1844 		case GPMC_BURST_8:
1845 		case GPMC_BURST_16:
1846 			break;
1847 		default:
1848 			pr_err("%s: invalid page/burst-length (%d)\n",
1849 			       __func__, p->burst_len);
1850 			return -EINVAL;
1851 		}
1852 	}
1853 
1854 	if (p->wait_pin > gpmc_nr_waitpins) {
1855 		pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1856 		return -EINVAL;
1857 	}
1858 
1859 	config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1860 
1861 	if (p->sync_read)
1862 		config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1863 	if (p->sync_write)
1864 		config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1865 	if (p->wait_on_read)
1866 		config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1867 	if (p->wait_on_write)
1868 		config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1869 	if (p->wait_on_read || p->wait_on_write)
1870 		config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1871 	if (p->device_nand)
1872 		config1	|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1873 	if (p->mux_add_data)
1874 		config1	|= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1875 	if (p->burst_read)
1876 		config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1877 	if (p->burst_write)
1878 		config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1879 	if (p->burst_read || p->burst_write) {
1880 		config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1881 		config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1882 	}
1883 
1884 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1885 
1886 	return 0;
1887 }
1888 
1889 #ifdef CONFIG_OF
1890 static const struct of_device_id gpmc_dt_ids[] = {
1891 	{ .compatible = "ti,omap2420-gpmc" },
1892 	{ .compatible = "ti,omap2430-gpmc" },
1893 	{ .compatible = "ti,omap3430-gpmc" },	/* omap3430 & omap3630 */
1894 	{ .compatible = "ti,omap4430-gpmc" },	/* omap4430 & omap4460 & omap543x */
1895 	{ .compatible = "ti,am3352-gpmc" },	/* am335x devices */
1896 	{ }
1897 };
1898 
1899 /**
1900  * gpmc_read_settings_dt - read gpmc settings from device-tree
1901  * @np:		pointer to device-tree node for a gpmc child device
1902  * @p:		pointer to gpmc settings structure
1903  *
1904  * Reads the GPMC settings for a GPMC child device from device-tree and
1905  * stores them in the GPMC settings structure passed. The GPMC settings
1906  * structure is initialised to zero by this function and so any
1907  * previously stored settings will be cleared.
1908  */
1909 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1910 {
1911 	memset(p, 0, sizeof(struct gpmc_settings));
1912 
1913 	p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1914 	p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1915 	of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1916 	of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1917 
1918 	if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1919 		p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1920 		p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1921 		p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1922 		if (!p->burst_read && !p->burst_write)
1923 			pr_warn("%s: page/burst-length set but not used!\n",
1924 				__func__);
1925 	}
1926 
1927 	if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1928 		p->wait_on_read = of_property_read_bool(np,
1929 							"gpmc,wait-on-read");
1930 		p->wait_on_write = of_property_read_bool(np,
1931 							 "gpmc,wait-on-write");
1932 		if (!p->wait_on_read && !p->wait_on_write)
1933 			pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1934 				 __func__);
1935 	}
1936 }
1937 
1938 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1939 						struct gpmc_timings *gpmc_t)
1940 {
1941 	struct gpmc_bool_timings *p;
1942 
1943 	if (!np || !gpmc_t)
1944 		return;
1945 
1946 	memset(gpmc_t, 0, sizeof(*gpmc_t));
1947 
1948 	/* minimum clock period for syncronous mode */
1949 	of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1950 
1951 	/* chip select timtings */
1952 	of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1953 	of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1954 	of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1955 
1956 	/* ADV signal timings */
1957 	of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1958 	of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1959 	of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1960 	of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1961 			     &gpmc_t->adv_aad_mux_on);
1962 	of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1963 			     &gpmc_t->adv_aad_mux_rd_off);
1964 	of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1965 			     &gpmc_t->adv_aad_mux_wr_off);
1966 
1967 	/* WE signal timings */
1968 	of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1969 	of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1970 
1971 	/* OE signal timings */
1972 	of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1973 	of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1974 	of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1975 			     &gpmc_t->oe_aad_mux_on);
1976 	of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1977 			     &gpmc_t->oe_aad_mux_off);
1978 
1979 	/* access and cycle timings */
1980 	of_property_read_u32(np, "gpmc,page-burst-access-ns",
1981 			     &gpmc_t->page_burst_access);
1982 	of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1983 	of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1984 	of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1985 	of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1986 			     &gpmc_t->bus_turnaround);
1987 	of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1988 			     &gpmc_t->cycle2cycle_delay);
1989 	of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1990 			     &gpmc_t->wait_monitoring);
1991 	of_property_read_u32(np, "gpmc,clk-activation-ns",
1992 			     &gpmc_t->clk_activation);
1993 
1994 	/* only applicable to OMAP3+ */
1995 	of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1996 	of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1997 			     &gpmc_t->wr_data_mux_bus);
1998 
1999 	/* bool timing parameters */
2000 	p = &gpmc_t->bool_timings;
2001 
2002 	p->cycle2cyclediffcsen =
2003 		of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2004 	p->cycle2cyclesamecsen =
2005 		of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2006 	p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2007 	p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2008 	p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2009 	p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2010 	p->time_para_granularity =
2011 		of_property_read_bool(np, "gpmc,time-para-granularity");
2012 }
2013 
2014 /**
2015  * gpmc_probe_generic_child - configures the gpmc for a child device
2016  * @pdev:	pointer to gpmc platform device
2017  * @child:	pointer to device-tree node for child device
2018  *
2019  * Allocates and configures a GPMC chip-select for a child device.
2020  * Returns 0 on success and appropriate negative error code on failure.
2021  */
2022 static int gpmc_probe_generic_child(struct platform_device *pdev,
2023 				struct device_node *child)
2024 {
2025 	struct gpmc_settings gpmc_s;
2026 	struct gpmc_timings gpmc_t;
2027 	struct resource res;
2028 	unsigned long base;
2029 	const char *name;
2030 	int ret, cs;
2031 	u32 val;
2032 	struct gpio_desc *waitpin_desc = NULL;
2033 	struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2034 
2035 	if (of_property_read_u32(child, "reg", &cs) < 0) {
2036 		dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2037 			child);
2038 		return -ENODEV;
2039 	}
2040 
2041 	if (of_address_to_resource(child, 0, &res) < 0) {
2042 		dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2043 			child);
2044 		return -ENODEV;
2045 	}
2046 
2047 	/*
2048 	 * Check if we have multiple instances of the same device
2049 	 * on a single chip select. If so, use the already initialized
2050 	 * timings.
2051 	 */
2052 	name = gpmc_cs_get_name(cs);
2053 	if (name && of_node_name_eq(child, name))
2054 		goto no_timings;
2055 
2056 	ret = gpmc_cs_request(cs, resource_size(&res), &base);
2057 	if (ret < 0) {
2058 		dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2059 		return ret;
2060 	}
2061 	gpmc_cs_set_name(cs, child->full_name);
2062 
2063 	gpmc_read_settings_dt(child, &gpmc_s);
2064 	gpmc_read_timings_dt(child, &gpmc_t);
2065 
2066 	/*
2067 	 * For some GPMC devices we still need to rely on the bootloader
2068 	 * timings because the devices can be connected via FPGA.
2069 	 * REVISIT: Add timing support from slls644g.pdf.
2070 	 */
2071 	if (!gpmc_t.cs_rd_off) {
2072 		WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2073 			cs);
2074 		gpmc_cs_show_timings(cs,
2075 				     "please add GPMC bootloader timings to .dts");
2076 		goto no_timings;
2077 	}
2078 
2079 	/* CS must be disabled while making changes to gpmc configuration */
2080 	gpmc_cs_disable_mem(cs);
2081 
2082 	/*
2083 	 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2084 	 * location in the gpmc address space. When booting with
2085 	 * device-tree we want the NOR flash to be mapped to the
2086 	 * location specified in the device-tree blob. So remap the
2087 	 * CS to this location. Once DT migration is complete should
2088 	 * just make gpmc_cs_request() map a specific address.
2089 	 */
2090 	ret = gpmc_cs_remap(cs, res.start);
2091 	if (ret < 0) {
2092 		dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2093 			cs, &res.start);
2094 		if (res.start < GPMC_MEM_START) {
2095 			dev_info(&pdev->dev,
2096 				 "GPMC CS %d start cannot be lesser than 0x%x\n",
2097 				 cs, GPMC_MEM_START);
2098 		} else if (res.end > GPMC_MEM_END) {
2099 			dev_info(&pdev->dev,
2100 				 "GPMC CS %d end cannot be greater than 0x%x\n",
2101 				 cs, GPMC_MEM_END);
2102 		}
2103 		goto err;
2104 	}
2105 
2106 	if (of_node_name_eq(child, "nand")) {
2107 		/* Warn about older DT blobs with no compatible property */
2108 		if (!of_property_read_bool(child, "compatible")) {
2109 			dev_warn(&pdev->dev,
2110 				 "Incompatible NAND node: missing compatible");
2111 			ret = -EINVAL;
2112 			goto err;
2113 		}
2114 	}
2115 
2116 	if (of_node_name_eq(child, "onenand")) {
2117 		/* Warn about older DT blobs with no compatible property */
2118 		if (!of_property_read_bool(child, "compatible")) {
2119 			dev_warn(&pdev->dev,
2120 				 "Incompatible OneNAND node: missing compatible");
2121 			ret = -EINVAL;
2122 			goto err;
2123 		}
2124 	}
2125 
2126 	if (of_device_is_compatible(child, "ti,omap2-nand")) {
2127 		/* NAND specific setup */
2128 		val = 8;
2129 		of_property_read_u32(child, "nand-bus-width", &val);
2130 		switch (val) {
2131 		case 8:
2132 			gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2133 			break;
2134 		case 16:
2135 			gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2136 			break;
2137 		default:
2138 			dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2139 				child);
2140 			ret = -EINVAL;
2141 			goto err;
2142 		}
2143 
2144 		/* disable write protect */
2145 		gpmc_configure(GPMC_CONFIG_WP, 0);
2146 		gpmc_s.device_nand = true;
2147 	} else {
2148 		ret = of_property_read_u32(child, "bank-width",
2149 					   &gpmc_s.device_width);
2150 		if (ret < 0 && !gpmc_s.device_width) {
2151 			dev_err(&pdev->dev,
2152 				"%pOF has no 'gpmc,device-width' property\n",
2153 				child);
2154 			goto err;
2155 		}
2156 	}
2157 
2158 	/* Reserve wait pin if it is required and valid */
2159 	if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2160 		unsigned int wait_pin = gpmc_s.wait_pin;
2161 
2162 		waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2163 							 wait_pin, "WAITPIN",
2164 							 GPIO_ACTIVE_HIGH,
2165 							 GPIOD_IN);
2166 		if (IS_ERR(waitpin_desc)) {
2167 			dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2168 			ret = PTR_ERR(waitpin_desc);
2169 			goto err;
2170 		}
2171 	}
2172 
2173 	gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2174 
2175 	ret = gpmc_cs_program_settings(cs, &gpmc_s);
2176 	if (ret < 0)
2177 		goto err_cs;
2178 
2179 	ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2180 	if (ret) {
2181 		dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2182 			child);
2183 		goto err_cs;
2184 	}
2185 
2186 	/* Clear limited address i.e. enable A26-A11 */
2187 	val = gpmc_read_reg(GPMC_CONFIG);
2188 	val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2189 	gpmc_write_reg(GPMC_CONFIG, val);
2190 
2191 	/* Enable CS region */
2192 	gpmc_cs_enable_mem(cs);
2193 
2194 no_timings:
2195 
2196 	/* create platform device, NULL on error or when disabled */
2197 	if (!of_platform_device_create(child, NULL, &pdev->dev))
2198 		goto err_child_fail;
2199 
2200 	/* is child a common bus? */
2201 	if (of_match_node(of_default_bus_match_table, child))
2202 		/* create children and other common bus children */
2203 		if (of_platform_default_populate(child, NULL, &pdev->dev))
2204 			goto err_child_fail;
2205 
2206 	return 0;
2207 
2208 err_child_fail:
2209 
2210 	dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2211 	ret = -ENODEV;
2212 
2213 err_cs:
2214 	gpiochip_free_own_desc(waitpin_desc);
2215 err:
2216 	gpmc_cs_free(cs);
2217 
2218 	return ret;
2219 }
2220 
2221 static int gpmc_probe_dt(struct platform_device *pdev)
2222 {
2223 	int ret;
2224 	const struct of_device_id *of_id =
2225 		of_match_device(gpmc_dt_ids, &pdev->dev);
2226 
2227 	if (!of_id)
2228 		return 0;
2229 
2230 	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2231 				   &gpmc_cs_num);
2232 	if (ret < 0) {
2233 		pr_err("%s: number of chip-selects not defined\n", __func__);
2234 		return ret;
2235 	} else if (gpmc_cs_num < 1) {
2236 		pr_err("%s: all chip-selects are disabled\n", __func__);
2237 		return -EINVAL;
2238 	} else if (gpmc_cs_num > GPMC_CS_NUM) {
2239 		pr_err("%s: number of supported chip-selects cannot be > %d\n",
2240 					 __func__, GPMC_CS_NUM);
2241 		return -EINVAL;
2242 	}
2243 
2244 	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2245 				   &gpmc_nr_waitpins);
2246 	if (ret < 0) {
2247 		pr_err("%s: number of wait pins not found!\n", __func__);
2248 		return ret;
2249 	}
2250 
2251 	return 0;
2252 }
2253 
2254 static void gpmc_probe_dt_children(struct platform_device *pdev)
2255 {
2256 	int ret;
2257 	struct device_node *child;
2258 
2259 	for_each_available_child_of_node(pdev->dev.of_node, child) {
2260 		ret = gpmc_probe_generic_child(pdev, child);
2261 		if (ret) {
2262 			dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2263 				child, ret);
2264 		}
2265 	}
2266 }
2267 #else
2268 static int gpmc_probe_dt(struct platform_device *pdev)
2269 {
2270 	return 0;
2271 }
2272 
2273 static void gpmc_probe_dt_children(struct platform_device *pdev)
2274 {
2275 }
2276 #endif /* CONFIG_OF */
2277 
2278 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2279 {
2280 	return 1;	/* we're input only */
2281 }
2282 
2283 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2284 				     unsigned int offset)
2285 {
2286 	return 0;	/* we're input only */
2287 }
2288 
2289 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2290 				      unsigned int offset, int value)
2291 {
2292 	return -EINVAL;	/* we're input only */
2293 }
2294 
2295 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2296 			  int value)
2297 {
2298 }
2299 
2300 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2301 {
2302 	u32 reg;
2303 
2304 	offset += 8;
2305 
2306 	reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2307 
2308 	return !!reg;
2309 }
2310 
2311 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2312 {
2313 	int ret;
2314 
2315 	gpmc->gpio_chip.parent = gpmc->dev;
2316 	gpmc->gpio_chip.owner = THIS_MODULE;
2317 	gpmc->gpio_chip.label = DEVICE_NAME;
2318 	gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2319 	gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2320 	gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2321 	gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2322 	gpmc->gpio_chip.set = gpmc_gpio_set;
2323 	gpmc->gpio_chip.get = gpmc_gpio_get;
2324 	gpmc->gpio_chip.base = -1;
2325 
2326 	ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2327 	if (ret < 0) {
2328 		dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2329 		return ret;
2330 	}
2331 
2332 	return 0;
2333 }
2334 
2335 static int gpmc_probe(struct platform_device *pdev)
2336 {
2337 	int rc;
2338 	u32 l;
2339 	struct resource *res;
2340 	struct gpmc_device *gpmc;
2341 
2342 	gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2343 	if (!gpmc)
2344 		return -ENOMEM;
2345 
2346 	gpmc->dev = &pdev->dev;
2347 	platform_set_drvdata(pdev, gpmc);
2348 
2349 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2350 	if (res == NULL)
2351 		return -ENOENT;
2352 
2353 	phys_base = res->start;
2354 	mem_size = resource_size(res);
2355 
2356 	gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2357 	if (IS_ERR(gpmc_base))
2358 		return PTR_ERR(gpmc_base);
2359 
2360 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2361 	if (!res) {
2362 		dev_err(&pdev->dev, "Failed to get resource: irq\n");
2363 		return -ENOENT;
2364 	}
2365 
2366 	gpmc->irq = res->start;
2367 
2368 	gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2369 	if (IS_ERR(gpmc_l3_clk)) {
2370 		dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2371 		return PTR_ERR(gpmc_l3_clk);
2372 	}
2373 
2374 	if (!clk_get_rate(gpmc_l3_clk)) {
2375 		dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2376 		return -EINVAL;
2377 	}
2378 
2379 	if (pdev->dev.of_node) {
2380 		rc = gpmc_probe_dt(pdev);
2381 		if (rc)
2382 			return rc;
2383 	} else {
2384 		gpmc_cs_num = GPMC_CS_NUM;
2385 		gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2386 	}
2387 
2388 	pm_runtime_enable(&pdev->dev);
2389 	pm_runtime_get_sync(&pdev->dev);
2390 
2391 	l = gpmc_read_reg(GPMC_REVISION);
2392 
2393 	/*
2394 	 * FIXME: Once device-tree migration is complete the below flags
2395 	 * should be populated based upon the device-tree compatible
2396 	 * string. For now just use the IP revision. OMAP3+ devices have
2397 	 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2398 	 * devices support the addr-addr-data multiplex protocol.
2399 	 *
2400 	 * GPMC IP revisions:
2401 	 * - OMAP24xx			= 2.0
2402 	 * - OMAP3xxx			= 5.0
2403 	 * - OMAP44xx/54xx/AM335x	= 6.0
2404 	 */
2405 	if (GPMC_REVISION_MAJOR(l) > 0x4)
2406 		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2407 	if (GPMC_REVISION_MAJOR(l) > 0x5)
2408 		gpmc_capability |= GPMC_HAS_MUX_AAD;
2409 	dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2410 		 GPMC_REVISION_MINOR(l));
2411 
2412 	gpmc_mem_init();
2413 	rc = gpmc_gpio_init(gpmc);
2414 	if (rc)
2415 		goto gpio_init_failed;
2416 
2417 	gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2418 	rc = gpmc_setup_irq(gpmc);
2419 	if (rc) {
2420 		dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2421 		goto gpio_init_failed;
2422 	}
2423 
2424 	gpmc_probe_dt_children(pdev);
2425 
2426 	return 0;
2427 
2428 gpio_init_failed:
2429 	gpmc_mem_exit();
2430 	pm_runtime_put_sync(&pdev->dev);
2431 	pm_runtime_disable(&pdev->dev);
2432 
2433 	return rc;
2434 }
2435 
2436 static int gpmc_remove(struct platform_device *pdev)
2437 {
2438 	struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2439 
2440 	gpmc_free_irq(gpmc);
2441 	gpmc_mem_exit();
2442 	pm_runtime_put_sync(&pdev->dev);
2443 	pm_runtime_disable(&pdev->dev);
2444 
2445 	return 0;
2446 }
2447 
2448 #ifdef CONFIG_PM_SLEEP
2449 static int gpmc_suspend(struct device *dev)
2450 {
2451 	omap3_gpmc_save_context();
2452 	pm_runtime_put_sync(dev);
2453 	return 0;
2454 }
2455 
2456 static int gpmc_resume(struct device *dev)
2457 {
2458 	pm_runtime_get_sync(dev);
2459 	omap3_gpmc_restore_context();
2460 	return 0;
2461 }
2462 #endif
2463 
2464 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2465 
2466 static struct platform_driver gpmc_driver = {
2467 	.probe		= gpmc_probe,
2468 	.remove		= gpmc_remove,
2469 	.driver		= {
2470 		.name	= DEVICE_NAME,
2471 		.of_match_table = of_match_ptr(gpmc_dt_ids),
2472 		.pm	= &gpmc_pm_ops,
2473 	},
2474 };
2475 
2476 static __init int gpmc_init(void)
2477 {
2478 	return platform_driver_register(&gpmc_driver);
2479 }
2480 postcore_initcall(gpmc_init);
2481 
2482 static struct omap3_gpmc_regs gpmc_context;
2483 
2484 void omap3_gpmc_save_context(void)
2485 {
2486 	int i;
2487 
2488 	if (!gpmc_base)
2489 		return;
2490 
2491 	gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2492 	gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2493 	gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2494 	gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2495 	gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2496 	gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2497 	gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2498 	for (i = 0; i < gpmc_cs_num; i++) {
2499 		gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2500 		if (gpmc_context.cs_context[i].is_valid) {
2501 			gpmc_context.cs_context[i].config1 =
2502 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2503 			gpmc_context.cs_context[i].config2 =
2504 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2505 			gpmc_context.cs_context[i].config3 =
2506 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2507 			gpmc_context.cs_context[i].config4 =
2508 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2509 			gpmc_context.cs_context[i].config5 =
2510 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2511 			gpmc_context.cs_context[i].config6 =
2512 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2513 			gpmc_context.cs_context[i].config7 =
2514 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2515 		}
2516 	}
2517 }
2518 
2519 void omap3_gpmc_restore_context(void)
2520 {
2521 	int i;
2522 
2523 	if (!gpmc_base)
2524 		return;
2525 
2526 	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2527 	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2528 	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2529 	gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2530 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2531 	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2532 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2533 	for (i = 0; i < gpmc_cs_num; i++) {
2534 		if (gpmc_context.cs_context[i].is_valid) {
2535 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2536 				gpmc_context.cs_context[i].config1);
2537 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2538 				gpmc_context.cs_context[i].config2);
2539 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2540 				gpmc_context.cs_context[i].config3);
2541 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2542 				gpmc_context.cs_context[i].config4);
2543 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2544 				gpmc_context.cs_context[i].config5);
2545 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2546 				gpmc_context.cs_context[i].config6);
2547 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2548 				gpmc_context.cs_context[i].config7);
2549 		}
2550 	}
2551 }
2552