xref: /linux/drivers/memory/omap-gpmc.c (revision 3ea5eb68b9d624935108b5e696859304edfac202)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GPMC support functions
4  *
5  * Copyright (C) 2005-2006 Nokia Corporation
6  *
7  * Author: Juha Yrjola
8  *
9  * Copyright (C) 2009 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  */
12 #include <linux/cleanup.h>
13 #include <linux/cpu_pm.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
25 #include <linux/gpio/machine.h>
26 #include <linux/interrupt.h>
27 #include <linux/irqdomain.h>
28 #include <linux/platform_device.h>
29 #include <linux/of.h>
30 #include <linux/of_address.h>
31 #include <linux/of_device.h>
32 #include <linux/of_platform.h>
33 #include <linux/omap-gpmc.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/sizes.h>
36 
37 #include <linux/platform_data/mtd-nand-omap2.h>
38 
39 #define	DEVICE_NAME		"omap-gpmc"
40 
41 /* GPMC register offsets */
42 #define GPMC_REVISION		0x00
43 #define GPMC_SYSCONFIG		0x10
44 #define GPMC_SYSSTATUS		0x14
45 #define GPMC_IRQSTATUS		0x18
46 #define GPMC_IRQENABLE		0x1c
47 #define GPMC_TIMEOUT_CONTROL	0x40
48 #define GPMC_ERR_ADDRESS	0x44
49 #define GPMC_ERR_TYPE		0x48
50 #define GPMC_CONFIG		0x50
51 #define GPMC_STATUS		0x54
52 #define GPMC_PREFETCH_CONFIG1	0x1e0
53 #define GPMC_PREFETCH_CONFIG2	0x1e4
54 #define GPMC_PREFETCH_CONTROL	0x1ec
55 #define GPMC_PREFETCH_STATUS	0x1f0
56 #define GPMC_ECC_CONFIG		0x1f4
57 #define GPMC_ECC_CONTROL	0x1f8
58 #define GPMC_ECC_SIZE_CONFIG	0x1fc
59 #define GPMC_ECC1_RESULT        0x200
60 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
61 #define	GPMC_ECC_BCH_RESULT_1	0x244	/* not available on OMAP2 */
62 #define	GPMC_ECC_BCH_RESULT_2	0x248	/* not available on OMAP2 */
63 #define	GPMC_ECC_BCH_RESULT_3	0x24c	/* not available on OMAP2 */
64 #define	GPMC_ECC_BCH_RESULT_4	0x300	/* not available on OMAP2 */
65 #define	GPMC_ECC_BCH_RESULT_5	0x304	/* not available on OMAP2 */
66 #define	GPMC_ECC_BCH_RESULT_6	0x308	/* not available on OMAP2 */
67 
68 /* GPMC ECC control settings */
69 #define GPMC_ECC_CTRL_ECCCLEAR		0x100
70 #define GPMC_ECC_CTRL_ECCDISABLE	0x000
71 #define GPMC_ECC_CTRL_ECCREG1		0x001
72 #define GPMC_ECC_CTRL_ECCREG2		0x002
73 #define GPMC_ECC_CTRL_ECCREG3		0x003
74 #define GPMC_ECC_CTRL_ECCREG4		0x004
75 #define GPMC_ECC_CTRL_ECCREG5		0x005
76 #define GPMC_ECC_CTRL_ECCREG6		0x006
77 #define GPMC_ECC_CTRL_ECCREG7		0x007
78 #define GPMC_ECC_CTRL_ECCREG8		0x008
79 #define GPMC_ECC_CTRL_ECCREG9		0x009
80 
81 #define GPMC_CONFIG_LIMITEDADDRESS		BIT(1)
82 
83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS	BIT(0)
84 
85 #define	GPMC_CONFIG2_CSEXTRADELAY		BIT(7)
86 #define	GPMC_CONFIG3_ADVEXTRADELAY		BIT(7)
87 #define	GPMC_CONFIG4_OEEXTRADELAY		BIT(7)
88 #define	GPMC_CONFIG4_WEEXTRADELAY		BIT(23)
89 #define	GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN	BIT(6)
90 #define	GPMC_CONFIG6_CYCLE2CYCLESAMECSEN	BIT(7)
91 
92 #define GPMC_CS0_OFFSET		0x60
93 #define GPMC_CS_SIZE		0x30
94 #define	GPMC_BCH_SIZE		0x10
95 
96 /*
97  * The first 1MB of GPMC address space is typically mapped to
98  * the internal ROM. Never allocate the first page, to
99  * facilitate bug detection; even if we didn't boot from ROM.
100  * As GPMC minimum partition size is 16MB we can only start from
101  * there.
102  */
103 #define GPMC_MEM_START		0x1000000
104 #define GPMC_MEM_END		0x3FFFFFFF
105 
106 #define GPMC_CHUNK_SHIFT	24		/* 16 MB */
107 #define GPMC_SECTION_SHIFT	28		/* 128 MB */
108 
109 #define CS_NUM_SHIFT		24
110 #define ENABLE_PREFETCH		(0x1 << 7)
111 #define DMA_MPU_MODE		2
112 
113 #define	GPMC_REVISION_MAJOR(l)		(((l) >> 4) & 0xf)
114 #define	GPMC_REVISION_MINOR(l)		((l) & 0xf)
115 
116 #define	GPMC_HAS_WR_ACCESS		0x1
117 #define	GPMC_HAS_WR_DATA_MUX_BUS	0x2
118 #define	GPMC_HAS_MUX_AAD		0x4
119 
120 #define GPMC_NR_WAITPINS		4
121 
122 #define GPMC_CS_CONFIG1		0x00
123 #define GPMC_CS_CONFIG2		0x04
124 #define GPMC_CS_CONFIG3		0x08
125 #define GPMC_CS_CONFIG4		0x0c
126 #define GPMC_CS_CONFIG5		0x10
127 #define GPMC_CS_CONFIG6		0x14
128 #define GPMC_CS_CONFIG7		0x18
129 #define GPMC_CS_NAND_COMMAND	0x1c
130 #define GPMC_CS_NAND_ADDRESS	0x20
131 #define GPMC_CS_NAND_DATA	0x24
132 
133 /* Control Commands */
134 #define GPMC_CONFIG_RDY_BSY	0x00000001
135 #define GPMC_CONFIG_DEV_SIZE	0x00000002
136 #define GPMC_CONFIG_DEV_TYPE	0x00000003
137 
138 #define GPMC_CONFIG_WAITPINPOLARITY(pin)	(BIT(pin) << 8)
139 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
140 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
141 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
142 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
143 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
144 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
145 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
146 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
147 /** CLKACTIVATIONTIME Max Ticks */
148 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
149 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
150 /** ATTACHEDDEVICEPAGELENGTH Max Value */
151 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
152 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
153 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
154 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
155 /** WAITMONITORINGTIME Max Ticks */
156 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
157 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
158 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
159 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
160 /** DEVICESIZE Max Value */
161 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
162 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
163 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
164 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
165 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
166 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
167 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
168 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
169 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
170 #define GPMC_CONFIG7_CSVALID		(1 << 6)
171 
172 #define GPMC_CONFIG7_BASEADDRESS_MASK	0x3f
173 #define GPMC_CONFIG7_CSVALID_MASK	BIT(6)
174 #define GPMC_CONFIG7_MASKADDRESS_OFFSET	8
175 #define GPMC_CONFIG7_MASKADDRESS_MASK	(0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
176 /* All CONFIG7 bits except reserved bits */
177 #define GPMC_CONFIG7_MASK		(GPMC_CONFIG7_BASEADDRESS_MASK | \
178 					 GPMC_CONFIG7_CSVALID_MASK |     \
179 					 GPMC_CONFIG7_MASKADDRESS_MASK)
180 
181 #define GPMC_DEVICETYPE_NOR		0
182 #define GPMC_DEVICETYPE_NAND		2
183 #define GPMC_CONFIG_WRITEPROTECT	0x00000010
184 #define WR_RD_PIN_MONITORING		0x00600000
185 
186 /* ECC commands */
187 #define GPMC_ECC_READ		0 /* Reset Hardware ECC for read */
188 #define GPMC_ECC_WRITE		1 /* Reset Hardware ECC for write */
189 #define GPMC_ECC_READSYN	2 /* Reset before syndrom is read back */
190 
191 #define	GPMC_NR_NAND_IRQS	2 /* number of NAND specific IRQs */
192 
193 enum gpmc_clk_domain {
194 	GPMC_CD_FCLK,
195 	GPMC_CD_CLK
196 };
197 
198 struct gpmc_cs_data {
199 	const char *name;
200 
201 #define GPMC_CS_RESERVED	(1 << 0)
202 	u32 flags;
203 
204 	struct resource mem;
205 };
206 
207 /* Structure to save gpmc cs context */
208 struct gpmc_cs_config {
209 	u32 config1;
210 	u32 config2;
211 	u32 config3;
212 	u32 config4;
213 	u32 config5;
214 	u32 config6;
215 	u32 config7;
216 	int is_valid;
217 };
218 
219 /*
220  * Structure to save/restore gpmc context
221  * to support core off on OMAP3
222  */
223 struct omap3_gpmc_regs {
224 	u32 sysconfig;
225 	u32 irqenable;
226 	u32 timeout_ctrl;
227 	u32 config;
228 	u32 prefetch_config1;
229 	u32 prefetch_config2;
230 	u32 prefetch_control;
231 	struct gpmc_cs_config cs_context[GPMC_CS_NUM];
232 };
233 
234 struct gpmc_waitpin {
235 	u32 pin;
236 	u32 polarity;
237 	struct gpio_desc *desc;
238 };
239 
240 struct gpmc_device {
241 	struct device *dev;
242 	int irq;
243 	struct irq_chip irq_chip;
244 	struct gpio_chip gpio_chip;
245 	struct notifier_block nb;
246 	struct omap3_gpmc_regs context;
247 	struct gpmc_waitpin *waitpins;
248 	int nirqs;
249 	unsigned int is_suspended:1;
250 	struct resource *data;
251 };
252 
253 static struct irq_domain *gpmc_irq_domain;
254 
255 static struct resource	gpmc_mem_root;
256 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
257 static DEFINE_SPINLOCK(gpmc_mem_lock);
258 /* Define chip-selects as reserved by default until probe completes */
259 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
260 static unsigned int gpmc_nr_waitpins;
261 static unsigned int gpmc_capability;
262 static void __iomem *gpmc_base;
263 
264 static struct clk *gpmc_l3_clk;
265 
266 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
267 
268 static void gpmc_write_reg(int idx, u32 val)
269 {
270 	writel_relaxed(val, gpmc_base + idx);
271 }
272 
273 static u32 gpmc_read_reg(int idx)
274 {
275 	return readl_relaxed(gpmc_base + idx);
276 }
277 
278 void gpmc_cs_write_reg(int cs, int idx, u32 val)
279 {
280 	void __iomem *reg_addr;
281 
282 	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
283 	writel_relaxed(val, reg_addr);
284 }
285 
286 static u32 gpmc_cs_read_reg(int cs, int idx)
287 {
288 	void __iomem *reg_addr;
289 
290 	reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
291 	return readl_relaxed(reg_addr);
292 }
293 
294 /* TODO: Add support for gpmc_fck to clock framework and use it */
295 static unsigned long gpmc_get_fclk_period(void)
296 {
297 	unsigned long rate = clk_get_rate(gpmc_l3_clk);
298 
299 	rate /= 1000;
300 	rate = 1000000000 / rate;	/* In picoseconds */
301 
302 	return rate;
303 }
304 
305 /**
306  * gpmc_get_clk_period - get period of selected clock domain in ps
307  * @cs: Chip Select Region.
308  * @cd: Clock Domain.
309  *
310  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
311  * prior to calling this function with GPMC_CD_CLK.
312  */
313 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
314 {
315 	unsigned long tick_ps = gpmc_get_fclk_period();
316 	u32 l;
317 	int div;
318 
319 	switch (cd) {
320 	case GPMC_CD_CLK:
321 		/* get current clk divider */
322 		l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
323 		div = (l & 0x03) + 1;
324 		/* get GPMC_CLK period */
325 		tick_ps *= div;
326 		break;
327 	case GPMC_CD_FCLK:
328 	default:
329 		break;
330 	}
331 
332 	return tick_ps;
333 }
334 
335 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
336 					 enum gpmc_clk_domain cd)
337 {
338 	unsigned long tick_ps;
339 
340 	/* Calculate in picosecs to yield more exact results */
341 	tick_ps = gpmc_get_clk_period(cs, cd);
342 
343 	return (time_ns * 1000 + tick_ps - 1) / tick_ps;
344 }
345 
346 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
347 {
348 	return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
349 }
350 
351 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
352 {
353 	unsigned long tick_ps;
354 
355 	/* Calculate in picosecs to yield more exact results */
356 	tick_ps = gpmc_get_fclk_period();
357 
358 	return (time_ps + tick_ps - 1) / tick_ps;
359 }
360 
361 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
362 					 enum gpmc_clk_domain cd)
363 {
364 	return ticks * gpmc_get_clk_period(cs, cd) / 1000;
365 }
366 
367 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
368 {
369 	return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
370 }
371 
372 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
373 {
374 	return ticks * gpmc_get_fclk_period();
375 }
376 
377 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
378 {
379 	unsigned long ticks = gpmc_ps_to_ticks(time_ps);
380 
381 	return ticks * gpmc_get_fclk_period();
382 }
383 
384 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
385 {
386 	u32 l;
387 
388 	l = gpmc_cs_read_reg(cs, reg);
389 	if (value)
390 		l |= mask;
391 	else
392 		l &= ~mask;
393 	gpmc_cs_write_reg(cs, reg, l);
394 }
395 
396 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
397 {
398 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
399 			   GPMC_CONFIG1_TIME_PARA_GRAN,
400 			   p->time_para_granularity);
401 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
402 			   GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
403 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
404 			   GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
405 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
406 			   GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
407 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
408 			   GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
409 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
410 			   GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
411 			   p->cycle2cyclesamecsen);
412 	gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
413 			   GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
414 			   p->cycle2cyclediffcsen);
415 }
416 
417 #ifdef CONFIG_OMAP_GPMC_DEBUG
418 /**
419  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
420  * @cs:      Chip Select Region
421  * @reg:     GPMC_CS_CONFIGn register offset.
422  * @st_bit:  Start Bit
423  * @end_bit: End Bit. Must be >= @st_bit.
424  * @max:     Maximum parameter value (before optional @shift).
425  *           If 0, maximum is as high as @st_bit and @end_bit allow.
426  * @name:    DTS node name, w/o "gpmc,"
427  * @cd:      Clock Domain of timing parameter.
428  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
429  * @raw:     Raw Format Option.
430  *           raw format:  gpmc,name = <value>
431  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
432  *           Where x ns -- y ns result in the same tick value.
433  *           When @max is exceeded, "invalid" is printed inside comment.
434  * @noval:   Parameter values equal to 0 are not printed.
435  * @return:  Specified timing parameter (after optional @shift).
436  *
437  */
438 static int get_gpmc_timing_reg(
439 	/* timing specifiers */
440 	int cs, int reg, int st_bit, int end_bit, int max,
441 	const char *name, const enum gpmc_clk_domain cd,
442 	/* value transform */
443 	int shift,
444 	/* format specifiers */
445 	bool raw, bool noval)
446 {
447 	u32 l;
448 	int nr_bits;
449 	int mask;
450 	bool invalid;
451 
452 	l = gpmc_cs_read_reg(cs, reg);
453 	nr_bits = end_bit - st_bit + 1;
454 	mask = (1 << nr_bits) - 1;
455 	l = (l >> st_bit) & mask;
456 	if (!max)
457 		max = mask;
458 	invalid = l > max;
459 	if (shift)
460 		l = (shift << l);
461 	if (noval && (l == 0))
462 		return 0;
463 	if (!raw) {
464 		/* DTS tick format for timings in ns */
465 		unsigned int time_ns;
466 		unsigned int time_ns_min = 0;
467 
468 		if (l)
469 			time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
470 		time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
471 		pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
472 			name, time_ns, time_ns_min, time_ns, l,
473 			invalid ? "; invalid " : " ");
474 	} else {
475 		/* raw format */
476 		pr_info("gpmc,%s = <%u>;%s\n", name, l,
477 			invalid ? " /* invalid */" : "");
478 	}
479 
480 	return l;
481 }
482 
483 #define GPMC_PRINT_CONFIG(cs, config) \
484 	pr_info("cs%i %s: 0x%08x\n", cs, #config, \
485 		gpmc_cs_read_reg(cs, config))
486 #define GPMC_GET_RAW(reg, st, end, field) \
487 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
488 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
489 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
490 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
491 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
492 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
493 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
494 #define GPMC_GET_TICKS(reg, st, end, field) \
495 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
496 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
497 	get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
498 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
499 	get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
500 
501 static void gpmc_show_regs(int cs, const char *desc)
502 {
503 	pr_info("gpmc cs%i %s:\n", cs, desc);
504 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
505 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
506 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
507 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
508 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
509 	GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
510 }
511 
512 /*
513  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
514  * see commit c9fb809.
515  */
516 static void gpmc_cs_show_timings(int cs, const char *desc)
517 {
518 	gpmc_show_regs(cs, desc);
519 
520 	pr_info("gpmc cs%i access configuration:\n", cs);
521 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
522 	GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
523 	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
524 			       GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
525 	GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
526 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
527 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
528 	GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
529 			       GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
530 			       "burst-length");
531 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
532 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
533 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
534 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
535 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
536 
537 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
538 
539 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
540 
541 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
542 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
543 
544 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
545 	GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
546 
547 	pr_info("gpmc cs%i timings configuration:\n", cs);
548 	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
549 	GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
550 	GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
551 
552 	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
553 	GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
554 	GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
555 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
556 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
557 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
558 				"adv-aad-mux-rd-off-ns");
559 		GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
560 				"adv-aad-mux-wr-off-ns");
561 	}
562 
563 	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
564 	GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
565 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
566 		GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
567 		GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
568 	}
569 	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
570 	GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
571 
572 	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
573 	GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
574 	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
575 
576 	GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
577 
578 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
579 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
580 
581 	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
582 			      GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
583 			      "wait-monitoring-ns", GPMC_CD_CLK);
584 	GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
585 			      GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
586 			      "clk-activation-ns", GPMC_CD_FCLK);
587 
588 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
589 	GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
590 }
591 #else
592 static inline void gpmc_cs_show_timings(int cs, const char *desc)
593 {
594 }
595 #endif
596 
597 /**
598  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
599  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
600  * prior to calling this function with @cd equal to GPMC_CD_CLK.
601  *
602  * @cs:      Chip Select Region.
603  * @reg:     GPMC_CS_CONFIGn register offset.
604  * @st_bit:  Start Bit
605  * @end_bit: End Bit. Must be >= @st_bit.
606  * @max:     Maximum parameter value.
607  *           If 0, maximum is as high as @st_bit and @end_bit allow.
608  * @time:    Timing parameter in ns.
609  * @cd:      Timing parameter clock domain.
610  * @name:    Timing parameter name.
611  * @return:  0 on success, -1 on error.
612  */
613 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
614 			       int time, enum gpmc_clk_domain cd, const char *name)
615 {
616 	u32 l;
617 	int ticks, mask, nr_bits;
618 
619 	if (time == 0)
620 		ticks = 0;
621 	else
622 		ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
623 	nr_bits = end_bit - st_bit + 1;
624 	mask = (1 << nr_bits) - 1;
625 
626 	if (!max)
627 		max = mask;
628 
629 	if (ticks > max) {
630 		pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
631 		       __func__, cs, name, time, ticks, max);
632 
633 		return -1;
634 	}
635 
636 	l = gpmc_cs_read_reg(cs, reg);
637 #ifdef CONFIG_OMAP_GPMC_DEBUG
638 	pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
639 		cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
640 			(l >> st_bit) & mask, time);
641 #endif
642 	l &= ~(mask << st_bit);
643 	l |= ticks << st_bit;
644 	gpmc_cs_write_reg(cs, reg, l);
645 
646 	return 0;
647 }
648 
649 /**
650  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
651  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
652  * read  --> don't sample bus too early
653  * write --> data is longer on bus
654  *
655  * Formula:
656  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
657  *                    / waitmonitoring_ticks)
658  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
659  * div <= 0 check.
660  *
661  * @wait_monitoring: WAITMONITORINGTIME in ns.
662  * @return:          -1 on failure to scale, else proper divider > 0.
663  */
664 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
665 {
666 	int div = gpmc_ns_to_ticks(wait_monitoring);
667 
668 	div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
669 	div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
670 
671 	if (div > 4)
672 		return -1;
673 	if (div <= 0)
674 		div = 1;
675 
676 	return div;
677 }
678 
679 /**
680  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
681  * @sync_clk: GPMC_CLK period in ps.
682  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
683  *            Else, returns -1.
684  */
685 int gpmc_calc_divider(unsigned int sync_clk)
686 {
687 	int div = gpmc_ps_to_ticks(sync_clk);
688 
689 	if (div > 4)
690 		return -1;
691 	if (div <= 0)
692 		div = 1;
693 
694 	return div;
695 }
696 
697 /**
698  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
699  * @cs:     Chip Select Region.
700  * @t:      GPMC timing parameters.
701  * @s:      GPMC timing settings.
702  * @return: 0 on success, -1 on error.
703  */
704 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
705 			const struct gpmc_settings *s)
706 {
707 	int div, ret;
708 	u32 l;
709 
710 	div = gpmc_calc_divider(t->sync_clk);
711 	if (div < 0)
712 		return -EINVAL;
713 
714 	/*
715 	 * See if we need to change the divider for waitmonitoringtime.
716 	 *
717 	 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
718 	 * pure asynchronous accesses, i.e. both read and write asynchronous.
719 	 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
720 	 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
721 	 *
722 	 * This statement must not change div to scale async WAITMONITORINGTIME
723 	 * to protect mixed synchronous and asynchronous accesses.
724 	 *
725 	 * We raise an error later if WAITMONITORINGTIME does not fit.
726 	 */
727 	if (!s->sync_read && !s->sync_write &&
728 	    (s->wait_on_read || s->wait_on_write)
729 	   ) {
730 		div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
731 		if (div < 0) {
732 			pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
733 			       __func__,
734 			       t->wait_monitoring
735 			       );
736 			return -ENXIO;
737 		}
738 	}
739 
740 	ret = 0;
741 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
742 				   GPMC_CD_FCLK, "cs_on");
743 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
744 				   GPMC_CD_FCLK, "cs_rd_off");
745 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
746 				   GPMC_CD_FCLK, "cs_wr_off");
747 	if (ret)
748 		return -ENXIO;
749 
750 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
751 				   GPMC_CD_FCLK, "adv_on");
752 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
753 				   GPMC_CD_FCLK, "adv_rd_off");
754 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
755 				   GPMC_CD_FCLK, "adv_wr_off");
756 	if (ret)
757 		return -ENXIO;
758 
759 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
760 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
761 					   t->adv_aad_mux_on, GPMC_CD_FCLK,
762 					   "adv_aad_mux_on");
763 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
764 					   t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
765 					   "adv_aad_mux_rd_off");
766 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
767 					   t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
768 					   "adv_aad_mux_wr_off");
769 		if (ret)
770 			return -ENXIO;
771 	}
772 
773 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
774 				   GPMC_CD_FCLK, "oe_on");
775 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
776 				   GPMC_CD_FCLK, "oe_off");
777 	if (gpmc_capability & GPMC_HAS_MUX_AAD) {
778 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
779 					   t->oe_aad_mux_on, GPMC_CD_FCLK,
780 					   "oe_aad_mux_on");
781 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
782 					   t->oe_aad_mux_off, GPMC_CD_FCLK,
783 					   "oe_aad_mux_off");
784 	}
785 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
786 				   GPMC_CD_FCLK, "we_on");
787 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
788 				   GPMC_CD_FCLK, "we_off");
789 	if (ret)
790 		return -ENXIO;
791 
792 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
793 				   GPMC_CD_FCLK, "rd_cycle");
794 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
795 				   GPMC_CD_FCLK, "wr_cycle");
796 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
797 				   GPMC_CD_FCLK, "access");
798 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
799 				   t->page_burst_access, GPMC_CD_FCLK,
800 				   "page_burst_access");
801 	if (ret)
802 		return -ENXIO;
803 
804 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
805 				   t->bus_turnaround, GPMC_CD_FCLK,
806 				   "bus_turnaround");
807 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
808 				   t->cycle2cycle_delay, GPMC_CD_FCLK,
809 				   "cycle2cycle_delay");
810 	if (ret)
811 		return -ENXIO;
812 
813 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
814 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
815 					   t->wr_data_mux_bus, GPMC_CD_FCLK,
816 					   "wr_data_mux_bus");
817 		if (ret)
818 			return -ENXIO;
819 	}
820 	if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
821 		ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
822 					   t->wr_access, GPMC_CD_FCLK,
823 					   "wr_access");
824 		if (ret)
825 			return -ENXIO;
826 	}
827 
828 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
829 	l &= ~0x03;
830 	l |= (div - 1);
831 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
832 
833 	ret = 0;
834 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
835 				   GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
836 				   t->wait_monitoring, GPMC_CD_CLK,
837 				   "wait_monitoring");
838 	ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
839 				   GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
840 				   t->clk_activation, GPMC_CD_FCLK,
841 				   "clk_activation");
842 	if (ret)
843 		return -ENXIO;
844 
845 #ifdef CONFIG_OMAP_GPMC_DEBUG
846 	pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
847 			cs, (div * gpmc_get_fclk_period()) / 1000, div);
848 #endif
849 
850 	gpmc_cs_bool_timings(cs, &t->bool_timings);
851 	gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
852 
853 	return 0;
854 }
855 
856 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
857 {
858 	u32 l;
859 	u32 mask;
860 
861 	/*
862 	 * Ensure that base address is aligned on a
863 	 * boundary equal to or greater than size.
864 	 */
865 	if (base & (size - 1))
866 		return -EINVAL;
867 
868 	base >>= GPMC_CHUNK_SHIFT;
869 	mask = (1 << GPMC_SECTION_SHIFT) - size;
870 	mask >>= GPMC_CHUNK_SHIFT;
871 	mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
872 
873 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
874 	l &= ~GPMC_CONFIG7_MASK;
875 	l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
876 	l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
877 	l |= GPMC_CONFIG7_CSVALID;
878 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
879 
880 	return 0;
881 }
882 
883 static void gpmc_cs_enable_mem(int cs)
884 {
885 	u32 l;
886 
887 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
888 	l |= GPMC_CONFIG7_CSVALID;
889 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
890 }
891 
892 static void gpmc_cs_disable_mem(int cs)
893 {
894 	u32 l;
895 
896 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
897 	l &= ~GPMC_CONFIG7_CSVALID;
898 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
899 }
900 
901 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
902 {
903 	u32 l;
904 	u32 mask;
905 
906 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
907 	*base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
908 	mask = (l >> 8) & 0x0f;
909 	*size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
910 }
911 
912 static int gpmc_cs_mem_enabled(int cs)
913 {
914 	u32 l;
915 
916 	l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
917 	return l & GPMC_CONFIG7_CSVALID;
918 }
919 
920 static void gpmc_cs_set_reserved(int cs, int reserved)
921 {
922 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
923 
924 	gpmc->flags |= GPMC_CS_RESERVED;
925 }
926 
927 static bool gpmc_cs_reserved(int cs)
928 {
929 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
930 
931 	return gpmc->flags & GPMC_CS_RESERVED;
932 }
933 
934 static unsigned long gpmc_mem_align(unsigned long size)
935 {
936 	int order;
937 
938 	size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
939 	order = GPMC_CHUNK_SHIFT - 1;
940 	do {
941 		size >>= 1;
942 		order++;
943 	} while (size);
944 	size = 1 << order;
945 	return size;
946 }
947 
948 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
949 {
950 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
951 	struct resource *res = &gpmc->mem;
952 	int r;
953 
954 	size = gpmc_mem_align(size);
955 	spin_lock(&gpmc_mem_lock);
956 	res->start = base;
957 	res->end = base + size - 1;
958 	r = request_resource(&gpmc_mem_root, res);
959 	spin_unlock(&gpmc_mem_lock);
960 
961 	return r;
962 }
963 
964 static int gpmc_cs_delete_mem(int cs)
965 {
966 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
967 	struct resource *res = &gpmc->mem;
968 	int r;
969 
970 	spin_lock(&gpmc_mem_lock);
971 	r = release_resource(res);
972 	res->start = 0;
973 	res->end = 0;
974 	spin_unlock(&gpmc_mem_lock);
975 
976 	return r;
977 }
978 
979 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
980 {
981 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
982 	struct resource *res = &gpmc->mem;
983 	int r = -1;
984 
985 	if (cs >= gpmc_cs_num) {
986 		pr_err("%s: requested chip-select is disabled\n", __func__);
987 		return -ENODEV;
988 	}
989 	size = gpmc_mem_align(size);
990 	if (size > (1 << GPMC_SECTION_SHIFT))
991 		return -ENOMEM;
992 
993 	guard(spinlock)(&gpmc_mem_lock);
994 
995 	if (gpmc_cs_reserved(cs))
996 		return -EBUSY;
997 
998 	if (gpmc_cs_mem_enabled(cs))
999 		r = adjust_resource(res, res->start & ~(size - 1), size);
1000 	if (r < 0)
1001 		r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1002 				      size, NULL, NULL);
1003 	if (r < 0)
1004 		return r;
1005 
1006 	/* Disable CS while changing base address and size mask */
1007 	gpmc_cs_disable_mem(cs);
1008 
1009 	r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1010 	if (r < 0) {
1011 		release_resource(res);
1012 		return r;
1013 	}
1014 
1015 	/* Enable CS */
1016 	gpmc_cs_enable_mem(cs);
1017 	*base = res->start;
1018 	gpmc_cs_set_reserved(cs, 1);
1019 
1020 	return 0;
1021 }
1022 EXPORT_SYMBOL(gpmc_cs_request);
1023 
1024 void gpmc_cs_free(int cs)
1025 {
1026 	struct gpmc_cs_data *gpmc;
1027 	struct resource *res;
1028 
1029 	guard(spinlock)(&gpmc_mem_lock);
1030 	if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1031 		WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1032 		return;
1033 	}
1034 	gpmc = &gpmc_cs[cs];
1035 	res = &gpmc->mem;
1036 
1037 	gpmc_cs_disable_mem(cs);
1038 	if (res->flags)
1039 		release_resource(res);
1040 	gpmc_cs_set_reserved(cs, 0);
1041 }
1042 EXPORT_SYMBOL(gpmc_cs_free);
1043 
1044 static bool gpmc_is_valid_waitpin(u32 waitpin)
1045 {
1046 	return waitpin < gpmc_nr_waitpins;
1047 }
1048 
1049 static int gpmc_alloc_waitpin(struct gpmc_device *gpmc,
1050 			      struct gpmc_settings *p)
1051 {
1052 	int ret;
1053 	struct gpmc_waitpin *waitpin;
1054 	struct gpio_desc *waitpin_desc;
1055 
1056 	if (!gpmc_is_valid_waitpin(p->wait_pin))
1057 		return -EINVAL;
1058 
1059 	waitpin = &gpmc->waitpins[p->wait_pin];
1060 
1061 	if (!waitpin->desc) {
1062 		/* Reserve the GPIO for wait pin usage.
1063 		 * GPIO polarity doesn't matter here. Wait pin polarity
1064 		 * is set in GPMC_CONFIG register.
1065 		 */
1066 		waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
1067 							 p->wait_pin, "WAITPIN",
1068 							 GPIO_ACTIVE_HIGH,
1069 							 GPIOD_IN);
1070 
1071 		ret = PTR_ERR(waitpin_desc);
1072 		if (IS_ERR(waitpin_desc) && ret != -EBUSY)
1073 			return ret;
1074 
1075 		/* New wait pin */
1076 		waitpin->desc = waitpin_desc;
1077 		waitpin->pin = p->wait_pin;
1078 		waitpin->polarity = p->wait_pin_polarity;
1079 	} else {
1080 		/* Shared wait pin */
1081 		if (p->wait_pin_polarity != waitpin->polarity ||
1082 		    p->wait_pin != waitpin->pin) {
1083 			dev_err(gpmc->dev,
1084 				"shared-wait-pin: invalid configuration\n");
1085 			return -EINVAL;
1086 		}
1087 		dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin);
1088 	}
1089 
1090 	return 0;
1091 }
1092 
1093 static void gpmc_free_waitpin(struct gpmc_device *gpmc,
1094 			      int wait_pin)
1095 {
1096 	if (gpmc_is_valid_waitpin(wait_pin))
1097 		gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc);
1098 }
1099 
1100 /**
1101  * gpmc_configure - write request to configure gpmc
1102  * @cmd: command type
1103  * @wval: value to write
1104  * @return status of the operation
1105  */
1106 int gpmc_configure(int cmd, int wval)
1107 {
1108 	u32 regval;
1109 
1110 	switch (cmd) {
1111 	case GPMC_CONFIG_WP:
1112 		regval = gpmc_read_reg(GPMC_CONFIG);
1113 		if (wval)
1114 			regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1115 		else
1116 			regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1117 		gpmc_write_reg(GPMC_CONFIG, regval);
1118 		break;
1119 
1120 	default:
1121 		pr_err("%s: command not supported\n", __func__);
1122 		return -EINVAL;
1123 	}
1124 
1125 	return 0;
1126 }
1127 EXPORT_SYMBOL(gpmc_configure);
1128 
1129 static bool gpmc_nand_writebuffer_empty(void)
1130 {
1131 	if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1132 		return true;
1133 
1134 	return false;
1135 }
1136 
1137 static struct gpmc_nand_ops nand_ops = {
1138 	.nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1139 };
1140 
1141 /**
1142  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1143  * @reg: the GPMC NAND register map exclusive for NAND use.
1144  * @cs: GPMC chip select number on which the NAND sits. The
1145  *      register map returned will be specific to this chip select.
1146  *
1147  * Returns NULL on error e.g. invalid cs.
1148  */
1149 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1150 {
1151 	int i;
1152 
1153 	if (cs >= gpmc_cs_num)
1154 		return NULL;
1155 
1156 	reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1157 				GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1158 	reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1159 				GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1160 	reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1161 				GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1162 	reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1163 	reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1164 	reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1165 	reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1166 	reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1167 	reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1168 	reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1169 	reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1170 
1171 	for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1172 		reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1173 					   GPMC_BCH_SIZE * i;
1174 		reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1175 					   GPMC_BCH_SIZE * i;
1176 		reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1177 					   GPMC_BCH_SIZE * i;
1178 		reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1179 					   GPMC_BCH_SIZE * i;
1180 		reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1181 					   i * GPMC_BCH_SIZE;
1182 		reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1183 					   i * GPMC_BCH_SIZE;
1184 		reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1185 					   i * GPMC_BCH_SIZE;
1186 	}
1187 
1188 	return &nand_ops;
1189 }
1190 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1191 
1192 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1193 						struct gpmc_settings *s,
1194 						int freq, int latency)
1195 {
1196 	struct gpmc_device_timings dev_t;
1197 	const int t_cer  = 15;
1198 	const int t_avdp = 12;
1199 	const int t_cez  = 20; /* max of t_cez, t_oez */
1200 	const int t_wpl  = 40;
1201 	const int t_wph  = 30;
1202 	int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1203 
1204 	switch (freq) {
1205 	case 104:
1206 		min_gpmc_clk_period = 9600; /* 104 MHz */
1207 		t_ces   = 3;
1208 		t_avds  = 4;
1209 		t_avdh  = 2;
1210 		t_ach   = 3;
1211 		t_aavdh = 6;
1212 		t_rdyo  = 6;
1213 		break;
1214 	case 83:
1215 		min_gpmc_clk_period = 12000; /* 83 MHz */
1216 		t_ces   = 5;
1217 		t_avds  = 4;
1218 		t_avdh  = 2;
1219 		t_ach   = 6;
1220 		t_aavdh = 6;
1221 		t_rdyo  = 9;
1222 		break;
1223 	case 66:
1224 		min_gpmc_clk_period = 15000; /* 66 MHz */
1225 		t_ces   = 6;
1226 		t_avds  = 5;
1227 		t_avdh  = 2;
1228 		t_ach   = 6;
1229 		t_aavdh = 6;
1230 		t_rdyo  = 11;
1231 		break;
1232 	default:
1233 		min_gpmc_clk_period = 18500; /* 54 MHz */
1234 		t_ces   = 7;
1235 		t_avds  = 7;
1236 		t_avdh  = 7;
1237 		t_ach   = 9;
1238 		t_aavdh = 7;
1239 		t_rdyo  = 15;
1240 		break;
1241 	}
1242 
1243 	/* Set synchronous read timings */
1244 	memset(&dev_t, 0, sizeof(dev_t));
1245 
1246 	if (!s->sync_write) {
1247 		dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1248 		dev_t.t_wpl = t_wpl * 1000;
1249 		dev_t.t_wph = t_wph * 1000;
1250 		dev_t.t_aavdh = t_aavdh * 1000;
1251 	}
1252 	dev_t.ce_xdelay = true;
1253 	dev_t.avd_xdelay = true;
1254 	dev_t.oe_xdelay = true;
1255 	dev_t.we_xdelay = true;
1256 	dev_t.clk = min_gpmc_clk_period;
1257 	dev_t.t_bacc = dev_t.clk;
1258 	dev_t.t_ces = t_ces * 1000;
1259 	dev_t.t_avds = t_avds * 1000;
1260 	dev_t.t_avdh = t_avdh * 1000;
1261 	dev_t.t_ach = t_ach * 1000;
1262 	dev_t.cyc_iaa = (latency + 1);
1263 	dev_t.t_cez_r = t_cez * 1000;
1264 	dev_t.t_cez_w = dev_t.t_cez_r;
1265 	dev_t.cyc_aavdh_oe = 1;
1266 	dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1267 
1268 	gpmc_calc_timings(t, s, &dev_t);
1269 }
1270 
1271 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1272 				  int latency,
1273 				  struct gpmc_onenand_info *info)
1274 {
1275 	int ret;
1276 	struct gpmc_timings gpmc_t;
1277 	struct gpmc_settings gpmc_s;
1278 
1279 	gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1280 
1281 	info->sync_read = gpmc_s.sync_read;
1282 	info->sync_write = gpmc_s.sync_write;
1283 	info->burst_len = gpmc_s.burst_len;
1284 
1285 	if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1286 		return 0;
1287 
1288 	gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1289 
1290 	ret = gpmc_cs_program_settings(cs, &gpmc_s);
1291 	if (ret < 0)
1292 		return ret;
1293 
1294 	return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1295 }
1296 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1297 
1298 int gpmc_get_client_irq(unsigned int irq_config)
1299 {
1300 	if (!gpmc_irq_domain) {
1301 		pr_warn("%s called before GPMC IRQ domain available\n",
1302 			__func__);
1303 		return 0;
1304 	}
1305 
1306 	/* we restrict this to NAND IRQs only */
1307 	if (irq_config >= GPMC_NR_NAND_IRQS)
1308 		return 0;
1309 
1310 	return irq_create_mapping(gpmc_irq_domain, irq_config);
1311 }
1312 
1313 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1314 {
1315 	u32 regval;
1316 
1317 	/* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1318 	if (hwirq >= GPMC_NR_NAND_IRQS)
1319 		hwirq += 8 - GPMC_NR_NAND_IRQS;
1320 
1321 	regval = gpmc_read_reg(GPMC_IRQENABLE);
1322 	if (endis)
1323 		regval |= BIT(hwirq);
1324 	else
1325 		regval &= ~BIT(hwirq);
1326 	gpmc_write_reg(GPMC_IRQENABLE, regval);
1327 
1328 	return 0;
1329 }
1330 
1331 static void gpmc_irq_disable(struct irq_data *p)
1332 {
1333 	gpmc_irq_endis(p->hwirq, false);
1334 }
1335 
1336 static void gpmc_irq_enable(struct irq_data *p)
1337 {
1338 	gpmc_irq_endis(p->hwirq, true);
1339 }
1340 
1341 static void gpmc_irq_mask(struct irq_data *d)
1342 {
1343 	gpmc_irq_endis(d->hwirq, false);
1344 }
1345 
1346 static void gpmc_irq_unmask(struct irq_data *d)
1347 {
1348 	gpmc_irq_endis(d->hwirq, true);
1349 }
1350 
1351 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1352 {
1353 	u32 regval;
1354 
1355 	/* NAND IRQs polarity is not configurable */
1356 	if (hwirq < GPMC_NR_NAND_IRQS)
1357 		return;
1358 
1359 	/* WAITPIN starts at BIT 8 */
1360 	hwirq += 8 - GPMC_NR_NAND_IRQS;
1361 
1362 	regval = gpmc_read_reg(GPMC_CONFIG);
1363 	if (rising_edge)
1364 		regval &= ~BIT(hwirq);
1365 	else
1366 		regval |= BIT(hwirq);
1367 
1368 	gpmc_write_reg(GPMC_CONFIG, regval);
1369 }
1370 
1371 static void gpmc_irq_ack(struct irq_data *d)
1372 {
1373 	unsigned int hwirq = d->hwirq;
1374 
1375 	/* skip reserved bits */
1376 	if (hwirq >= GPMC_NR_NAND_IRQS)
1377 		hwirq += 8 - GPMC_NR_NAND_IRQS;
1378 
1379 	/* Setting bit to 1 clears (or Acks) the interrupt */
1380 	gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1381 }
1382 
1383 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1384 {
1385 	/* can't set type for NAND IRQs */
1386 	if (d->hwirq < GPMC_NR_NAND_IRQS)
1387 		return -EINVAL;
1388 
1389 	/* We can support either rising or falling edge at a time */
1390 	if (trigger == IRQ_TYPE_EDGE_FALLING)
1391 		gpmc_irq_edge_config(d->hwirq, false);
1392 	else if (trigger == IRQ_TYPE_EDGE_RISING)
1393 		gpmc_irq_edge_config(d->hwirq, true);
1394 	else
1395 		return -EINVAL;
1396 
1397 	return 0;
1398 }
1399 
1400 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1401 			irq_hw_number_t hw)
1402 {
1403 	struct gpmc_device *gpmc = d->host_data;
1404 
1405 	irq_set_chip_data(virq, gpmc);
1406 	if (hw < GPMC_NR_NAND_IRQS) {
1407 		irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1408 		irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1409 					 handle_simple_irq);
1410 	} else {
1411 		irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1412 					 handle_edge_irq);
1413 	}
1414 
1415 	return 0;
1416 }
1417 
1418 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1419 	.map    = gpmc_irq_map,
1420 	.xlate  = irq_domain_xlate_twocell,
1421 };
1422 
1423 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1424 {
1425 	int hwirq, virq;
1426 	u32 regval, regvalx;
1427 	struct gpmc_device *gpmc = data;
1428 
1429 	regval = gpmc_read_reg(GPMC_IRQSTATUS);
1430 	regvalx = regval;
1431 
1432 	if (!regval)
1433 		return IRQ_NONE;
1434 
1435 	for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1436 		/* skip reserved status bits */
1437 		if (hwirq == GPMC_NR_NAND_IRQS)
1438 			regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1439 
1440 		if (regvalx & BIT(hwirq)) {
1441 			virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1442 			if (!virq) {
1443 				dev_warn(gpmc->dev,
1444 					 "spurious irq detected hwirq %d, virq %d\n",
1445 					 hwirq, virq);
1446 			}
1447 
1448 			generic_handle_irq(virq);
1449 		}
1450 	}
1451 
1452 	gpmc_write_reg(GPMC_IRQSTATUS, regval);
1453 
1454 	return IRQ_HANDLED;
1455 }
1456 
1457 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1458 {
1459 	u32 regval;
1460 	int rc;
1461 
1462 	/* Disable interrupts */
1463 	gpmc_write_reg(GPMC_IRQENABLE, 0);
1464 
1465 	/* clear interrupts */
1466 	regval = gpmc_read_reg(GPMC_IRQSTATUS);
1467 	gpmc_write_reg(GPMC_IRQSTATUS, regval);
1468 
1469 	gpmc->irq_chip.name = "gpmc";
1470 	gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1471 	gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1472 	gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1473 	gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1474 	gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1475 	gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1476 
1477 	gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1478 						gpmc->nirqs,
1479 						&gpmc_irq_domain_ops,
1480 						gpmc);
1481 	if (!gpmc_irq_domain) {
1482 		dev_err(gpmc->dev, "IRQ domain add failed\n");
1483 		return -ENODEV;
1484 	}
1485 
1486 	rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1487 	if (rc) {
1488 		dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1489 			gpmc->irq, rc);
1490 		irq_domain_remove(gpmc_irq_domain);
1491 		gpmc_irq_domain = NULL;
1492 	}
1493 
1494 	return rc;
1495 }
1496 
1497 static int gpmc_free_irq(struct gpmc_device *gpmc)
1498 {
1499 	int hwirq;
1500 
1501 	free_irq(gpmc->irq, gpmc);
1502 
1503 	for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1504 		irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1505 
1506 	irq_domain_remove(gpmc_irq_domain);
1507 	gpmc_irq_domain = NULL;
1508 
1509 	return 0;
1510 }
1511 
1512 static void gpmc_mem_exit(void)
1513 {
1514 	int cs;
1515 
1516 	for (cs = 0; cs < gpmc_cs_num; cs++) {
1517 		if (!gpmc_cs_mem_enabled(cs))
1518 			continue;
1519 		gpmc_cs_delete_mem(cs);
1520 	}
1521 }
1522 
1523 static void gpmc_mem_init(struct gpmc_device *gpmc)
1524 {
1525 	int cs;
1526 
1527 	if (!gpmc->data) {
1528 		/* All legacy devices have same data IO window */
1529 		gpmc_mem_root.start = GPMC_MEM_START;
1530 		gpmc_mem_root.end = GPMC_MEM_END;
1531 	} else {
1532 		gpmc_mem_root.start = gpmc->data->start;
1533 		gpmc_mem_root.end = gpmc->data->end;
1534 	}
1535 
1536 	/* Reserve all regions that has been set up by bootloader */
1537 	for (cs = 0; cs < gpmc_cs_num; cs++) {
1538 		u32 base, size;
1539 
1540 		if (!gpmc_cs_mem_enabled(cs))
1541 			continue;
1542 		gpmc_cs_get_memconf(cs, &base, &size);
1543 		if (gpmc_cs_insert_mem(cs, base, size)) {
1544 			pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1545 				__func__, cs, base, base + size);
1546 			gpmc_cs_disable_mem(cs);
1547 		}
1548 	}
1549 }
1550 
1551 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1552 {
1553 	u32 temp;
1554 	int div;
1555 
1556 	div = gpmc_calc_divider(sync_clk);
1557 	temp = gpmc_ps_to_ticks(time_ps);
1558 	temp = (temp + div - 1) / div;
1559 	return gpmc_ticks_to_ps(temp * div);
1560 }
1561 
1562 /* XXX: can the cycles be avoided ? */
1563 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1564 				       struct gpmc_device_timings *dev_t,
1565 				       bool mux)
1566 {
1567 	u32 temp;
1568 
1569 	/* adv_rd_off */
1570 	temp = dev_t->t_avdp_r;
1571 	/* XXX: mux check required ? */
1572 	if (mux) {
1573 		/* XXX: t_avdp not to be required for sync, only added for tusb
1574 		 * this indirectly necessitates requirement of t_avdp_r and
1575 		 * t_avdp_w instead of having a single t_avdp
1576 		 */
1577 		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_avdh);
1578 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1579 	}
1580 	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1581 
1582 	/* oe_on */
1583 	temp = dev_t->t_oeasu; /* XXX: remove this ? */
1584 	if (mux) {
1585 		temp = max_t(u32, temp,	gpmc_t->clk_activation + dev_t->t_ach);
1586 		temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1587 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1588 	}
1589 	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1590 
1591 	/* access */
1592 	/* XXX: any scope for improvement ?, by combining oe_on
1593 	 * and clk_activation, need to check whether
1594 	 * access = clk_activation + round to sync clk ?
1595 	 */
1596 	temp = max_t(u32, dev_t->t_iaa,	dev_t->cyc_iaa * gpmc_t->sync_clk);
1597 	temp += gpmc_t->clk_activation;
1598 	if (dev_t->cyc_oe)
1599 		temp = max_t(u32, temp, gpmc_t->oe_on +
1600 				gpmc_ticks_to_ps(dev_t->cyc_oe));
1601 	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1602 
1603 	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1604 	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1605 
1606 	/* rd_cycle */
1607 	temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1608 	temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1609 							gpmc_t->access;
1610 	/* XXX: barter t_ce_rdyz with t_cez_r ? */
1611 	if (dev_t->t_ce_rdyz)
1612 		temp = max_t(u32, temp,	gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1613 	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1614 
1615 	return 0;
1616 }
1617 
1618 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1619 					struct gpmc_device_timings *dev_t,
1620 					bool mux)
1621 {
1622 	u32 temp;
1623 
1624 	/* adv_wr_off */
1625 	temp = dev_t->t_avdp_w;
1626 	if (mux) {
1627 		temp = max_t(u32, temp,
1628 			gpmc_t->clk_activation + dev_t->t_avdh);
1629 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1630 	}
1631 	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1632 
1633 	/* wr_data_mux_bus */
1634 	temp = max_t(u32, dev_t->t_weasu,
1635 			gpmc_t->clk_activation + dev_t->t_rdyo);
1636 	/* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1637 	 * and in that case remember to handle we_on properly
1638 	 */
1639 	if (mux) {
1640 		temp = max_t(u32, temp,
1641 			gpmc_t->adv_wr_off + dev_t->t_aavdh);
1642 		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1643 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1644 	}
1645 	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1646 
1647 	/* we_on */
1648 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1649 		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1650 	else
1651 		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1652 
1653 	/* wr_access */
1654 	/* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1655 	gpmc_t->wr_access = gpmc_t->access;
1656 
1657 	/* we_off */
1658 	temp = gpmc_t->we_on + dev_t->t_wpl;
1659 	temp = max_t(u32, temp,
1660 			gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1661 	temp = max_t(u32, temp,
1662 		gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1663 	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1664 
1665 	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1666 							dev_t->t_wph);
1667 
1668 	/* wr_cycle */
1669 	temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1670 	temp += gpmc_t->wr_access;
1671 	/* XXX: barter t_ce_rdyz with t_cez_w ? */
1672 	if (dev_t->t_ce_rdyz)
1673 		temp = max_t(u32, temp,
1674 				 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1675 	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1676 
1677 	return 0;
1678 }
1679 
1680 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1681 					struct gpmc_device_timings *dev_t,
1682 					bool mux)
1683 {
1684 	u32 temp;
1685 
1686 	/* adv_rd_off */
1687 	temp = dev_t->t_avdp_r;
1688 	if (mux)
1689 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1690 	gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1691 
1692 	/* oe_on */
1693 	temp = dev_t->t_oeasu;
1694 	if (mux)
1695 		temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1696 	gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1697 
1698 	/* access */
1699 	temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1700 		     gpmc_t->oe_on + dev_t->t_oe);
1701 	temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1702 	temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1703 	gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1704 
1705 	gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1706 	gpmc_t->cs_rd_off = gpmc_t->oe_off;
1707 
1708 	/* rd_cycle */
1709 	temp = max_t(u32, dev_t->t_rd_cycle,
1710 			gpmc_t->cs_rd_off + dev_t->t_cez_r);
1711 	temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1712 	gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1713 
1714 	return 0;
1715 }
1716 
1717 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1718 					 struct gpmc_device_timings *dev_t,
1719 					 bool mux)
1720 {
1721 	u32 temp;
1722 
1723 	/* adv_wr_off */
1724 	temp = dev_t->t_avdp_w;
1725 	if (mux)
1726 		temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1727 	gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1728 
1729 	/* wr_data_mux_bus */
1730 	temp = dev_t->t_weasu;
1731 	if (mux) {
1732 		temp = max_t(u32, temp,	gpmc_t->adv_wr_off + dev_t->t_aavdh);
1733 		temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1734 				gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1735 	}
1736 	gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1737 
1738 	/* we_on */
1739 	if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1740 		gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1741 	else
1742 		gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1743 
1744 	/* we_off */
1745 	temp = gpmc_t->we_on + dev_t->t_wpl;
1746 	gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1747 
1748 	gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1749 							dev_t->t_wph);
1750 
1751 	/* wr_cycle */
1752 	temp = max_t(u32, dev_t->t_wr_cycle,
1753 				gpmc_t->cs_wr_off + dev_t->t_cez_w);
1754 	gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1755 
1756 	return 0;
1757 }
1758 
1759 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1760 			struct gpmc_device_timings *dev_t)
1761 {
1762 	u32 temp;
1763 
1764 	gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1765 						gpmc_get_fclk_period();
1766 
1767 	gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1768 					dev_t->t_bacc,
1769 					gpmc_t->sync_clk);
1770 
1771 	temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1772 	gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1773 
1774 	if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1775 		return 0;
1776 
1777 	if (dev_t->ce_xdelay)
1778 		gpmc_t->bool_timings.cs_extra_delay = true;
1779 	if (dev_t->avd_xdelay)
1780 		gpmc_t->bool_timings.adv_extra_delay = true;
1781 	if (dev_t->oe_xdelay)
1782 		gpmc_t->bool_timings.oe_extra_delay = true;
1783 	if (dev_t->we_xdelay)
1784 		gpmc_t->bool_timings.we_extra_delay = true;
1785 
1786 	return 0;
1787 }
1788 
1789 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1790 				    struct gpmc_device_timings *dev_t,
1791 				    bool sync)
1792 {
1793 	u32 temp;
1794 
1795 	/* cs_on */
1796 	gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1797 
1798 	/* adv_on */
1799 	temp = dev_t->t_avdasu;
1800 	if (dev_t->t_ce_avd)
1801 		temp = max_t(u32, temp,
1802 				gpmc_t->cs_on + dev_t->t_ce_avd);
1803 	gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1804 
1805 	if (sync)
1806 		gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1807 
1808 	return 0;
1809 }
1810 
1811 /*
1812  * TODO: remove this function once all peripherals are confirmed to
1813  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1814  * has to be modified to handle timings in ps instead of ns
1815  */
1816 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1817 {
1818 	t->cs_on /= 1000;
1819 	t->cs_rd_off /= 1000;
1820 	t->cs_wr_off /= 1000;
1821 	t->adv_on /= 1000;
1822 	t->adv_rd_off /= 1000;
1823 	t->adv_wr_off /= 1000;
1824 	t->we_on /= 1000;
1825 	t->we_off /= 1000;
1826 	t->oe_on /= 1000;
1827 	t->oe_off /= 1000;
1828 	t->page_burst_access /= 1000;
1829 	t->access /= 1000;
1830 	t->rd_cycle /= 1000;
1831 	t->wr_cycle /= 1000;
1832 	t->bus_turnaround /= 1000;
1833 	t->cycle2cycle_delay /= 1000;
1834 	t->wait_monitoring /= 1000;
1835 	t->clk_activation /= 1000;
1836 	t->wr_access /= 1000;
1837 	t->wr_data_mux_bus /= 1000;
1838 }
1839 
1840 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1841 		      struct gpmc_settings *gpmc_s,
1842 		      struct gpmc_device_timings *dev_t)
1843 {
1844 	bool mux = false, sync = false;
1845 
1846 	if (gpmc_s) {
1847 		mux = gpmc_s->mux_add_data ? true : false;
1848 		sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1849 	}
1850 
1851 	memset(gpmc_t, 0, sizeof(*gpmc_t));
1852 
1853 	gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1854 
1855 	if (gpmc_s && gpmc_s->sync_read)
1856 		gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1857 	else
1858 		gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1859 
1860 	if (gpmc_s && gpmc_s->sync_write)
1861 		gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1862 	else
1863 		gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1864 
1865 	/* TODO: remove, see function definition */
1866 	gpmc_convert_ps_to_ns(gpmc_t);
1867 
1868 	return 0;
1869 }
1870 
1871 /**
1872  * gpmc_cs_program_settings - programs non-timing related settings
1873  * @cs:		GPMC chip-select to program
1874  * @p:		pointer to GPMC settings structure
1875  *
1876  * Programs non-timing related settings for a GPMC chip-select, such as
1877  * bus-width, burst configuration, etc. Function should be called once
1878  * for each chip-select that is being used and must be called before
1879  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1880  * register will be initialised to zero by this function. Returns 0 on
1881  * success and appropriate negative error code on failure.
1882  */
1883 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1884 {
1885 	u32 config1;
1886 
1887 	if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1888 		pr_err("%s: invalid width %d!", __func__, p->device_width);
1889 		return -EINVAL;
1890 	}
1891 
1892 	/* Address-data multiplexing not supported for NAND devices */
1893 	if (p->device_nand && p->mux_add_data) {
1894 		pr_err("%s: invalid configuration!\n", __func__);
1895 		return -EINVAL;
1896 	}
1897 
1898 	if ((p->mux_add_data > GPMC_MUX_AD) ||
1899 	    ((p->mux_add_data == GPMC_MUX_AAD) &&
1900 	     !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1901 		pr_err("%s: invalid multiplex configuration!\n", __func__);
1902 		return -EINVAL;
1903 	}
1904 
1905 	/* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1906 	if (p->burst_read || p->burst_write) {
1907 		switch (p->burst_len) {
1908 		case GPMC_BURST_4:
1909 		case GPMC_BURST_8:
1910 		case GPMC_BURST_16:
1911 			break;
1912 		default:
1913 			pr_err("%s: invalid page/burst-length (%d)\n",
1914 			       __func__, p->burst_len);
1915 			return -EINVAL;
1916 		}
1917 	}
1918 
1919 	if (p->wait_pin != GPMC_WAITPIN_INVALID &&
1920 	    p->wait_pin > gpmc_nr_waitpins) {
1921 		pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1922 		return -EINVAL;
1923 	}
1924 
1925 	config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1926 
1927 	if (p->sync_read)
1928 		config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1929 	if (p->sync_write)
1930 		config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1931 	if (p->wait_on_read)
1932 		config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1933 	if (p->wait_on_write)
1934 		config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1935 	if (p->wait_on_read || p->wait_on_write)
1936 		config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1937 	if (p->device_nand)
1938 		config1	|= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1939 	if (p->mux_add_data)
1940 		config1	|= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1941 	if (p->burst_read)
1942 		config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1943 	if (p->burst_write)
1944 		config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1945 	if (p->burst_read || p->burst_write) {
1946 		config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1947 		config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1948 	}
1949 
1950 	gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1951 
1952 	if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) {
1953 		config1 = gpmc_read_reg(GPMC_CONFIG);
1954 
1955 		if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW)
1956 			config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
1957 		else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH)
1958 			config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin);
1959 
1960 		gpmc_write_reg(GPMC_CONFIG, config1);
1961 	}
1962 
1963 	return 0;
1964 }
1965 
1966 #ifdef CONFIG_OF
1967 static void gpmc_cs_set_name(int cs, const char *name)
1968 {
1969 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1970 
1971 	gpmc->name = name;
1972 }
1973 
1974 static const char *gpmc_cs_get_name(int cs)
1975 {
1976 	struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1977 
1978 	return gpmc->name;
1979 }
1980 
1981 /**
1982  * gpmc_cs_remap - remaps a chip-select physical base address
1983  * @cs:		chip-select to remap
1984  * @base:	physical base address to re-map chip-select to
1985  *
1986  * Re-maps a chip-select to a new physical base address specified by
1987  * "base". Returns 0 on success and appropriate negative error code
1988  * on failure.
1989  */
1990 static int gpmc_cs_remap(int cs, u32 base)
1991 {
1992 	int ret;
1993 	u32 old_base, size;
1994 
1995 	if (cs >= gpmc_cs_num) {
1996 		pr_err("%s: requested chip-select is disabled\n", __func__);
1997 		return -ENODEV;
1998 	}
1999 
2000 	/*
2001 	 * Make sure we ignore any device offsets from the GPMC partition
2002 	 * allocated for the chip select and that the new base confirms
2003 	 * to the GPMC 16MB minimum granularity.
2004 	 */
2005 	base &= ~(SZ_16M - 1);
2006 
2007 	gpmc_cs_get_memconf(cs, &old_base, &size);
2008 	if (base == old_base)
2009 		return 0;
2010 
2011 	ret = gpmc_cs_delete_mem(cs);
2012 	if (ret < 0)
2013 		return ret;
2014 
2015 	ret = gpmc_cs_insert_mem(cs, base, size);
2016 	if (ret < 0)
2017 		return ret;
2018 
2019 	ret = gpmc_cs_set_memconf(cs, base, size);
2020 
2021 	return ret;
2022 }
2023 
2024 /**
2025  * gpmc_read_settings_dt - read gpmc settings from device-tree
2026  * @np:		pointer to device-tree node for a gpmc child device
2027  * @p:		pointer to gpmc settings structure
2028  *
2029  * Reads the GPMC settings for a GPMC child device from device-tree and
2030  * stores them in the GPMC settings structure passed. The GPMC settings
2031  * structure is initialised to zero by this function and so any
2032  * previously stored settings will be cleared.
2033  */
2034 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2035 {
2036 	memset(p, 0, sizeof(struct gpmc_settings));
2037 
2038 	p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
2039 	p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
2040 	of_property_read_u32(np, "gpmc,device-width", &p->device_width);
2041 	of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
2042 
2043 	if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
2044 		p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
2045 		p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
2046 		p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
2047 		if (!p->burst_read && !p->burst_write)
2048 			pr_warn("%s: page/burst-length set but not used!\n",
2049 				__func__);
2050 	}
2051 
2052 	p->wait_pin = GPMC_WAITPIN_INVALID;
2053 	p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
2054 
2055 	if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
2056 		if (!gpmc_is_valid_waitpin(p->wait_pin)) {
2057 			pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin);
2058 			p->wait_pin = GPMC_WAITPIN_INVALID;
2059 		}
2060 
2061 		if (!of_property_read_u32(np, "ti,wait-pin-polarity",
2062 					  &p->wait_pin_polarity)) {
2063 			if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH &&
2064 			    p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) {
2065 				pr_err("%s: Invalid wait-pin-polarity (%d)\n",
2066 				       __func__, p->wait_pin_polarity);
2067 				p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID;
2068 				}
2069 		}
2070 
2071 		p->wait_on_read = of_property_read_bool(np,
2072 							"gpmc,wait-on-read");
2073 		p->wait_on_write = of_property_read_bool(np,
2074 							 "gpmc,wait-on-write");
2075 		if (!p->wait_on_read && !p->wait_on_write)
2076 			pr_debug("%s: rd/wr wait monitoring not enabled!\n",
2077 				 __func__);
2078 	}
2079 }
2080 
2081 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
2082 						struct gpmc_timings *gpmc_t)
2083 {
2084 	struct gpmc_bool_timings *p;
2085 
2086 	if (!np || !gpmc_t)
2087 		return;
2088 
2089 	memset(gpmc_t, 0, sizeof(*gpmc_t));
2090 
2091 	/* minimum clock period for syncronous mode */
2092 	of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
2093 
2094 	/* chip select timtings */
2095 	of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2096 	of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2097 	of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2098 
2099 	/* ADV signal timings */
2100 	of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2101 	of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2102 	of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2103 	of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2104 			     &gpmc_t->adv_aad_mux_on);
2105 	of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2106 			     &gpmc_t->adv_aad_mux_rd_off);
2107 	of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2108 			     &gpmc_t->adv_aad_mux_wr_off);
2109 
2110 	/* WE signal timings */
2111 	of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2112 	of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2113 
2114 	/* OE signal timings */
2115 	of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2116 	of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2117 	of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2118 			     &gpmc_t->oe_aad_mux_on);
2119 	of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2120 			     &gpmc_t->oe_aad_mux_off);
2121 
2122 	/* access and cycle timings */
2123 	of_property_read_u32(np, "gpmc,page-burst-access-ns",
2124 			     &gpmc_t->page_burst_access);
2125 	of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2126 	of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2127 	of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2128 	of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2129 			     &gpmc_t->bus_turnaround);
2130 	of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2131 			     &gpmc_t->cycle2cycle_delay);
2132 	of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2133 			     &gpmc_t->wait_monitoring);
2134 	of_property_read_u32(np, "gpmc,clk-activation-ns",
2135 			     &gpmc_t->clk_activation);
2136 
2137 	/* only applicable to OMAP3+ */
2138 	of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2139 	of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2140 			     &gpmc_t->wr_data_mux_bus);
2141 
2142 	/* bool timing parameters */
2143 	p = &gpmc_t->bool_timings;
2144 
2145 	p->cycle2cyclediffcsen =
2146 		of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2147 	p->cycle2cyclesamecsen =
2148 		of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2149 	p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2150 	p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2151 	p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2152 	p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2153 	p->time_para_granularity =
2154 		of_property_read_bool(np, "gpmc,time-para-granularity");
2155 }
2156 
2157 /**
2158  * gpmc_probe_generic_child - configures the gpmc for a child device
2159  * @pdev:	pointer to gpmc platform device
2160  * @child:	pointer to device-tree node for child device
2161  *
2162  * Allocates and configures a GPMC chip-select for a child device.
2163  * Returns 0 on success and appropriate negative error code on failure.
2164  */
2165 static int gpmc_probe_generic_child(struct platform_device *pdev,
2166 				struct device_node *child)
2167 {
2168 	struct gpmc_settings gpmc_s;
2169 	struct gpmc_timings gpmc_t;
2170 	struct resource res;
2171 	unsigned long base;
2172 	const char *name;
2173 	int ret, cs;
2174 	u32 val;
2175 	struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2176 
2177 	if (of_property_read_u32(child, "reg", &cs) < 0) {
2178 		dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2179 			child);
2180 		return -ENODEV;
2181 	}
2182 
2183 	if (of_address_to_resource(child, 0, &res) < 0) {
2184 		dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2185 			child);
2186 		return -ENODEV;
2187 	}
2188 
2189 	/*
2190 	 * Check if we have multiple instances of the same device
2191 	 * on a single chip select. If so, use the already initialized
2192 	 * timings.
2193 	 */
2194 	name = gpmc_cs_get_name(cs);
2195 	if (name && of_node_name_eq(child, name))
2196 		goto no_timings;
2197 
2198 	ret = gpmc_cs_request(cs, resource_size(&res), &base);
2199 	if (ret < 0) {
2200 		dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2201 		return ret;
2202 	}
2203 	gpmc_cs_set_name(cs, child->full_name);
2204 
2205 	gpmc_read_settings_dt(child, &gpmc_s);
2206 	gpmc_read_timings_dt(child, &gpmc_t);
2207 
2208 	/*
2209 	 * For some GPMC devices we still need to rely on the bootloader
2210 	 * timings because the devices can be connected via FPGA.
2211 	 * REVISIT: Add timing support from slls644g.pdf.
2212 	 */
2213 	if (!gpmc_t.cs_rd_off) {
2214 		WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2215 			cs);
2216 		gpmc_cs_show_timings(cs,
2217 				     "please add GPMC bootloader timings to .dts");
2218 		goto no_timings;
2219 	}
2220 
2221 	/* CS must be disabled while making changes to gpmc configuration */
2222 	gpmc_cs_disable_mem(cs);
2223 
2224 	/*
2225 	 * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2226 	 * location in the gpmc address space. When booting with
2227 	 * device-tree we want the NOR flash to be mapped to the
2228 	 * location specified in the device-tree blob. So remap the
2229 	 * CS to this location. Once DT migration is complete should
2230 	 * just make gpmc_cs_request() map a specific address.
2231 	 */
2232 	ret = gpmc_cs_remap(cs, res.start);
2233 	if (ret < 0) {
2234 		dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2235 			cs, &res.start);
2236 		if (res.start < GPMC_MEM_START) {
2237 			dev_info(&pdev->dev,
2238 				 "GPMC CS %d start cannot be lesser than 0x%x\n",
2239 				 cs, GPMC_MEM_START);
2240 		} else if (res.end > GPMC_MEM_END) {
2241 			dev_info(&pdev->dev,
2242 				 "GPMC CS %d end cannot be greater than 0x%x\n",
2243 				 cs, GPMC_MEM_END);
2244 		}
2245 		goto err;
2246 	}
2247 
2248 	if (of_node_name_eq(child, "nand")) {
2249 		/* Warn about older DT blobs with no compatible property */
2250 		if (!of_property_read_bool(child, "compatible")) {
2251 			dev_warn(&pdev->dev,
2252 				 "Incompatible NAND node: missing compatible");
2253 			ret = -EINVAL;
2254 			goto err;
2255 		}
2256 	}
2257 
2258 	if (of_node_name_eq(child, "onenand")) {
2259 		/* Warn about older DT blobs with no compatible property */
2260 		if (!of_property_read_bool(child, "compatible")) {
2261 			dev_warn(&pdev->dev,
2262 				 "Incompatible OneNAND node: missing compatible");
2263 			ret = -EINVAL;
2264 			goto err;
2265 		}
2266 	}
2267 
2268 	if (of_match_node(omap_nand_ids, child)) {
2269 		/* NAND specific setup */
2270 		val = 8;
2271 		of_property_read_u32(child, "nand-bus-width", &val);
2272 		switch (val) {
2273 		case 8:
2274 			gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2275 			break;
2276 		case 16:
2277 			gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2278 			break;
2279 		default:
2280 			dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2281 				child);
2282 			ret = -EINVAL;
2283 			goto err;
2284 		}
2285 
2286 		/* disable write protect */
2287 		gpmc_configure(GPMC_CONFIG_WP, 0);
2288 		gpmc_s.device_nand = true;
2289 	} else {
2290 		ret = of_property_read_u32(child, "bank-width",
2291 					   &gpmc_s.device_width);
2292 		if (ret < 0 && !gpmc_s.device_width) {
2293 			dev_err(&pdev->dev,
2294 				"%pOF has no 'gpmc,device-width' property\n",
2295 				child);
2296 			goto err;
2297 		}
2298 	}
2299 
2300 	/* Reserve wait pin if it is required and valid */
2301 	if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2302 		ret = gpmc_alloc_waitpin(gpmc, &gpmc_s);
2303 		if (ret < 0)
2304 			goto err;
2305 	}
2306 
2307 	gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2308 
2309 	ret = gpmc_cs_program_settings(cs, &gpmc_s);
2310 	if (ret < 0)
2311 		goto err_cs;
2312 
2313 	ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2314 	if (ret) {
2315 		dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2316 			child);
2317 		goto err_cs;
2318 	}
2319 
2320 	/* Clear limited address i.e. enable A26-A11 */
2321 	val = gpmc_read_reg(GPMC_CONFIG);
2322 	val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2323 	gpmc_write_reg(GPMC_CONFIG, val);
2324 
2325 	/* Enable CS region */
2326 	gpmc_cs_enable_mem(cs);
2327 
2328 no_timings:
2329 
2330 	/* create platform device, NULL on error or when disabled */
2331 	if (!of_platform_device_create(child, NULL, &pdev->dev))
2332 		goto err_child_fail;
2333 
2334 	/* create children and other common bus children */
2335 	if (of_platform_default_populate(child, NULL, &pdev->dev))
2336 		goto err_child_fail;
2337 
2338 	return 0;
2339 
2340 err_child_fail:
2341 
2342 	dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2343 	ret = -ENODEV;
2344 
2345 err_cs:
2346 	gpmc_free_waitpin(gpmc, gpmc_s.wait_pin);
2347 err:
2348 	gpmc_cs_free(cs);
2349 
2350 	return ret;
2351 }
2352 
2353 static const struct of_device_id gpmc_dt_ids[];
2354 
2355 static int gpmc_probe_dt(struct platform_device *pdev)
2356 {
2357 	int ret;
2358 	const struct of_device_id *of_id =
2359 		of_match_device(gpmc_dt_ids, &pdev->dev);
2360 
2361 	if (!of_id)
2362 		return 0;
2363 
2364 	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2365 				   &gpmc_cs_num);
2366 	if (ret < 0) {
2367 		pr_err("%s: number of chip-selects not defined\n", __func__);
2368 		return ret;
2369 	} else if (gpmc_cs_num < 1) {
2370 		pr_err("%s: all chip-selects are disabled\n", __func__);
2371 		return -EINVAL;
2372 	} else if (gpmc_cs_num > GPMC_CS_NUM) {
2373 		pr_err("%s: number of supported chip-selects cannot be > %d\n",
2374 					 __func__, GPMC_CS_NUM);
2375 		return -EINVAL;
2376 	}
2377 
2378 	ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2379 				   &gpmc_nr_waitpins);
2380 	if (ret < 0) {
2381 		pr_err("%s: number of wait pins not found!\n", __func__);
2382 		return ret;
2383 	}
2384 
2385 	return 0;
2386 }
2387 
2388 static void gpmc_probe_dt_children(struct platform_device *pdev)
2389 {
2390 	int ret;
2391 	struct device_node *child;
2392 
2393 	for_each_available_child_of_node(pdev->dev.of_node, child) {
2394 		ret = gpmc_probe_generic_child(pdev, child);
2395 		if (ret) {
2396 			dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2397 				child, ret);
2398 		}
2399 	}
2400 }
2401 #else
2402 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2403 {
2404 	memset(p, 0, sizeof(*p));
2405 }
2406 static int gpmc_probe_dt(struct platform_device *pdev)
2407 {
2408 	return 0;
2409 }
2410 
2411 static void gpmc_probe_dt_children(struct platform_device *pdev)
2412 {
2413 }
2414 #endif /* CONFIG_OF */
2415 
2416 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2417 {
2418 	return 1;	/* we're input only */
2419 }
2420 
2421 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2422 				     unsigned int offset)
2423 {
2424 	return 0;	/* we're input only */
2425 }
2426 
2427 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2428 				      unsigned int offset, int value)
2429 {
2430 	return -EINVAL;	/* we're input only */
2431 }
2432 
2433 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2434 			  int value)
2435 {
2436 }
2437 
2438 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2439 {
2440 	u32 reg;
2441 
2442 	offset += 8;
2443 
2444 	reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2445 
2446 	return !!reg;
2447 }
2448 
2449 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2450 {
2451 	int ret;
2452 
2453 	gpmc->gpio_chip.parent = gpmc->dev;
2454 	gpmc->gpio_chip.owner = THIS_MODULE;
2455 	gpmc->gpio_chip.label = DEVICE_NAME;
2456 	gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2457 	gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2458 	gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2459 	gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2460 	gpmc->gpio_chip.set = gpmc_gpio_set;
2461 	gpmc->gpio_chip.get = gpmc_gpio_get;
2462 	gpmc->gpio_chip.base = -1;
2463 
2464 	ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2465 	if (ret < 0) {
2466 		dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2467 		return ret;
2468 	}
2469 
2470 	return 0;
2471 }
2472 
2473 static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
2474 {
2475 	struct omap3_gpmc_regs *gpmc_context;
2476 	int i;
2477 
2478 	if (!gpmc || !gpmc_base)
2479 		return;
2480 
2481 	gpmc_context = &gpmc->context;
2482 
2483 	gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2484 	gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2485 	gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2486 	gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
2487 	gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2488 	gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2489 	gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2490 	for (i = 0; i < gpmc_cs_num; i++) {
2491 		gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2492 		if (gpmc_context->cs_context[i].is_valid) {
2493 			gpmc_context->cs_context[i].config1 =
2494 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2495 			gpmc_context->cs_context[i].config2 =
2496 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2497 			gpmc_context->cs_context[i].config3 =
2498 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2499 			gpmc_context->cs_context[i].config4 =
2500 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2501 			gpmc_context->cs_context[i].config5 =
2502 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2503 			gpmc_context->cs_context[i].config6 =
2504 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2505 			gpmc_context->cs_context[i].config7 =
2506 				gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2507 		}
2508 	}
2509 }
2510 
2511 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
2512 {
2513 	struct omap3_gpmc_regs *gpmc_context;
2514 	int i;
2515 
2516 	if (!gpmc || !gpmc_base)
2517 		return;
2518 
2519 	gpmc_context = &gpmc->context;
2520 
2521 	gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
2522 	gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
2523 	gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
2524 	gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
2525 	gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
2526 	gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
2527 	gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
2528 	for (i = 0; i < gpmc_cs_num; i++) {
2529 		if (gpmc_context->cs_context[i].is_valid) {
2530 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2531 					  gpmc_context->cs_context[i].config1);
2532 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2533 					  gpmc_context->cs_context[i].config2);
2534 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2535 					  gpmc_context->cs_context[i].config3);
2536 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2537 					  gpmc_context->cs_context[i].config4);
2538 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2539 					  gpmc_context->cs_context[i].config5);
2540 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2541 					  gpmc_context->cs_context[i].config6);
2542 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2543 					  gpmc_context->cs_context[i].config7);
2544 		} else {
2545 			gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
2546 		}
2547 	}
2548 }
2549 
2550 static int omap_gpmc_context_notifier(struct notifier_block *nb,
2551 				      unsigned long cmd, void *v)
2552 {
2553 	struct gpmc_device *gpmc;
2554 
2555 	gpmc = container_of(nb, struct gpmc_device, nb);
2556 	if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
2557 		return NOTIFY_OK;
2558 
2559 	switch (cmd) {
2560 	case CPU_CLUSTER_PM_ENTER:
2561 		omap3_gpmc_save_context(gpmc);
2562 		break;
2563 	case CPU_CLUSTER_PM_ENTER_FAILED:	/* No need to restore context */
2564 		break;
2565 	case CPU_CLUSTER_PM_EXIT:
2566 		omap3_gpmc_restore_context(gpmc);
2567 		break;
2568 	}
2569 
2570 	return NOTIFY_OK;
2571 }
2572 
2573 static int gpmc_probe(struct platform_device *pdev)
2574 {
2575 	int rc, i;
2576 	u32 l;
2577 	struct resource *res;
2578 	struct gpmc_device *gpmc;
2579 
2580 	gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2581 	if (!gpmc)
2582 		return -ENOMEM;
2583 
2584 	gpmc->dev = &pdev->dev;
2585 	platform_set_drvdata(pdev, gpmc);
2586 
2587 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
2588 	if (!res) {
2589 		/* legacy DT */
2590 		gpmc_base = devm_platform_ioremap_resource(pdev, 0);
2591 		if (IS_ERR(gpmc_base))
2592 			return PTR_ERR(gpmc_base);
2593 	} else {
2594 		gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2595 		if (IS_ERR(gpmc_base))
2596 			return PTR_ERR(gpmc_base);
2597 
2598 		res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
2599 		if (!res) {
2600 			dev_err(&pdev->dev, "couldn't get data reg resource\n");
2601 			return -ENOENT;
2602 		}
2603 
2604 		gpmc->data = res;
2605 	}
2606 
2607 	gpmc->irq = platform_get_irq(pdev, 0);
2608 	if (gpmc->irq < 0)
2609 		return gpmc->irq;
2610 
2611 	gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2612 	if (IS_ERR(gpmc_l3_clk)) {
2613 		dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2614 		return PTR_ERR(gpmc_l3_clk);
2615 	}
2616 
2617 	if (!clk_get_rate(gpmc_l3_clk)) {
2618 		dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2619 		return -EINVAL;
2620 	}
2621 
2622 	if (pdev->dev.of_node) {
2623 		rc = gpmc_probe_dt(pdev);
2624 		if (rc)
2625 			return rc;
2626 	} else {
2627 		gpmc_cs_num = GPMC_CS_NUM;
2628 		gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2629 	}
2630 
2631 	gpmc->waitpins = devm_kzalloc(&pdev->dev,
2632 				      gpmc_nr_waitpins * sizeof(struct gpmc_waitpin),
2633 				      GFP_KERNEL);
2634 	if (!gpmc->waitpins)
2635 		return -ENOMEM;
2636 
2637 	for (i = 0; i < gpmc_nr_waitpins; i++)
2638 		gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID;
2639 
2640 	pm_runtime_enable(&pdev->dev);
2641 	pm_runtime_get_sync(&pdev->dev);
2642 
2643 	l = gpmc_read_reg(GPMC_REVISION);
2644 
2645 	/*
2646 	 * FIXME: Once device-tree migration is complete the below flags
2647 	 * should be populated based upon the device-tree compatible
2648 	 * string. For now just use the IP revision. OMAP3+ devices have
2649 	 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2650 	 * devices support the addr-addr-data multiplex protocol.
2651 	 *
2652 	 * GPMC IP revisions:
2653 	 * - OMAP24xx			= 2.0
2654 	 * - OMAP3xxx			= 5.0
2655 	 * - OMAP44xx/54xx/AM335x	= 6.0
2656 	 */
2657 	if (GPMC_REVISION_MAJOR(l) > 0x4)
2658 		gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2659 	if (GPMC_REVISION_MAJOR(l) > 0x5)
2660 		gpmc_capability |= GPMC_HAS_MUX_AAD;
2661 	dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2662 		 GPMC_REVISION_MINOR(l));
2663 
2664 	gpmc_mem_init(gpmc);
2665 	rc = gpmc_gpio_init(gpmc);
2666 	if (rc)
2667 		goto gpio_init_failed;
2668 
2669 	gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2670 	rc = gpmc_setup_irq(gpmc);
2671 	if (rc) {
2672 		dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2673 		goto gpio_init_failed;
2674 	}
2675 
2676 	gpmc_probe_dt_children(pdev);
2677 
2678 	gpmc->nb.notifier_call = omap_gpmc_context_notifier;
2679 	cpu_pm_register_notifier(&gpmc->nb);
2680 
2681 	return 0;
2682 
2683 gpio_init_failed:
2684 	gpmc_mem_exit();
2685 	pm_runtime_put_sync(&pdev->dev);
2686 	pm_runtime_disable(&pdev->dev);
2687 
2688 	return rc;
2689 }
2690 
2691 static void gpmc_remove(struct platform_device *pdev)
2692 {
2693 	int i;
2694 	struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2695 
2696 	cpu_pm_unregister_notifier(&gpmc->nb);
2697 	for (i = 0; i < gpmc_nr_waitpins; i++)
2698 		gpmc_free_waitpin(gpmc, i);
2699 	gpmc_free_irq(gpmc);
2700 	gpmc_mem_exit();
2701 	pm_runtime_put_sync(&pdev->dev);
2702 	pm_runtime_disable(&pdev->dev);
2703 }
2704 
2705 #ifdef CONFIG_PM_SLEEP
2706 static int gpmc_suspend(struct device *dev)
2707 {
2708 	struct gpmc_device *gpmc = dev_get_drvdata(dev);
2709 
2710 	omap3_gpmc_save_context(gpmc);
2711 	pm_runtime_put_sync(dev);
2712 	gpmc->is_suspended = 1;
2713 
2714 	return 0;
2715 }
2716 
2717 static int gpmc_resume(struct device *dev)
2718 {
2719 	struct gpmc_device *gpmc = dev_get_drvdata(dev);
2720 
2721 	pm_runtime_get_sync(dev);
2722 	omap3_gpmc_restore_context(gpmc);
2723 	gpmc->is_suspended = 0;
2724 
2725 	return 0;
2726 }
2727 #endif
2728 
2729 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2730 
2731 #ifdef CONFIG_OF
2732 static const struct of_device_id gpmc_dt_ids[] = {
2733 	{ .compatible = "ti,omap2420-gpmc" },
2734 	{ .compatible = "ti,omap2430-gpmc" },
2735 	{ .compatible = "ti,omap3430-gpmc" },	/* omap3430 & omap3630 */
2736 	{ .compatible = "ti,omap4430-gpmc" },	/* omap4430 & omap4460 & omap543x */
2737 	{ .compatible = "ti,am3352-gpmc" },	/* am335x devices */
2738 	{ .compatible = "ti,am64-gpmc" },
2739 	{ }
2740 };
2741 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
2742 #endif
2743 
2744 static struct platform_driver gpmc_driver = {
2745 	.probe		= gpmc_probe,
2746 	.remove_new	= gpmc_remove,
2747 	.driver		= {
2748 		.name	= DEVICE_NAME,
2749 		.of_match_table = of_match_ptr(gpmc_dt_ids),
2750 		.pm	= &gpmc_pm_ops,
2751 	},
2752 };
2753 
2754 module_platform_driver(gpmc_driver);
2755 
2756 MODULE_DESCRIPTION("Texas Instruments GPMC driver");
2757 MODULE_LICENSE("GPL");
2758