1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPMC support functions 4 * 5 * Copyright (C) 2005-2006 Nokia Corporation 6 * 7 * Author: Juha Yrjola 8 * 9 * Copyright (C) 2009 Texas Instruments 10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 11 */ 12 #include <linux/cleanup.h> 13 #include <linux/cpu_pm.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/err.h> 19 #include <linux/clk.h> 20 #include <linux/ioport.h> 21 #include <linux/spinlock.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */ 25 #include <linux/gpio/machine.h> 26 #include <linux/interrupt.h> 27 #include <linux/irqdomain.h> 28 #include <linux/platform_device.h> 29 #include <linux/of.h> 30 #include <linux/of_address.h> 31 #include <linux/of_device.h> 32 #include <linux/of_platform.h> 33 #include <linux/omap-gpmc.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/sizes.h> 36 37 #include <linux/platform_data/mtd-nand-omap2.h> 38 39 #define DEVICE_NAME "omap-gpmc" 40 41 /* GPMC register offsets */ 42 #define GPMC_REVISION 0x00 43 #define GPMC_SYSCONFIG 0x10 44 #define GPMC_SYSSTATUS 0x14 45 #define GPMC_IRQSTATUS 0x18 46 #define GPMC_IRQENABLE 0x1c 47 #define GPMC_TIMEOUT_CONTROL 0x40 48 #define GPMC_ERR_ADDRESS 0x44 49 #define GPMC_ERR_TYPE 0x48 50 #define GPMC_CONFIG 0x50 51 #define GPMC_STATUS 0x54 52 #define GPMC_PREFETCH_CONFIG1 0x1e0 53 #define GPMC_PREFETCH_CONFIG2 0x1e4 54 #define GPMC_PREFETCH_CONTROL 0x1ec 55 #define GPMC_PREFETCH_STATUS 0x1f0 56 #define GPMC_ECC_CONFIG 0x1f4 57 #define GPMC_ECC_CONTROL 0x1f8 58 #define GPMC_ECC_SIZE_CONFIG 0x1fc 59 #define GPMC_ECC1_RESULT 0x200 60 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ 61 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ 62 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ 63 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ 64 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */ 65 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */ 66 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */ 67 68 /* GPMC ECC control settings */ 69 #define GPMC_ECC_CTRL_ECCCLEAR 0x100 70 #define GPMC_ECC_CTRL_ECCDISABLE 0x000 71 #define GPMC_ECC_CTRL_ECCREG1 0x001 72 #define GPMC_ECC_CTRL_ECCREG2 0x002 73 #define GPMC_ECC_CTRL_ECCREG3 0x003 74 #define GPMC_ECC_CTRL_ECCREG4 0x004 75 #define GPMC_ECC_CTRL_ECCREG5 0x005 76 #define GPMC_ECC_CTRL_ECCREG6 0x006 77 #define GPMC_ECC_CTRL_ECCREG7 0x007 78 #define GPMC_ECC_CTRL_ECCREG8 0x008 79 #define GPMC_ECC_CTRL_ECCREG9 0x009 80 81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1) 82 83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0) 84 85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) 89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) 90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) 91 92 #define GPMC_CS0_OFFSET 0x60 93 #define GPMC_CS_SIZE 0x30 94 #define GPMC_BCH_SIZE 0x10 95 96 /* 97 * The first 1MB of GPMC address space is typically mapped to 98 * the internal ROM. Never allocate the first page, to 99 * facilitate bug detection; even if we didn't boot from ROM. 100 * As GPMC minimum partition size is 16MB we can only start from 101 * there. 102 */ 103 #define GPMC_MEM_START 0x1000000 104 #define GPMC_MEM_END 0x3FFFFFFF 105 106 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ 107 #define GPMC_SECTION_SHIFT 28 /* 128 MB */ 108 109 #define CS_NUM_SHIFT 24 110 #define ENABLE_PREFETCH (0x1 << 7) 111 #define DMA_MPU_MODE 2 112 113 #define GPMC_REVISION_MAJOR(l) (((l) >> 4) & 0xf) 114 #define GPMC_REVISION_MINOR(l) ((l) & 0xf) 115 116 #define GPMC_HAS_WR_ACCESS 0x1 117 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 118 #define GPMC_HAS_MUX_AAD 0x4 119 120 #define GPMC_NR_WAITPINS 4 121 122 #define GPMC_CS_CONFIG1 0x00 123 #define GPMC_CS_CONFIG2 0x04 124 #define GPMC_CS_CONFIG3 0x08 125 #define GPMC_CS_CONFIG4 0x0c 126 #define GPMC_CS_CONFIG5 0x10 127 #define GPMC_CS_CONFIG6 0x14 128 #define GPMC_CS_CONFIG7 0x18 129 #define GPMC_CS_NAND_COMMAND 0x1c 130 #define GPMC_CS_NAND_ADDRESS 0x20 131 #define GPMC_CS_NAND_DATA 0x24 132 133 /* Control Commands */ 134 #define GPMC_CONFIG_RDY_BSY 0x00000001 135 #define GPMC_CONFIG_DEV_SIZE 0x00000002 136 #define GPMC_CONFIG_DEV_TYPE 0x00000003 137 138 #define GPMC_CONFIG_WAITPINPOLARITY(pin) (BIT(pin) << 8) 139 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) 140 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) 141 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) 142 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) 143 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) 144 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) 145 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) 146 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25) 147 /** CLKACTIVATIONTIME Max Ticks */ 148 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2 149 #define GPMC_CONFIG1_PAGE_LEN(val) (((val) & 3) << 23) 150 /** ATTACHEDDEVICEPAGELENGTH Max Value */ 151 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2 152 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) 153 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) 154 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18) 155 /** WAITMONITORINGTIME Max Ticks */ 156 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2 157 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) (((val) & 3) << 16) 158 #define GPMC_CONFIG1_DEVICESIZE(val) (((val) & 3) << 12) 159 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) 160 /** DEVICESIZE Max Value */ 161 #define GPMC_CONFIG1_DEVICESIZE_MAX 1 162 #define GPMC_CONFIG1_DEVICETYPE(val) (((val) & 3) << 10) 163 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) 164 #define GPMC_CONFIG1_MUXTYPE(val) (((val) & 3) << 8) 165 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) 166 #define GPMC_CONFIG1_FCLK_DIV(val) ((val) & 3) 167 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) 168 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) 169 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) 170 #define GPMC_CONFIG7_CSVALID (1 << 6) 171 172 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f 173 #define GPMC_CONFIG7_CSVALID_MASK BIT(6) 174 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8 175 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET) 176 /* All CONFIG7 bits except reserved bits */ 177 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \ 178 GPMC_CONFIG7_CSVALID_MASK | \ 179 GPMC_CONFIG7_MASKADDRESS_MASK) 180 181 #define GPMC_DEVICETYPE_NOR 0 182 #define GPMC_DEVICETYPE_NAND 2 183 #define GPMC_CONFIG_WRITEPROTECT 0x00000010 184 #define WR_RD_PIN_MONITORING 0x00600000 185 186 /* ECC commands */ 187 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */ 188 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */ 189 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */ 190 191 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */ 192 193 enum gpmc_clk_domain { 194 GPMC_CD_FCLK, 195 GPMC_CD_CLK 196 }; 197 198 struct gpmc_cs_data { 199 const char *name; 200 201 #define GPMC_CS_RESERVED (1 << 0) 202 u32 flags; 203 204 struct resource mem; 205 }; 206 207 /* Structure to save gpmc cs context */ 208 struct gpmc_cs_config { 209 u32 config1; 210 u32 config2; 211 u32 config3; 212 u32 config4; 213 u32 config5; 214 u32 config6; 215 u32 config7; 216 int is_valid; 217 }; 218 219 /* 220 * Structure to save/restore gpmc context 221 * to support core off on OMAP3 222 */ 223 struct omap3_gpmc_regs { 224 u32 sysconfig; 225 u32 irqenable; 226 u32 timeout_ctrl; 227 u32 config; 228 u32 prefetch_config1; 229 u32 prefetch_config2; 230 u32 prefetch_control; 231 struct gpmc_cs_config cs_context[GPMC_CS_NUM]; 232 }; 233 234 struct gpmc_waitpin { 235 u32 pin; 236 u32 polarity; 237 struct gpio_desc *desc; 238 }; 239 240 struct gpmc_device { 241 struct device *dev; 242 int irq; 243 struct irq_chip irq_chip; 244 struct gpio_chip gpio_chip; 245 struct notifier_block nb; 246 struct omap3_gpmc_regs context; 247 struct gpmc_waitpin *waitpins; 248 int nirqs; 249 unsigned int is_suspended:1; 250 struct resource *data; 251 }; 252 253 static struct irq_domain *gpmc_irq_domain; 254 255 static struct resource gpmc_mem_root; 256 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM]; 257 static DEFINE_SPINLOCK(gpmc_mem_lock); 258 /* Define chip-selects as reserved by default until probe completes */ 259 static unsigned int gpmc_cs_num = GPMC_CS_NUM; 260 static unsigned int gpmc_nr_waitpins; 261 static unsigned int gpmc_capability; 262 static void __iomem *gpmc_base; 263 264 static struct clk *gpmc_l3_clk; 265 266 static irqreturn_t gpmc_handle_irq(int irq, void *dev); 267 268 static void gpmc_write_reg(int idx, u32 val) 269 { 270 writel_relaxed(val, gpmc_base + idx); 271 } 272 273 static u32 gpmc_read_reg(int idx) 274 { 275 return readl_relaxed(gpmc_base + idx); 276 } 277 278 void gpmc_cs_write_reg(int cs, int idx, u32 val) 279 { 280 void __iomem *reg_addr; 281 282 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 283 writel_relaxed(val, reg_addr); 284 } 285 286 static u32 gpmc_cs_read_reg(int cs, int idx) 287 { 288 void __iomem *reg_addr; 289 290 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; 291 return readl_relaxed(reg_addr); 292 } 293 294 /* TODO: Add support for gpmc_fck to clock framework and use it */ 295 static unsigned long gpmc_get_fclk_period(void) 296 { 297 unsigned long rate = clk_get_rate(gpmc_l3_clk); 298 299 rate /= 1000; 300 rate = 1000000000 / rate; /* In picoseconds */ 301 302 return rate; 303 } 304 305 /** 306 * gpmc_get_clk_period - get period of selected clock domain in ps 307 * @cs: Chip Select Region. 308 * @cd: Clock Domain. 309 * 310 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup 311 * prior to calling this function with GPMC_CD_CLK. 312 */ 313 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd) 314 { 315 unsigned long tick_ps = gpmc_get_fclk_period(); 316 u32 l; 317 int div; 318 319 switch (cd) { 320 case GPMC_CD_CLK: 321 /* get current clk divider */ 322 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 323 div = (l & 0x03) + 1; 324 /* get GPMC_CLK period */ 325 tick_ps *= div; 326 break; 327 case GPMC_CD_FCLK: 328 default: 329 break; 330 } 331 332 return tick_ps; 333 } 334 335 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs, 336 enum gpmc_clk_domain cd) 337 { 338 unsigned long tick_ps; 339 340 /* Calculate in picosecs to yield more exact results */ 341 tick_ps = gpmc_get_clk_period(cs, cd); 342 343 return (time_ns * 1000 + tick_ps - 1) / tick_ps; 344 } 345 346 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) 347 { 348 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); 349 } 350 351 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) 352 { 353 unsigned long tick_ps; 354 355 /* Calculate in picosecs to yield more exact results */ 356 tick_ps = gpmc_get_fclk_period(); 357 358 return (time_ps + tick_ps - 1) / tick_ps; 359 } 360 361 static unsigned int gpmc_ticks_to_ps(unsigned int ticks) 362 { 363 return ticks * gpmc_get_fclk_period(); 364 } 365 366 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) 367 { 368 unsigned long ticks = gpmc_ps_to_ticks(time_ps); 369 370 return ticks * gpmc_get_fclk_period(); 371 } 372 373 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) 374 { 375 u32 l; 376 377 l = gpmc_cs_read_reg(cs, reg); 378 if (value) 379 l |= mask; 380 else 381 l &= ~mask; 382 gpmc_cs_write_reg(cs, reg, l); 383 } 384 385 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) 386 { 387 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, 388 GPMC_CONFIG1_TIME_PARA_GRAN, 389 p->time_para_granularity); 390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, 391 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); 392 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, 393 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); 394 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 395 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); 396 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, 397 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay); 398 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 399 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, 400 p->cycle2cyclesamecsen); 401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, 402 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, 403 p->cycle2cyclediffcsen); 404 } 405 406 #ifdef CONFIG_OMAP_GPMC_DEBUG 407 408 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs, 409 enum gpmc_clk_domain cd) 410 { 411 return ticks * gpmc_get_clk_period(cs, cd) / 1000; 412 } 413 414 /** 415 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it. 416 * @cs: Chip Select Region 417 * @reg: GPMC_CS_CONFIGn register offset. 418 * @st_bit: Start Bit 419 * @end_bit: End Bit. Must be >= @st_bit. 420 * @max: Maximum parameter value (before optional @shift). 421 * If 0, maximum is as high as @st_bit and @end_bit allow. 422 * @name: DTS node name, w/o "gpmc," 423 * @cd: Clock Domain of timing parameter. 424 * @shift: Parameter value left shifts @shift, which is then printed instead of value. 425 * @raw: Raw Format Option. 426 * raw format: gpmc,name = <value> 427 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/ 428 * Where x ns -- y ns result in the same tick value. 429 * When @max is exceeded, "invalid" is printed inside comment. 430 * @noval: Parameter values equal to 0 are not printed. 431 * @return: Specified timing parameter (after optional @shift). 432 * 433 */ 434 static int get_gpmc_timing_reg( 435 /* timing specifiers */ 436 int cs, int reg, int st_bit, int end_bit, int max, 437 const char *name, const enum gpmc_clk_domain cd, 438 /* value transform */ 439 int shift, 440 /* format specifiers */ 441 bool raw, bool noval) 442 { 443 u32 l; 444 int nr_bits; 445 int mask; 446 bool invalid; 447 448 l = gpmc_cs_read_reg(cs, reg); 449 nr_bits = end_bit - st_bit + 1; 450 mask = (1 << nr_bits) - 1; 451 l = (l >> st_bit) & mask; 452 if (!max) 453 max = mask; 454 invalid = l > max; 455 if (shift) 456 l = (shift << l); 457 if (noval && (l == 0)) 458 return 0; 459 if (!raw) { 460 /* DTS tick format for timings in ns */ 461 unsigned int time_ns; 462 unsigned int time_ns_min = 0; 463 464 if (l) 465 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1; 466 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd); 467 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n", 468 name, time_ns, time_ns_min, time_ns, l, 469 invalid ? "; invalid " : " "); 470 } else { 471 /* raw format */ 472 pr_info("gpmc,%s = <%u>;%s\n", name, l, 473 invalid ? " /* invalid */" : ""); 474 } 475 476 return l; 477 } 478 479 #define GPMC_PRINT_CONFIG(cs, config) \ 480 pr_info("cs%i %s: 0x%08x\n", cs, #config, \ 481 gpmc_cs_read_reg(cs, config)) 482 #define GPMC_GET_RAW(reg, st, end, field) \ 483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0) 484 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \ 485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0) 486 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \ 487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1) 488 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \ 489 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1) 490 #define GPMC_GET_TICKS(reg, st, end, field) \ 491 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0) 492 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \ 493 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0) 494 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \ 495 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0) 496 497 static void gpmc_show_regs(int cs, const char *desc) 498 { 499 pr_info("gpmc cs%i %s:\n", cs, desc); 500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1); 501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2); 502 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3); 503 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4); 504 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5); 505 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6); 506 } 507 508 /* 509 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available, 510 * see commit c9fb809. 511 */ 512 static void gpmc_cs_show_timings(int cs, const char *desc) 513 { 514 gpmc_show_regs(cs, desc); 515 516 pr_info("gpmc cs%i access configuration:\n", cs); 517 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity"); 518 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); 519 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1, 520 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width"); 521 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin"); 522 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write"); 523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read"); 524 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4, 525 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX, 526 "burst-length"); 527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write"); 528 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write"); 529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read"); 530 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read"); 531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap"); 532 533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay"); 534 535 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay"); 536 537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay"); 538 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay"); 539 540 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen"); 541 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen"); 542 543 pr_info("gpmc cs%i timings configuration:\n", cs); 544 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns"); 545 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns"); 546 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns"); 547 548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns"); 549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns"); 550 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns"); 551 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 552 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns"); 553 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26, 554 "adv-aad-mux-rd-off-ns"); 555 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30, 556 "adv-aad-mux-wr-off-ns"); 557 } 558 559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns"); 560 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns"); 561 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns"); 563 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns"); 564 } 565 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns"); 566 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns"); 567 568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns"); 569 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns"); 570 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns"); 571 572 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns"); 573 574 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns"); 575 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns"); 576 577 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19, 578 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 579 "wait-monitoring-ns", GPMC_CD_CLK); 580 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26, 581 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 582 "clk-activation-ns", GPMC_CD_FCLK); 583 584 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); 585 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns"); 586 } 587 #else 588 static inline void gpmc_cs_show_timings(int cs, const char *desc) 589 { 590 } 591 #endif 592 593 /** 594 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region. 595 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER 596 * prior to calling this function with @cd equal to GPMC_CD_CLK. 597 * 598 * @cs: Chip Select Region. 599 * @reg: GPMC_CS_CONFIGn register offset. 600 * @st_bit: Start Bit 601 * @end_bit: End Bit. Must be >= @st_bit. 602 * @max: Maximum parameter value. 603 * If 0, maximum is as high as @st_bit and @end_bit allow. 604 * @time: Timing parameter in ns. 605 * @cd: Timing parameter clock domain. 606 * @name: Timing parameter name. 607 * @return: 0 on success, -1 on error. 608 */ 609 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max, 610 int time, enum gpmc_clk_domain cd, const char *name) 611 { 612 u32 l; 613 int ticks, mask, nr_bits; 614 615 if (time == 0) 616 ticks = 0; 617 else 618 ticks = gpmc_ns_to_clk_ticks(time, cs, cd); 619 nr_bits = end_bit - st_bit + 1; 620 mask = (1 << nr_bits) - 1; 621 622 if (!max) 623 max = mask; 624 625 if (ticks > max) { 626 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", 627 __func__, cs, name, time, ticks, max); 628 629 return -1; 630 } 631 632 l = gpmc_cs_read_reg(cs, reg); 633 #ifdef CONFIG_OMAP_GPMC_DEBUG 634 pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", 635 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000, 636 (l >> st_bit) & mask, time); 637 #endif 638 l &= ~(mask << st_bit); 639 l |= ticks << st_bit; 640 gpmc_cs_write_reg(cs, reg, l); 641 642 return 0; 643 } 644 645 /** 646 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME 647 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e. 648 * read --> don't sample bus too early 649 * write --> data is longer on bus 650 * 651 * Formula: 652 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns) 653 * / waitmonitoring_ticks) 654 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by 655 * div <= 0 check. 656 * 657 * @wait_monitoring: WAITMONITORINGTIME in ns. 658 * @return: -1 on failure to scale, else proper divider > 0. 659 */ 660 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring) 661 { 662 int div = gpmc_ns_to_ticks(wait_monitoring); 663 664 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1; 665 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX; 666 667 if (div > 4) 668 return -1; 669 if (div <= 0) 670 div = 1; 671 672 return div; 673 } 674 675 /** 676 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period. 677 * @sync_clk: GPMC_CLK period in ps. 678 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK. 679 * Else, returns -1. 680 */ 681 int gpmc_calc_divider(unsigned int sync_clk) 682 { 683 int div = gpmc_ps_to_ticks(sync_clk); 684 685 if (div > 4) 686 return -1; 687 if (div <= 0) 688 div = 1; 689 690 return div; 691 } 692 693 /** 694 * gpmc_cs_set_timings - program timing parameters for Chip Select Region. 695 * @cs: Chip Select Region. 696 * @t: GPMC timing parameters. 697 * @s: GPMC timing settings. 698 * @return: 0 on success, -1 on error. 699 */ 700 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t, 701 const struct gpmc_settings *s) 702 { 703 int div, ret; 704 u32 l; 705 706 div = gpmc_calc_divider(t->sync_clk); 707 if (div < 0) 708 return -EINVAL; 709 710 /* 711 * See if we need to change the divider for waitmonitoringtime. 712 * 713 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for 714 * pure asynchronous accesses, i.e. both read and write asynchronous. 715 * However, only do so if WAITMONITORINGTIME is actually used, i.e. 716 * either WAITREADMONITORING or WAITWRITEMONITORING is set. 717 * 718 * This statement must not change div to scale async WAITMONITORINGTIME 719 * to protect mixed synchronous and asynchronous accesses. 720 * 721 * We raise an error later if WAITMONITORINGTIME does not fit. 722 */ 723 if (!s->sync_read && !s->sync_write && 724 (s->wait_on_read || s->wait_on_write) 725 ) { 726 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring); 727 if (div < 0) { 728 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n", 729 __func__, 730 t->wait_monitoring 731 ); 732 return -ENXIO; 733 } 734 } 735 736 ret = 0; 737 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on, 738 GPMC_CD_FCLK, "cs_on"); 739 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off, 740 GPMC_CD_FCLK, "cs_rd_off"); 741 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off, 742 GPMC_CD_FCLK, "cs_wr_off"); 743 if (ret) 744 return -ENXIO; 745 746 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on, 747 GPMC_CD_FCLK, "adv_on"); 748 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off, 749 GPMC_CD_FCLK, "adv_rd_off"); 750 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off, 751 GPMC_CD_FCLK, "adv_wr_off"); 752 if (ret) 753 return -ENXIO; 754 755 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 756 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0, 757 t->adv_aad_mux_on, GPMC_CD_FCLK, 758 "adv_aad_mux_on"); 759 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0, 760 t->adv_aad_mux_rd_off, GPMC_CD_FCLK, 761 "adv_aad_mux_rd_off"); 762 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0, 763 t->adv_aad_mux_wr_off, GPMC_CD_FCLK, 764 "adv_aad_mux_wr_off"); 765 if (ret) 766 return -ENXIO; 767 } 768 769 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on, 770 GPMC_CD_FCLK, "oe_on"); 771 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off, 772 GPMC_CD_FCLK, "oe_off"); 773 if (gpmc_capability & GPMC_HAS_MUX_AAD) { 774 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0, 775 t->oe_aad_mux_on, GPMC_CD_FCLK, 776 "oe_aad_mux_on"); 777 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0, 778 t->oe_aad_mux_off, GPMC_CD_FCLK, 779 "oe_aad_mux_off"); 780 } 781 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on, 782 GPMC_CD_FCLK, "we_on"); 783 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off, 784 GPMC_CD_FCLK, "we_off"); 785 if (ret) 786 return -ENXIO; 787 788 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle, 789 GPMC_CD_FCLK, "rd_cycle"); 790 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle, 791 GPMC_CD_FCLK, "wr_cycle"); 792 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access, 793 GPMC_CD_FCLK, "access"); 794 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0, 795 t->page_burst_access, GPMC_CD_FCLK, 796 "page_burst_access"); 797 if (ret) 798 return -ENXIO; 799 800 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0, 801 t->bus_turnaround, GPMC_CD_FCLK, 802 "bus_turnaround"); 803 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0, 804 t->cycle2cycle_delay, GPMC_CD_FCLK, 805 "cycle2cycle_delay"); 806 if (ret) 807 return -ENXIO; 808 809 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) { 810 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0, 811 t->wr_data_mux_bus, GPMC_CD_FCLK, 812 "wr_data_mux_bus"); 813 if (ret) 814 return -ENXIO; 815 } 816 if (gpmc_capability & GPMC_HAS_WR_ACCESS) { 817 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0, 818 t->wr_access, GPMC_CD_FCLK, 819 "wr_access"); 820 if (ret) 821 return -ENXIO; 822 } 823 824 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); 825 l &= ~0x03; 826 l |= (div - 1); 827 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); 828 829 ret = 0; 830 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19, 831 GPMC_CONFIG1_WAITMONITORINGTIME_MAX, 832 t->wait_monitoring, GPMC_CD_CLK, 833 "wait_monitoring"); 834 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26, 835 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX, 836 t->clk_activation, GPMC_CD_FCLK, 837 "clk_activation"); 838 if (ret) 839 return -ENXIO; 840 841 #ifdef CONFIG_OMAP_GPMC_DEBUG 842 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", 843 cs, (div * gpmc_get_fclk_period()) / 1000, div); 844 #endif 845 846 gpmc_cs_bool_timings(cs, &t->bool_timings); 847 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings"); 848 849 return 0; 850 } 851 852 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size) 853 { 854 u32 l; 855 u32 mask; 856 857 /* 858 * Ensure that base address is aligned on a 859 * boundary equal to or greater than size. 860 */ 861 if (base & (size - 1)) 862 return -EINVAL; 863 864 base >>= GPMC_CHUNK_SHIFT; 865 mask = (1 << GPMC_SECTION_SHIFT) - size; 866 mask >>= GPMC_CHUNK_SHIFT; 867 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET; 868 869 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 870 l &= ~GPMC_CONFIG7_MASK; 871 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK; 872 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK; 873 l |= GPMC_CONFIG7_CSVALID; 874 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 875 876 return 0; 877 } 878 879 static void gpmc_cs_enable_mem(int cs) 880 { 881 u32 l; 882 883 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 884 l |= GPMC_CONFIG7_CSVALID; 885 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 886 } 887 888 static void gpmc_cs_disable_mem(int cs) 889 { 890 u32 l; 891 892 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 893 l &= ~GPMC_CONFIG7_CSVALID; 894 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); 895 } 896 897 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) 898 { 899 u32 l; 900 u32 mask; 901 902 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 903 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; 904 mask = (l >> 8) & 0x0f; 905 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); 906 } 907 908 static int gpmc_cs_mem_enabled(int cs) 909 { 910 u32 l; 911 912 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); 913 return l & GPMC_CONFIG7_CSVALID; 914 } 915 916 static void gpmc_cs_set_reserved(int cs, int reserved) 917 { 918 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 919 920 gpmc->flags |= GPMC_CS_RESERVED; 921 } 922 923 static bool gpmc_cs_reserved(int cs) 924 { 925 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 926 927 return gpmc->flags & GPMC_CS_RESERVED; 928 } 929 930 static unsigned long gpmc_mem_align(unsigned long size) 931 { 932 int order; 933 934 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); 935 order = GPMC_CHUNK_SHIFT - 1; 936 do { 937 size >>= 1; 938 order++; 939 } while (size); 940 size = 1 << order; 941 return size; 942 } 943 944 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 945 { 946 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 947 struct resource *res = &gpmc->mem; 948 int r; 949 950 size = gpmc_mem_align(size); 951 spin_lock(&gpmc_mem_lock); 952 res->start = base; 953 res->end = base + size - 1; 954 r = request_resource(&gpmc_mem_root, res); 955 spin_unlock(&gpmc_mem_lock); 956 957 return r; 958 } 959 960 static int gpmc_cs_delete_mem(int cs) 961 { 962 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 963 struct resource *res = &gpmc->mem; 964 int r; 965 966 spin_lock(&gpmc_mem_lock); 967 r = release_resource(res); 968 res->start = 0; 969 res->end = 0; 970 spin_unlock(&gpmc_mem_lock); 971 972 return r; 973 } 974 975 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 976 { 977 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 978 struct resource *res = &gpmc->mem; 979 int r = -1; 980 981 if (cs >= gpmc_cs_num) { 982 pr_err("%s: requested chip-select is disabled\n", __func__); 983 return -ENODEV; 984 } 985 size = gpmc_mem_align(size); 986 if (size > (1 << GPMC_SECTION_SHIFT)) 987 return -ENOMEM; 988 989 guard(spinlock)(&gpmc_mem_lock); 990 991 if (gpmc_cs_reserved(cs)) 992 return -EBUSY; 993 994 if (gpmc_cs_mem_enabled(cs)) 995 r = adjust_resource(res, res->start & ~(size - 1), size); 996 if (r < 0) 997 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, 998 size, NULL, NULL); 999 if (r < 0) 1000 return r; 1001 1002 /* Disable CS while changing base address and size mask */ 1003 gpmc_cs_disable_mem(cs); 1004 1005 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res)); 1006 if (r < 0) { 1007 release_resource(res); 1008 return r; 1009 } 1010 1011 /* Enable CS */ 1012 gpmc_cs_enable_mem(cs); 1013 *base = res->start; 1014 gpmc_cs_set_reserved(cs, 1); 1015 1016 return 0; 1017 } 1018 EXPORT_SYMBOL(gpmc_cs_request); 1019 1020 void gpmc_cs_free(int cs) 1021 { 1022 struct gpmc_cs_data *gpmc; 1023 struct resource *res; 1024 1025 guard(spinlock)(&gpmc_mem_lock); 1026 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 1027 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs); 1028 return; 1029 } 1030 gpmc = &gpmc_cs[cs]; 1031 res = &gpmc->mem; 1032 1033 gpmc_cs_disable_mem(cs); 1034 if (res->flags) 1035 release_resource(res); 1036 gpmc_cs_set_reserved(cs, 0); 1037 } 1038 EXPORT_SYMBOL(gpmc_cs_free); 1039 1040 static bool gpmc_is_valid_waitpin(u32 waitpin) 1041 { 1042 return waitpin < gpmc_nr_waitpins; 1043 } 1044 1045 static int gpmc_alloc_waitpin(struct gpmc_device *gpmc, 1046 struct gpmc_settings *p) 1047 { 1048 int ret; 1049 struct gpmc_waitpin *waitpin; 1050 struct gpio_desc *waitpin_desc; 1051 1052 if (!gpmc_is_valid_waitpin(p->wait_pin)) 1053 return -EINVAL; 1054 1055 waitpin = &gpmc->waitpins[p->wait_pin]; 1056 1057 if (!waitpin->desc) { 1058 /* Reserve the GPIO for wait pin usage. 1059 * GPIO polarity doesn't matter here. Wait pin polarity 1060 * is set in GPMC_CONFIG register. 1061 */ 1062 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip, 1063 p->wait_pin, "WAITPIN", 1064 GPIO_ACTIVE_HIGH, 1065 GPIOD_IN); 1066 1067 ret = PTR_ERR(waitpin_desc); 1068 if (IS_ERR(waitpin_desc) && ret != -EBUSY) 1069 return ret; 1070 1071 /* New wait pin */ 1072 waitpin->desc = waitpin_desc; 1073 waitpin->pin = p->wait_pin; 1074 waitpin->polarity = p->wait_pin_polarity; 1075 } else { 1076 /* Shared wait pin */ 1077 if (p->wait_pin_polarity != waitpin->polarity || 1078 p->wait_pin != waitpin->pin) { 1079 dev_err(gpmc->dev, 1080 "shared-wait-pin: invalid configuration\n"); 1081 return -EINVAL; 1082 } 1083 dev_info(gpmc->dev, "shared wait-pin: %d\n", waitpin->pin); 1084 } 1085 1086 return 0; 1087 } 1088 1089 static void gpmc_free_waitpin(struct gpmc_device *gpmc, 1090 int wait_pin) 1091 { 1092 if (gpmc_is_valid_waitpin(wait_pin)) 1093 gpiochip_free_own_desc(gpmc->waitpins[wait_pin].desc); 1094 } 1095 1096 /** 1097 * gpmc_configure - write request to configure gpmc 1098 * @cmd: command type 1099 * @wval: value to write 1100 * @return status of the operation 1101 */ 1102 int gpmc_configure(int cmd, int wval) 1103 { 1104 u32 regval; 1105 1106 switch (cmd) { 1107 case GPMC_CONFIG_WP: 1108 regval = gpmc_read_reg(GPMC_CONFIG); 1109 if (wval) 1110 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ 1111 else 1112 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ 1113 gpmc_write_reg(GPMC_CONFIG, regval); 1114 break; 1115 1116 default: 1117 pr_err("%s: command not supported\n", __func__); 1118 return -EINVAL; 1119 } 1120 1121 return 0; 1122 } 1123 EXPORT_SYMBOL(gpmc_configure); 1124 1125 static bool gpmc_nand_writebuffer_empty(void) 1126 { 1127 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS) 1128 return true; 1129 1130 return false; 1131 } 1132 1133 static struct gpmc_nand_ops nand_ops = { 1134 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty, 1135 }; 1136 1137 /** 1138 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface 1139 * @reg: the GPMC NAND register map exclusive for NAND use. 1140 * @cs: GPMC chip select number on which the NAND sits. The 1141 * register map returned will be specific to this chip select. 1142 * 1143 * Returns NULL on error e.g. invalid cs. 1144 */ 1145 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs) 1146 { 1147 int i; 1148 1149 if (cs >= gpmc_cs_num) 1150 return NULL; 1151 1152 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + 1153 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; 1154 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + 1155 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; 1156 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + 1157 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; 1158 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; 1159 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; 1160 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; 1161 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; 1162 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; 1163 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; 1164 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; 1165 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; 1166 1167 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { 1168 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + 1169 GPMC_BCH_SIZE * i; 1170 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + 1171 GPMC_BCH_SIZE * i; 1172 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + 1173 GPMC_BCH_SIZE * i; 1174 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + 1175 GPMC_BCH_SIZE * i; 1176 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 + 1177 i * GPMC_BCH_SIZE; 1178 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 + 1179 i * GPMC_BCH_SIZE; 1180 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 + 1181 i * GPMC_BCH_SIZE; 1182 } 1183 1184 return &nand_ops; 1185 } 1186 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops); 1187 1188 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t, 1189 struct gpmc_settings *s, 1190 int freq, int latency) 1191 { 1192 struct gpmc_device_timings dev_t; 1193 const int t_cer = 15; 1194 const int t_avdp = 12; 1195 const int t_cez = 20; /* max of t_cez, t_oez */ 1196 const int t_wpl = 40; 1197 const int t_wph = 30; 1198 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo; 1199 1200 switch (freq) { 1201 case 104: 1202 min_gpmc_clk_period = 9600; /* 104 MHz */ 1203 t_ces = 3; 1204 t_avds = 4; 1205 t_avdh = 2; 1206 t_ach = 3; 1207 t_aavdh = 6; 1208 t_rdyo = 6; 1209 break; 1210 case 83: 1211 min_gpmc_clk_period = 12000; /* 83 MHz */ 1212 t_ces = 5; 1213 t_avds = 4; 1214 t_avdh = 2; 1215 t_ach = 6; 1216 t_aavdh = 6; 1217 t_rdyo = 9; 1218 break; 1219 case 66: 1220 min_gpmc_clk_period = 15000; /* 66 MHz */ 1221 t_ces = 6; 1222 t_avds = 5; 1223 t_avdh = 2; 1224 t_ach = 6; 1225 t_aavdh = 6; 1226 t_rdyo = 11; 1227 break; 1228 default: 1229 min_gpmc_clk_period = 18500; /* 54 MHz */ 1230 t_ces = 7; 1231 t_avds = 7; 1232 t_avdh = 7; 1233 t_ach = 9; 1234 t_aavdh = 7; 1235 t_rdyo = 15; 1236 break; 1237 } 1238 1239 /* Set synchronous read timings */ 1240 memset(&dev_t, 0, sizeof(dev_t)); 1241 1242 if (!s->sync_write) { 1243 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000; 1244 dev_t.t_wpl = t_wpl * 1000; 1245 dev_t.t_wph = t_wph * 1000; 1246 dev_t.t_aavdh = t_aavdh * 1000; 1247 } 1248 dev_t.ce_xdelay = true; 1249 dev_t.avd_xdelay = true; 1250 dev_t.oe_xdelay = true; 1251 dev_t.we_xdelay = true; 1252 dev_t.clk = min_gpmc_clk_period; 1253 dev_t.t_bacc = dev_t.clk; 1254 dev_t.t_ces = t_ces * 1000; 1255 dev_t.t_avds = t_avds * 1000; 1256 dev_t.t_avdh = t_avdh * 1000; 1257 dev_t.t_ach = t_ach * 1000; 1258 dev_t.cyc_iaa = (latency + 1); 1259 dev_t.t_cez_r = t_cez * 1000; 1260 dev_t.t_cez_w = dev_t.t_cez_r; 1261 dev_t.cyc_aavdh_oe = 1; 1262 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period; 1263 1264 gpmc_calc_timings(t, s, &dev_t); 1265 } 1266 1267 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq, 1268 int latency, 1269 struct gpmc_onenand_info *info) 1270 { 1271 int ret; 1272 struct gpmc_timings gpmc_t; 1273 struct gpmc_settings gpmc_s; 1274 1275 gpmc_read_settings_dt(dev->of_node, &gpmc_s); 1276 1277 info->sync_read = gpmc_s.sync_read; 1278 info->sync_write = gpmc_s.sync_write; 1279 info->burst_len = gpmc_s.burst_len; 1280 1281 if (!gpmc_s.sync_read && !gpmc_s.sync_write) 1282 return 0; 1283 1284 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency); 1285 1286 ret = gpmc_cs_program_settings(cs, &gpmc_s); 1287 if (ret < 0) 1288 return ret; 1289 1290 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 1291 } 1292 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings); 1293 1294 static int gpmc_irq_endis(unsigned long hwirq, bool endis) 1295 { 1296 u32 regval; 1297 1298 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */ 1299 if (hwirq >= GPMC_NR_NAND_IRQS) 1300 hwirq += 8 - GPMC_NR_NAND_IRQS; 1301 1302 regval = gpmc_read_reg(GPMC_IRQENABLE); 1303 if (endis) 1304 regval |= BIT(hwirq); 1305 else 1306 regval &= ~BIT(hwirq); 1307 gpmc_write_reg(GPMC_IRQENABLE, regval); 1308 1309 return 0; 1310 } 1311 1312 static void gpmc_irq_disable(struct irq_data *p) 1313 { 1314 gpmc_irq_endis(p->hwirq, false); 1315 } 1316 1317 static void gpmc_irq_enable(struct irq_data *p) 1318 { 1319 gpmc_irq_endis(p->hwirq, true); 1320 } 1321 1322 static void gpmc_irq_mask(struct irq_data *d) 1323 { 1324 gpmc_irq_endis(d->hwirq, false); 1325 } 1326 1327 static void gpmc_irq_unmask(struct irq_data *d) 1328 { 1329 gpmc_irq_endis(d->hwirq, true); 1330 } 1331 1332 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge) 1333 { 1334 u32 regval; 1335 1336 /* NAND IRQs polarity is not configurable */ 1337 if (hwirq < GPMC_NR_NAND_IRQS) 1338 return; 1339 1340 /* WAITPIN starts at BIT 8 */ 1341 hwirq += 8 - GPMC_NR_NAND_IRQS; 1342 1343 regval = gpmc_read_reg(GPMC_CONFIG); 1344 if (rising_edge) 1345 regval &= ~BIT(hwirq); 1346 else 1347 regval |= BIT(hwirq); 1348 1349 gpmc_write_reg(GPMC_CONFIG, regval); 1350 } 1351 1352 static void gpmc_irq_ack(struct irq_data *d) 1353 { 1354 unsigned int hwirq = d->hwirq; 1355 1356 /* skip reserved bits */ 1357 if (hwirq >= GPMC_NR_NAND_IRQS) 1358 hwirq += 8 - GPMC_NR_NAND_IRQS; 1359 1360 /* Setting bit to 1 clears (or Acks) the interrupt */ 1361 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq)); 1362 } 1363 1364 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger) 1365 { 1366 /* can't set type for NAND IRQs */ 1367 if (d->hwirq < GPMC_NR_NAND_IRQS) 1368 return -EINVAL; 1369 1370 /* We can support either rising or falling edge at a time */ 1371 if (trigger == IRQ_TYPE_EDGE_FALLING) 1372 gpmc_irq_edge_config(d->hwirq, false); 1373 else if (trigger == IRQ_TYPE_EDGE_RISING) 1374 gpmc_irq_edge_config(d->hwirq, true); 1375 else 1376 return -EINVAL; 1377 1378 return 0; 1379 } 1380 1381 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq, 1382 irq_hw_number_t hw) 1383 { 1384 struct gpmc_device *gpmc = d->host_data; 1385 1386 irq_set_chip_data(virq, gpmc); 1387 if (hw < GPMC_NR_NAND_IRQS) { 1388 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN); 1389 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1390 handle_simple_irq); 1391 } else { 1392 irq_set_chip_and_handler(virq, &gpmc->irq_chip, 1393 handle_edge_irq); 1394 } 1395 1396 return 0; 1397 } 1398 1399 static const struct irq_domain_ops gpmc_irq_domain_ops = { 1400 .map = gpmc_irq_map, 1401 .xlate = irq_domain_xlate_twocell, 1402 }; 1403 1404 static irqreturn_t gpmc_handle_irq(int irq, void *data) 1405 { 1406 int hwirq, virq; 1407 u32 regval, regvalx; 1408 struct gpmc_device *gpmc = data; 1409 1410 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1411 regvalx = regval; 1412 1413 if (!regval) 1414 return IRQ_NONE; 1415 1416 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) { 1417 /* skip reserved status bits */ 1418 if (hwirq == GPMC_NR_NAND_IRQS) 1419 regvalx >>= 8 - GPMC_NR_NAND_IRQS; 1420 1421 if (regvalx & BIT(hwirq)) { 1422 virq = irq_find_mapping(gpmc_irq_domain, hwirq); 1423 if (!virq) { 1424 dev_warn(gpmc->dev, 1425 "spurious irq detected hwirq %d, virq %d\n", 1426 hwirq, virq); 1427 } 1428 1429 generic_handle_irq(virq); 1430 } 1431 } 1432 1433 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1434 1435 return IRQ_HANDLED; 1436 } 1437 1438 static int gpmc_setup_irq(struct gpmc_device *gpmc) 1439 { 1440 u32 regval; 1441 int rc; 1442 1443 /* Disable interrupts */ 1444 gpmc_write_reg(GPMC_IRQENABLE, 0); 1445 1446 /* clear interrupts */ 1447 regval = gpmc_read_reg(GPMC_IRQSTATUS); 1448 gpmc_write_reg(GPMC_IRQSTATUS, regval); 1449 1450 gpmc->irq_chip.name = "gpmc"; 1451 gpmc->irq_chip.irq_enable = gpmc_irq_enable; 1452 gpmc->irq_chip.irq_disable = gpmc_irq_disable; 1453 gpmc->irq_chip.irq_ack = gpmc_irq_ack; 1454 gpmc->irq_chip.irq_mask = gpmc_irq_mask; 1455 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask; 1456 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type; 1457 1458 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node, 1459 gpmc->nirqs, 1460 &gpmc_irq_domain_ops, 1461 gpmc); 1462 if (!gpmc_irq_domain) { 1463 dev_err(gpmc->dev, "IRQ domain add failed\n"); 1464 return -ENODEV; 1465 } 1466 1467 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc); 1468 if (rc) { 1469 dev_err(gpmc->dev, "failed to request irq %d: %d\n", 1470 gpmc->irq, rc); 1471 irq_domain_remove(gpmc_irq_domain); 1472 gpmc_irq_domain = NULL; 1473 } 1474 1475 return rc; 1476 } 1477 1478 static int gpmc_free_irq(struct gpmc_device *gpmc) 1479 { 1480 int hwirq; 1481 1482 free_irq(gpmc->irq, gpmc); 1483 1484 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) 1485 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq)); 1486 1487 irq_domain_remove(gpmc_irq_domain); 1488 gpmc_irq_domain = NULL; 1489 1490 return 0; 1491 } 1492 1493 static void gpmc_mem_exit(void) 1494 { 1495 int cs; 1496 1497 for (cs = 0; cs < gpmc_cs_num; cs++) { 1498 if (!gpmc_cs_mem_enabled(cs)) 1499 continue; 1500 gpmc_cs_delete_mem(cs); 1501 } 1502 } 1503 1504 static void gpmc_mem_init(struct gpmc_device *gpmc) 1505 { 1506 int cs; 1507 1508 if (!gpmc->data) { 1509 /* All legacy devices have same data IO window */ 1510 gpmc_mem_root.start = GPMC_MEM_START; 1511 gpmc_mem_root.end = GPMC_MEM_END; 1512 } else { 1513 gpmc_mem_root.start = gpmc->data->start; 1514 gpmc_mem_root.end = gpmc->data->end; 1515 } 1516 1517 /* Reserve all regions that has been set up by bootloader */ 1518 for (cs = 0; cs < gpmc_cs_num; cs++) { 1519 u32 base, size; 1520 1521 if (!gpmc_cs_mem_enabled(cs)) 1522 continue; 1523 gpmc_cs_get_memconf(cs, &base, &size); 1524 if (gpmc_cs_insert_mem(cs, base, size)) { 1525 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n", 1526 __func__, cs, base, base + size); 1527 gpmc_cs_disable_mem(cs); 1528 } 1529 } 1530 } 1531 1532 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) 1533 { 1534 u32 temp; 1535 int div; 1536 1537 div = gpmc_calc_divider(sync_clk); 1538 temp = gpmc_ps_to_ticks(time_ps); 1539 temp = (temp + div - 1) / div; 1540 return gpmc_ticks_to_ps(temp * div); 1541 } 1542 1543 /* XXX: can the cycles be avoided ? */ 1544 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, 1545 struct gpmc_device_timings *dev_t, 1546 bool mux) 1547 { 1548 u32 temp; 1549 1550 /* adv_rd_off */ 1551 temp = dev_t->t_avdp_r; 1552 /* XXX: mux check required ? */ 1553 if (mux) { 1554 /* XXX: t_avdp not to be required for sync, only added for tusb 1555 * this indirectly necessitates requirement of t_avdp_r and 1556 * t_avdp_w instead of having a single t_avdp 1557 */ 1558 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); 1559 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1560 } 1561 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1562 1563 /* oe_on */ 1564 temp = dev_t->t_oeasu; /* XXX: remove this ? */ 1565 if (mux) { 1566 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); 1567 temp = max_t(u32, temp, gpmc_t->adv_rd_off + 1568 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); 1569 } 1570 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1571 1572 /* access */ 1573 /* XXX: any scope for improvement ?, by combining oe_on 1574 * and clk_activation, need to check whether 1575 * access = clk_activation + round to sync clk ? 1576 */ 1577 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); 1578 temp += gpmc_t->clk_activation; 1579 if (dev_t->cyc_oe) 1580 temp = max_t(u32, temp, gpmc_t->oe_on + 1581 gpmc_ticks_to_ps(dev_t->cyc_oe)); 1582 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1583 1584 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1585 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1586 1587 /* rd_cycle */ 1588 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); 1589 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + 1590 gpmc_t->access; 1591 /* XXX: barter t_ce_rdyz with t_cez_r ? */ 1592 if (dev_t->t_ce_rdyz) 1593 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); 1594 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1595 1596 return 0; 1597 } 1598 1599 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, 1600 struct gpmc_device_timings *dev_t, 1601 bool mux) 1602 { 1603 u32 temp; 1604 1605 /* adv_wr_off */ 1606 temp = dev_t->t_avdp_w; 1607 if (mux) { 1608 temp = max_t(u32, temp, 1609 gpmc_t->clk_activation + dev_t->t_avdh); 1610 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1611 } 1612 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1613 1614 /* wr_data_mux_bus */ 1615 temp = max_t(u32, dev_t->t_weasu, 1616 gpmc_t->clk_activation + dev_t->t_rdyo); 1617 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, 1618 * and in that case remember to handle we_on properly 1619 */ 1620 if (mux) { 1621 temp = max_t(u32, temp, 1622 gpmc_t->adv_wr_off + dev_t->t_aavdh); 1623 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1624 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1625 } 1626 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1627 1628 /* we_on */ 1629 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1630 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1631 else 1632 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1633 1634 /* wr_access */ 1635 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ 1636 gpmc_t->wr_access = gpmc_t->access; 1637 1638 /* we_off */ 1639 temp = gpmc_t->we_on + dev_t->t_wpl; 1640 temp = max_t(u32, temp, 1641 gpmc_t->wr_access + gpmc_ticks_to_ps(1)); 1642 temp = max_t(u32, temp, 1643 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); 1644 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1645 1646 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1647 dev_t->t_wph); 1648 1649 /* wr_cycle */ 1650 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); 1651 temp += gpmc_t->wr_access; 1652 /* XXX: barter t_ce_rdyz with t_cez_w ? */ 1653 if (dev_t->t_ce_rdyz) 1654 temp = max_t(u32, temp, 1655 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); 1656 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1657 1658 return 0; 1659 } 1660 1661 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, 1662 struct gpmc_device_timings *dev_t, 1663 bool mux) 1664 { 1665 u32 temp; 1666 1667 /* adv_rd_off */ 1668 temp = dev_t->t_avdp_r; 1669 if (mux) 1670 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1671 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); 1672 1673 /* oe_on */ 1674 temp = dev_t->t_oeasu; 1675 if (mux) 1676 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh); 1677 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); 1678 1679 /* access */ 1680 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ 1681 gpmc_t->oe_on + dev_t->t_oe); 1682 temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce); 1683 temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa); 1684 gpmc_t->access = gpmc_round_ps_to_ticks(temp); 1685 1686 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); 1687 gpmc_t->cs_rd_off = gpmc_t->oe_off; 1688 1689 /* rd_cycle */ 1690 temp = max_t(u32, dev_t->t_rd_cycle, 1691 gpmc_t->cs_rd_off + dev_t->t_cez_r); 1692 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); 1693 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); 1694 1695 return 0; 1696 } 1697 1698 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, 1699 struct gpmc_device_timings *dev_t, 1700 bool mux) 1701 { 1702 u32 temp; 1703 1704 /* adv_wr_off */ 1705 temp = dev_t->t_avdp_w; 1706 if (mux) 1707 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); 1708 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); 1709 1710 /* wr_data_mux_bus */ 1711 temp = dev_t->t_weasu; 1712 if (mux) { 1713 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); 1714 temp = max_t(u32, temp, gpmc_t->adv_wr_off + 1715 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); 1716 } 1717 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); 1718 1719 /* we_on */ 1720 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) 1721 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); 1722 else 1723 gpmc_t->we_on = gpmc_t->wr_data_mux_bus; 1724 1725 /* we_off */ 1726 temp = gpmc_t->we_on + dev_t->t_wpl; 1727 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); 1728 1729 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + 1730 dev_t->t_wph); 1731 1732 /* wr_cycle */ 1733 temp = max_t(u32, dev_t->t_wr_cycle, 1734 gpmc_t->cs_wr_off + dev_t->t_cez_w); 1735 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); 1736 1737 return 0; 1738 } 1739 1740 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, 1741 struct gpmc_device_timings *dev_t) 1742 { 1743 u32 temp; 1744 1745 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * 1746 gpmc_get_fclk_period(); 1747 1748 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( 1749 dev_t->t_bacc, 1750 gpmc_t->sync_clk); 1751 1752 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); 1753 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); 1754 1755 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) 1756 return 0; 1757 1758 if (dev_t->ce_xdelay) 1759 gpmc_t->bool_timings.cs_extra_delay = true; 1760 if (dev_t->avd_xdelay) 1761 gpmc_t->bool_timings.adv_extra_delay = true; 1762 if (dev_t->oe_xdelay) 1763 gpmc_t->bool_timings.oe_extra_delay = true; 1764 if (dev_t->we_xdelay) 1765 gpmc_t->bool_timings.we_extra_delay = true; 1766 1767 return 0; 1768 } 1769 1770 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, 1771 struct gpmc_device_timings *dev_t, 1772 bool sync) 1773 { 1774 u32 temp; 1775 1776 /* cs_on */ 1777 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); 1778 1779 /* adv_on */ 1780 temp = dev_t->t_avdasu; 1781 if (dev_t->t_ce_avd) 1782 temp = max_t(u32, temp, 1783 gpmc_t->cs_on + dev_t->t_ce_avd); 1784 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); 1785 1786 if (sync) 1787 gpmc_calc_sync_common_timings(gpmc_t, dev_t); 1788 1789 return 0; 1790 } 1791 1792 /* 1793 * TODO: remove this function once all peripherals are confirmed to 1794 * work with generic timing. Simultaneously gpmc_cs_set_timings() 1795 * has to be modified to handle timings in ps instead of ns 1796 */ 1797 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) 1798 { 1799 t->cs_on /= 1000; 1800 t->cs_rd_off /= 1000; 1801 t->cs_wr_off /= 1000; 1802 t->adv_on /= 1000; 1803 t->adv_rd_off /= 1000; 1804 t->adv_wr_off /= 1000; 1805 t->we_on /= 1000; 1806 t->we_off /= 1000; 1807 t->oe_on /= 1000; 1808 t->oe_off /= 1000; 1809 t->page_burst_access /= 1000; 1810 t->access /= 1000; 1811 t->rd_cycle /= 1000; 1812 t->wr_cycle /= 1000; 1813 t->bus_turnaround /= 1000; 1814 t->cycle2cycle_delay /= 1000; 1815 t->wait_monitoring /= 1000; 1816 t->clk_activation /= 1000; 1817 t->wr_access /= 1000; 1818 t->wr_data_mux_bus /= 1000; 1819 } 1820 1821 int gpmc_calc_timings(struct gpmc_timings *gpmc_t, 1822 struct gpmc_settings *gpmc_s, 1823 struct gpmc_device_timings *dev_t) 1824 { 1825 bool mux = false, sync = false; 1826 1827 if (gpmc_s) { 1828 mux = gpmc_s->mux_add_data ? true : false; 1829 sync = (gpmc_s->sync_read || gpmc_s->sync_write); 1830 } 1831 1832 memset(gpmc_t, 0, sizeof(*gpmc_t)); 1833 1834 gpmc_calc_common_timings(gpmc_t, dev_t, sync); 1835 1836 if (gpmc_s && gpmc_s->sync_read) 1837 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); 1838 else 1839 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); 1840 1841 if (gpmc_s && gpmc_s->sync_write) 1842 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); 1843 else 1844 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); 1845 1846 /* TODO: remove, see function definition */ 1847 gpmc_convert_ps_to_ns(gpmc_t); 1848 1849 return 0; 1850 } 1851 1852 /** 1853 * gpmc_cs_program_settings - programs non-timing related settings 1854 * @cs: GPMC chip-select to program 1855 * @p: pointer to GPMC settings structure 1856 * 1857 * Programs non-timing related settings for a GPMC chip-select, such as 1858 * bus-width, burst configuration, etc. Function should be called once 1859 * for each chip-select that is being used and must be called before 1860 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1 1861 * register will be initialised to zero by this function. Returns 0 on 1862 * success and appropriate negative error code on failure. 1863 */ 1864 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p) 1865 { 1866 u32 config1; 1867 1868 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) { 1869 pr_err("%s: invalid width %d!", __func__, p->device_width); 1870 return -EINVAL; 1871 } 1872 1873 /* Address-data multiplexing not supported for NAND devices */ 1874 if (p->device_nand && p->mux_add_data) { 1875 pr_err("%s: invalid configuration!\n", __func__); 1876 return -EINVAL; 1877 } 1878 1879 if ((p->mux_add_data > GPMC_MUX_AD) || 1880 ((p->mux_add_data == GPMC_MUX_AAD) && 1881 !(gpmc_capability & GPMC_HAS_MUX_AAD))) { 1882 pr_err("%s: invalid multiplex configuration!\n", __func__); 1883 return -EINVAL; 1884 } 1885 1886 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */ 1887 if (p->burst_read || p->burst_write) { 1888 switch (p->burst_len) { 1889 case GPMC_BURST_4: 1890 case GPMC_BURST_8: 1891 case GPMC_BURST_16: 1892 break; 1893 default: 1894 pr_err("%s: invalid page/burst-length (%d)\n", 1895 __func__, p->burst_len); 1896 return -EINVAL; 1897 } 1898 } 1899 1900 if (p->wait_pin != GPMC_WAITPIN_INVALID && 1901 p->wait_pin > gpmc_nr_waitpins) { 1902 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin); 1903 return -EINVAL; 1904 } 1905 1906 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1)); 1907 1908 if (p->sync_read) 1909 config1 |= GPMC_CONFIG1_READTYPE_SYNC; 1910 if (p->sync_write) 1911 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC; 1912 if (p->wait_on_read) 1913 config1 |= GPMC_CONFIG1_WAIT_READ_MON; 1914 if (p->wait_on_write) 1915 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON; 1916 if (p->wait_on_read || p->wait_on_write) 1917 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin); 1918 if (p->device_nand) 1919 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND); 1920 if (p->mux_add_data) 1921 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data); 1922 if (p->burst_read) 1923 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP; 1924 if (p->burst_write) 1925 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP; 1926 if (p->burst_read || p->burst_write) { 1927 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3); 1928 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0; 1929 } 1930 1931 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1); 1932 1933 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_INVALID) { 1934 config1 = gpmc_read_reg(GPMC_CONFIG); 1935 1936 if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_LOW) 1937 config1 &= ~GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); 1938 else if (p->wait_pin_polarity == GPMC_WAITPINPOLARITY_ACTIVE_HIGH) 1939 config1 |= GPMC_CONFIG_WAITPINPOLARITY(p->wait_pin); 1940 1941 gpmc_write_reg(GPMC_CONFIG, config1); 1942 } 1943 1944 return 0; 1945 } 1946 1947 #ifdef CONFIG_OF 1948 static void gpmc_cs_set_name(int cs, const char *name) 1949 { 1950 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1951 1952 gpmc->name = name; 1953 } 1954 1955 static const char *gpmc_cs_get_name(int cs) 1956 { 1957 struct gpmc_cs_data *gpmc = &gpmc_cs[cs]; 1958 1959 return gpmc->name; 1960 } 1961 1962 /** 1963 * gpmc_cs_remap - remaps a chip-select physical base address 1964 * @cs: chip-select to remap 1965 * @base: physical base address to re-map chip-select to 1966 * 1967 * Re-maps a chip-select to a new physical base address specified by 1968 * "base". Returns 0 on success and appropriate negative error code 1969 * on failure. 1970 */ 1971 static int gpmc_cs_remap(int cs, u32 base) 1972 { 1973 int ret; 1974 u32 old_base, size; 1975 1976 if (cs >= gpmc_cs_num) { 1977 pr_err("%s: requested chip-select is disabled\n", __func__); 1978 return -ENODEV; 1979 } 1980 1981 /* 1982 * Make sure we ignore any device offsets from the GPMC partition 1983 * allocated for the chip select and that the new base confirms 1984 * to the GPMC 16MB minimum granularity. 1985 */ 1986 base &= ~(SZ_16M - 1); 1987 1988 gpmc_cs_get_memconf(cs, &old_base, &size); 1989 if (base == old_base) 1990 return 0; 1991 1992 ret = gpmc_cs_delete_mem(cs); 1993 if (ret < 0) 1994 return ret; 1995 1996 ret = gpmc_cs_insert_mem(cs, base, size); 1997 if (ret < 0) 1998 return ret; 1999 2000 ret = gpmc_cs_set_memconf(cs, base, size); 2001 2002 return ret; 2003 } 2004 2005 /** 2006 * gpmc_read_settings_dt - read gpmc settings from device-tree 2007 * @np: pointer to device-tree node for a gpmc child device 2008 * @p: pointer to gpmc settings structure 2009 * 2010 * Reads the GPMC settings for a GPMC child device from device-tree and 2011 * stores them in the GPMC settings structure passed. The GPMC settings 2012 * structure is initialised to zero by this function and so any 2013 * previously stored settings will be cleared. 2014 */ 2015 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 2016 { 2017 memset(p, 0, sizeof(struct gpmc_settings)); 2018 2019 p->sync_read = of_property_read_bool(np, "gpmc,sync-read"); 2020 p->sync_write = of_property_read_bool(np, "gpmc,sync-write"); 2021 of_property_read_u32(np, "gpmc,device-width", &p->device_width); 2022 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); 2023 2024 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) { 2025 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap"); 2026 p->burst_read = of_property_read_bool(np, "gpmc,burst-read"); 2027 p->burst_write = of_property_read_bool(np, "gpmc,burst-write"); 2028 if (!p->burst_read && !p->burst_write) 2029 pr_warn("%s: page/burst-length set but not used!\n", 2030 __func__); 2031 } 2032 2033 p->wait_pin = GPMC_WAITPIN_INVALID; 2034 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; 2035 2036 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) { 2037 if (!gpmc_is_valid_waitpin(p->wait_pin)) { 2038 pr_err("%s: Invalid wait-pin (%d)\n", __func__, p->wait_pin); 2039 p->wait_pin = GPMC_WAITPIN_INVALID; 2040 } 2041 2042 if (!of_property_read_u32(np, "ti,wait-pin-polarity", 2043 &p->wait_pin_polarity)) { 2044 if (p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_HIGH && 2045 p->wait_pin_polarity != GPMC_WAITPINPOLARITY_ACTIVE_LOW) { 2046 pr_err("%s: Invalid wait-pin-polarity (%d)\n", 2047 __func__, p->wait_pin_polarity); 2048 p->wait_pin_polarity = GPMC_WAITPINPOLARITY_INVALID; 2049 } 2050 } 2051 2052 p->wait_on_read = of_property_read_bool(np, 2053 "gpmc,wait-on-read"); 2054 p->wait_on_write = of_property_read_bool(np, 2055 "gpmc,wait-on-write"); 2056 if (!p->wait_on_read && !p->wait_on_write) 2057 pr_debug("%s: rd/wr wait monitoring not enabled!\n", 2058 __func__); 2059 } 2060 } 2061 2062 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, 2063 struct gpmc_timings *gpmc_t) 2064 { 2065 struct gpmc_bool_timings *p; 2066 2067 if (!np || !gpmc_t) 2068 return; 2069 2070 memset(gpmc_t, 0, sizeof(*gpmc_t)); 2071 2072 /* minimum clock period for syncronous mode */ 2073 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk); 2074 2075 /* chip select timtings */ 2076 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on); 2077 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off); 2078 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off); 2079 2080 /* ADV signal timings */ 2081 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on); 2082 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off); 2083 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off); 2084 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns", 2085 &gpmc_t->adv_aad_mux_on); 2086 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns", 2087 &gpmc_t->adv_aad_mux_rd_off); 2088 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns", 2089 &gpmc_t->adv_aad_mux_wr_off); 2090 2091 /* WE signal timings */ 2092 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on); 2093 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off); 2094 2095 /* OE signal timings */ 2096 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on); 2097 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off); 2098 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns", 2099 &gpmc_t->oe_aad_mux_on); 2100 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns", 2101 &gpmc_t->oe_aad_mux_off); 2102 2103 /* access and cycle timings */ 2104 of_property_read_u32(np, "gpmc,page-burst-access-ns", 2105 &gpmc_t->page_burst_access); 2106 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access); 2107 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle); 2108 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle); 2109 of_property_read_u32(np, "gpmc,bus-turnaround-ns", 2110 &gpmc_t->bus_turnaround); 2111 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns", 2112 &gpmc_t->cycle2cycle_delay); 2113 of_property_read_u32(np, "gpmc,wait-monitoring-ns", 2114 &gpmc_t->wait_monitoring); 2115 of_property_read_u32(np, "gpmc,clk-activation-ns", 2116 &gpmc_t->clk_activation); 2117 2118 /* only applicable to OMAP3+ */ 2119 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access); 2120 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", 2121 &gpmc_t->wr_data_mux_bus); 2122 2123 /* bool timing parameters */ 2124 p = &gpmc_t->bool_timings; 2125 2126 p->cycle2cyclediffcsen = 2127 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen"); 2128 p->cycle2cyclesamecsen = 2129 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen"); 2130 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay"); 2131 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay"); 2132 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay"); 2133 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay"); 2134 p->time_para_granularity = 2135 of_property_read_bool(np, "gpmc,time-para-granularity"); 2136 } 2137 2138 /** 2139 * gpmc_probe_generic_child - configures the gpmc for a child device 2140 * @pdev: pointer to gpmc platform device 2141 * @child: pointer to device-tree node for child device 2142 * 2143 * Allocates and configures a GPMC chip-select for a child device. 2144 * Returns 0 on success and appropriate negative error code on failure. 2145 */ 2146 static int gpmc_probe_generic_child(struct platform_device *pdev, 2147 struct device_node *child) 2148 { 2149 struct gpmc_settings gpmc_s; 2150 struct gpmc_timings gpmc_t; 2151 struct resource res; 2152 unsigned long base; 2153 const char *name; 2154 int ret, cs; 2155 u32 val; 2156 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2157 2158 if (of_property_read_u32(child, "reg", &cs) < 0) { 2159 dev_err(&pdev->dev, "%pOF has no 'reg' property\n", 2160 child); 2161 return -ENODEV; 2162 } 2163 2164 if (of_address_to_resource(child, 0, &res) < 0) { 2165 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n", 2166 child); 2167 return -ENODEV; 2168 } 2169 2170 /* 2171 * Check if we have multiple instances of the same device 2172 * on a single chip select. If so, use the already initialized 2173 * timings. 2174 */ 2175 name = gpmc_cs_get_name(cs); 2176 if (name && of_node_name_eq(child, name)) 2177 goto no_timings; 2178 2179 ret = gpmc_cs_request(cs, resource_size(&res), &base); 2180 if (ret < 0) { 2181 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 2182 return ret; 2183 } 2184 gpmc_cs_set_name(cs, child->full_name); 2185 2186 gpmc_read_settings_dt(child, &gpmc_s); 2187 gpmc_read_timings_dt(child, &gpmc_t); 2188 2189 /* 2190 * For some GPMC devices we still need to rely on the bootloader 2191 * timings because the devices can be connected via FPGA. 2192 * REVISIT: Add timing support from slls644g.pdf. 2193 */ 2194 if (!gpmc_t.cs_rd_off) { 2195 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", 2196 cs); 2197 gpmc_cs_show_timings(cs, 2198 "please add GPMC bootloader timings to .dts"); 2199 goto no_timings; 2200 } 2201 2202 /* CS must be disabled while making changes to gpmc configuration */ 2203 gpmc_cs_disable_mem(cs); 2204 2205 /* 2206 * FIXME: gpmc_cs_request() will map the CS to an arbitrary 2207 * location in the gpmc address space. When booting with 2208 * device-tree we want the NOR flash to be mapped to the 2209 * location specified in the device-tree blob. So remap the 2210 * CS to this location. Once DT migration is complete should 2211 * just make gpmc_cs_request() map a specific address. 2212 */ 2213 ret = gpmc_cs_remap(cs, res.start); 2214 if (ret < 0) { 2215 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", 2216 cs, &res.start); 2217 if (res.start < GPMC_MEM_START) { 2218 dev_info(&pdev->dev, 2219 "GPMC CS %d start cannot be lesser than 0x%x\n", 2220 cs, GPMC_MEM_START); 2221 } else if (res.end > GPMC_MEM_END) { 2222 dev_info(&pdev->dev, 2223 "GPMC CS %d end cannot be greater than 0x%x\n", 2224 cs, GPMC_MEM_END); 2225 } 2226 goto err; 2227 } 2228 2229 if (of_node_name_eq(child, "nand")) { 2230 /* Warn about older DT blobs with no compatible property */ 2231 if (!of_property_read_bool(child, "compatible")) { 2232 dev_warn(&pdev->dev, 2233 "Incompatible NAND node: missing compatible"); 2234 ret = -EINVAL; 2235 goto err; 2236 } 2237 } 2238 2239 if (of_node_name_eq(child, "onenand")) { 2240 /* Warn about older DT blobs with no compatible property */ 2241 if (!of_property_read_bool(child, "compatible")) { 2242 dev_warn(&pdev->dev, 2243 "Incompatible OneNAND node: missing compatible"); 2244 ret = -EINVAL; 2245 goto err; 2246 } 2247 } 2248 2249 if (of_match_node(omap_nand_ids, child)) { 2250 /* NAND specific setup */ 2251 val = 8; 2252 of_property_read_u32(child, "nand-bus-width", &val); 2253 switch (val) { 2254 case 8: 2255 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT; 2256 break; 2257 case 16: 2258 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT; 2259 break; 2260 default: 2261 dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n", 2262 child); 2263 ret = -EINVAL; 2264 goto err; 2265 } 2266 2267 /* disable write protect */ 2268 gpmc_configure(GPMC_CONFIG_WP, 0); 2269 gpmc_s.device_nand = true; 2270 } else { 2271 ret = of_property_read_u32(child, "bank-width", 2272 &gpmc_s.device_width); 2273 if (ret < 0 && !gpmc_s.device_width) { 2274 dev_err(&pdev->dev, 2275 "%pOF has no 'gpmc,device-width' property\n", 2276 child); 2277 goto err; 2278 } 2279 } 2280 2281 /* Reserve wait pin if it is required and valid */ 2282 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) { 2283 ret = gpmc_alloc_waitpin(gpmc, &gpmc_s); 2284 if (ret < 0) 2285 goto err; 2286 } 2287 2288 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings"); 2289 2290 ret = gpmc_cs_program_settings(cs, &gpmc_s); 2291 if (ret < 0) 2292 goto err_cs; 2293 2294 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s); 2295 if (ret) { 2296 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n", 2297 child); 2298 goto err_cs; 2299 } 2300 2301 /* Clear limited address i.e. enable A26-A11 */ 2302 val = gpmc_read_reg(GPMC_CONFIG); 2303 val &= ~GPMC_CONFIG_LIMITEDADDRESS; 2304 gpmc_write_reg(GPMC_CONFIG, val); 2305 2306 /* Enable CS region */ 2307 gpmc_cs_enable_mem(cs); 2308 2309 no_timings: 2310 2311 /* create platform device, NULL on error or when disabled */ 2312 if (!of_platform_device_create(child, NULL, &pdev->dev)) 2313 goto err_child_fail; 2314 2315 /* create children and other common bus children */ 2316 if (of_platform_default_populate(child, NULL, &pdev->dev)) 2317 goto err_child_fail; 2318 2319 return 0; 2320 2321 err_child_fail: 2322 2323 dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child); 2324 ret = -ENODEV; 2325 2326 err_cs: 2327 gpmc_free_waitpin(gpmc, gpmc_s.wait_pin); 2328 err: 2329 gpmc_cs_free(cs); 2330 2331 return ret; 2332 } 2333 2334 static const struct of_device_id gpmc_dt_ids[]; 2335 2336 static int gpmc_probe_dt(struct platform_device *pdev) 2337 { 2338 int ret; 2339 const struct of_device_id *of_id = 2340 of_match_device(gpmc_dt_ids, &pdev->dev); 2341 2342 if (!of_id) 2343 return 0; 2344 2345 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs", 2346 &gpmc_cs_num); 2347 if (ret < 0) { 2348 pr_err("%s: number of chip-selects not defined\n", __func__); 2349 return ret; 2350 } else if (gpmc_cs_num < 1) { 2351 pr_err("%s: all chip-selects are disabled\n", __func__); 2352 return -EINVAL; 2353 } else if (gpmc_cs_num > GPMC_CS_NUM) { 2354 pr_err("%s: number of supported chip-selects cannot be > %d\n", 2355 __func__, GPMC_CS_NUM); 2356 return -EINVAL; 2357 } 2358 2359 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins", 2360 &gpmc_nr_waitpins); 2361 if (ret < 0) { 2362 pr_err("%s: number of wait pins not found!\n", __func__); 2363 return ret; 2364 } 2365 2366 return 0; 2367 } 2368 2369 static void gpmc_probe_dt_children(struct platform_device *pdev) 2370 { 2371 int ret; 2372 struct device_node *child; 2373 2374 for_each_available_child_of_node(pdev->dev.of_node, child) { 2375 ret = gpmc_probe_generic_child(pdev, child); 2376 if (ret) { 2377 dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n", 2378 child, ret); 2379 } 2380 } 2381 } 2382 #else 2383 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p) 2384 { 2385 memset(p, 0, sizeof(*p)); 2386 } 2387 static int gpmc_probe_dt(struct platform_device *pdev) 2388 { 2389 return 0; 2390 } 2391 2392 static void gpmc_probe_dt_children(struct platform_device *pdev) 2393 { 2394 } 2395 #endif /* CONFIG_OF */ 2396 2397 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 2398 { 2399 return 1; /* we're input only */ 2400 } 2401 2402 static int gpmc_gpio_direction_input(struct gpio_chip *chip, 2403 unsigned int offset) 2404 { 2405 return 0; /* we're input only */ 2406 } 2407 2408 static int gpmc_gpio_direction_output(struct gpio_chip *chip, 2409 unsigned int offset, int value) 2410 { 2411 return -EINVAL; /* we're input only */ 2412 } 2413 2414 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset, 2415 int value) 2416 { 2417 } 2418 2419 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset) 2420 { 2421 u32 reg; 2422 2423 offset += 8; 2424 2425 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset); 2426 2427 return !!reg; 2428 } 2429 2430 static int gpmc_gpio_init(struct gpmc_device *gpmc) 2431 { 2432 int ret; 2433 2434 gpmc->gpio_chip.parent = gpmc->dev; 2435 gpmc->gpio_chip.owner = THIS_MODULE; 2436 gpmc->gpio_chip.label = DEVICE_NAME; 2437 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins; 2438 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction; 2439 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input; 2440 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output; 2441 gpmc->gpio_chip.set = gpmc_gpio_set; 2442 gpmc->gpio_chip.get = gpmc_gpio_get; 2443 gpmc->gpio_chip.base = -1; 2444 2445 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL); 2446 if (ret < 0) { 2447 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret); 2448 return ret; 2449 } 2450 2451 return 0; 2452 } 2453 2454 static void omap3_gpmc_save_context(struct gpmc_device *gpmc) 2455 { 2456 struct omap3_gpmc_regs *gpmc_context; 2457 int i; 2458 2459 if (!gpmc || !gpmc_base) 2460 return; 2461 2462 gpmc_context = &gpmc->context; 2463 2464 gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); 2465 gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE); 2466 gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); 2467 gpmc_context->config = gpmc_read_reg(GPMC_CONFIG); 2468 gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); 2469 gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); 2470 gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); 2471 for (i = 0; i < gpmc_cs_num; i++) { 2472 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i); 2473 if (gpmc_context->cs_context[i].is_valid) { 2474 gpmc_context->cs_context[i].config1 = 2475 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); 2476 gpmc_context->cs_context[i].config2 = 2477 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); 2478 gpmc_context->cs_context[i].config3 = 2479 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); 2480 gpmc_context->cs_context[i].config4 = 2481 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); 2482 gpmc_context->cs_context[i].config5 = 2483 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); 2484 gpmc_context->cs_context[i].config6 = 2485 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); 2486 gpmc_context->cs_context[i].config7 = 2487 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); 2488 } 2489 } 2490 } 2491 2492 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc) 2493 { 2494 struct omap3_gpmc_regs *gpmc_context; 2495 int i; 2496 2497 if (!gpmc || !gpmc_base) 2498 return; 2499 2500 gpmc_context = &gpmc->context; 2501 2502 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig); 2503 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable); 2504 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl); 2505 gpmc_write_reg(GPMC_CONFIG, gpmc_context->config); 2506 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1); 2507 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2); 2508 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control); 2509 for (i = 0; i < gpmc_cs_num; i++) { 2510 if (gpmc_context->cs_context[i].is_valid) { 2511 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, 2512 gpmc_context->cs_context[i].config1); 2513 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, 2514 gpmc_context->cs_context[i].config2); 2515 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, 2516 gpmc_context->cs_context[i].config3); 2517 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, 2518 gpmc_context->cs_context[i].config4); 2519 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, 2520 gpmc_context->cs_context[i].config5); 2521 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, 2522 gpmc_context->cs_context[i].config6); 2523 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 2524 gpmc_context->cs_context[i].config7); 2525 } else { 2526 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0); 2527 } 2528 } 2529 } 2530 2531 static int omap_gpmc_context_notifier(struct notifier_block *nb, 2532 unsigned long cmd, void *v) 2533 { 2534 struct gpmc_device *gpmc; 2535 2536 gpmc = container_of(nb, struct gpmc_device, nb); 2537 if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev)) 2538 return NOTIFY_OK; 2539 2540 switch (cmd) { 2541 case CPU_CLUSTER_PM_ENTER: 2542 omap3_gpmc_save_context(gpmc); 2543 break; 2544 case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */ 2545 break; 2546 case CPU_CLUSTER_PM_EXIT: 2547 omap3_gpmc_restore_context(gpmc); 2548 break; 2549 } 2550 2551 return NOTIFY_OK; 2552 } 2553 2554 static int gpmc_probe(struct platform_device *pdev) 2555 { 2556 int rc, i; 2557 u32 l; 2558 struct resource *res; 2559 struct gpmc_device *gpmc; 2560 2561 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL); 2562 if (!gpmc) 2563 return -ENOMEM; 2564 2565 gpmc->dev = &pdev->dev; 2566 platform_set_drvdata(pdev, gpmc); 2567 2568 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); 2569 if (!res) { 2570 /* legacy DT */ 2571 gpmc_base = devm_platform_ioremap_resource(pdev, 0); 2572 if (IS_ERR(gpmc_base)) 2573 return PTR_ERR(gpmc_base); 2574 } else { 2575 gpmc_base = devm_ioremap_resource(&pdev->dev, res); 2576 if (IS_ERR(gpmc_base)) 2577 return PTR_ERR(gpmc_base); 2578 2579 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data"); 2580 if (!res) { 2581 dev_err(&pdev->dev, "couldn't get data reg resource\n"); 2582 return -ENOENT; 2583 } 2584 2585 gpmc->data = res; 2586 } 2587 2588 gpmc->irq = platform_get_irq(pdev, 0); 2589 if (gpmc->irq < 0) 2590 return gpmc->irq; 2591 2592 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck"); 2593 if (IS_ERR(gpmc_l3_clk)) { 2594 dev_err(&pdev->dev, "Failed to get GPMC fck\n"); 2595 return PTR_ERR(gpmc_l3_clk); 2596 } 2597 2598 if (!clk_get_rate(gpmc_l3_clk)) { 2599 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n"); 2600 return -EINVAL; 2601 } 2602 2603 if (pdev->dev.of_node) { 2604 rc = gpmc_probe_dt(pdev); 2605 if (rc) 2606 return rc; 2607 } else { 2608 gpmc_cs_num = GPMC_CS_NUM; 2609 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 2610 } 2611 2612 gpmc->waitpins = devm_kzalloc(&pdev->dev, 2613 gpmc_nr_waitpins * sizeof(struct gpmc_waitpin), 2614 GFP_KERNEL); 2615 if (!gpmc->waitpins) 2616 return -ENOMEM; 2617 2618 for (i = 0; i < gpmc_nr_waitpins; i++) 2619 gpmc->waitpins[i].pin = GPMC_WAITPIN_INVALID; 2620 2621 pm_runtime_enable(&pdev->dev); 2622 pm_runtime_get_sync(&pdev->dev); 2623 2624 l = gpmc_read_reg(GPMC_REVISION); 2625 2626 /* 2627 * FIXME: Once device-tree migration is complete the below flags 2628 * should be populated based upon the device-tree compatible 2629 * string. For now just use the IP revision. OMAP3+ devices have 2630 * the wr_access and wr_data_mux_bus register fields. OMAP4+ 2631 * devices support the addr-addr-data multiplex protocol. 2632 * 2633 * GPMC IP revisions: 2634 * - OMAP24xx = 2.0 2635 * - OMAP3xxx = 5.0 2636 * - OMAP44xx/54xx/AM335x = 6.0 2637 */ 2638 if (GPMC_REVISION_MAJOR(l) > 0x4) 2639 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; 2640 if (GPMC_REVISION_MAJOR(l) > 0x5) 2641 gpmc_capability |= GPMC_HAS_MUX_AAD; 2642 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), 2643 GPMC_REVISION_MINOR(l)); 2644 2645 gpmc_mem_init(gpmc); 2646 rc = gpmc_gpio_init(gpmc); 2647 if (rc) 2648 goto gpio_init_failed; 2649 2650 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins; 2651 rc = gpmc_setup_irq(gpmc); 2652 if (rc) { 2653 dev_err(gpmc->dev, "gpmc_setup_irq failed\n"); 2654 goto gpio_init_failed; 2655 } 2656 2657 gpmc_probe_dt_children(pdev); 2658 2659 gpmc->nb.notifier_call = omap_gpmc_context_notifier; 2660 cpu_pm_register_notifier(&gpmc->nb); 2661 2662 return 0; 2663 2664 gpio_init_failed: 2665 gpmc_mem_exit(); 2666 pm_runtime_put_sync(&pdev->dev); 2667 pm_runtime_disable(&pdev->dev); 2668 2669 return rc; 2670 } 2671 2672 static void gpmc_remove(struct platform_device *pdev) 2673 { 2674 int i; 2675 struct gpmc_device *gpmc = platform_get_drvdata(pdev); 2676 2677 cpu_pm_unregister_notifier(&gpmc->nb); 2678 for (i = 0; i < gpmc_nr_waitpins; i++) 2679 gpmc_free_waitpin(gpmc, i); 2680 gpmc_free_irq(gpmc); 2681 gpmc_mem_exit(); 2682 pm_runtime_put_sync(&pdev->dev); 2683 pm_runtime_disable(&pdev->dev); 2684 } 2685 2686 #ifdef CONFIG_PM_SLEEP 2687 static int gpmc_suspend(struct device *dev) 2688 { 2689 struct gpmc_device *gpmc = dev_get_drvdata(dev); 2690 2691 omap3_gpmc_save_context(gpmc); 2692 pm_runtime_put_sync(dev); 2693 gpmc->is_suspended = 1; 2694 2695 return 0; 2696 } 2697 2698 static int gpmc_resume(struct device *dev) 2699 { 2700 struct gpmc_device *gpmc = dev_get_drvdata(dev); 2701 2702 pm_runtime_get_sync(dev); 2703 omap3_gpmc_restore_context(gpmc); 2704 gpmc->is_suspended = 0; 2705 2706 return 0; 2707 } 2708 #endif 2709 2710 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume); 2711 2712 #ifdef CONFIG_OF 2713 static const struct of_device_id gpmc_dt_ids[] = { 2714 { .compatible = "ti,omap2420-gpmc" }, 2715 { .compatible = "ti,omap2430-gpmc" }, 2716 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ 2717 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ 2718 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ 2719 { .compatible = "ti,am64-gpmc" }, 2720 { } 2721 }; 2722 MODULE_DEVICE_TABLE(of, gpmc_dt_ids); 2723 #endif 2724 2725 static struct platform_driver gpmc_driver = { 2726 .probe = gpmc_probe, 2727 .remove = gpmc_remove, 2728 .driver = { 2729 .name = DEVICE_NAME, 2730 .of_match_table = of_match_ptr(gpmc_dt_ids), 2731 .pm = &gpmc_pm_ops, 2732 }, 2733 }; 2734 2735 module_platform_driver(gpmc_driver); 2736 2737 MODULE_DESCRIPTION("Texas Instruments GPMC driver"); 2738 MODULE_LICENSE("GPL"); 2739