1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015-2016 MediaTek Inc. 4 * Author: Yong Wu <yong.wu@mediatek.com> 5 */ 6 #include <linux/clk.h> 7 #include <linux/component.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <soc/mediatek/smi.h> 18 #include <dt-bindings/memory/mt2701-larb-port.h> 19 #include <dt-bindings/memory/mtk-memory-port.h> 20 21 /* SMI COMMON */ 22 #define SMI_L1LEN 0x100 23 24 #define SMI_L1_ARB 0x200 25 #define SMI_BUS_SEL 0x220 26 #define SMI_BUS_LARB_SHIFT(larbid) ((larbid) << 1) 27 /* All are MMU0 defaultly. Only specialize mmu1 here. */ 28 #define F_MMU1_LARB(larbid) (0x1 << SMI_BUS_LARB_SHIFT(larbid)) 29 30 #define SMI_READ_FIFO_TH 0x230 31 #define SMI_M4U_TH 0x234 32 #define SMI_FIFO_TH1 0x238 33 #define SMI_FIFO_TH2 0x23c 34 #define SMI_DCM 0x300 35 #define SMI_DUMMY 0x444 36 37 /* SMI LARB */ 38 #define SMI_LARB_SLP_CON 0xc 39 #define SLP_PROT_EN BIT(0) 40 #define SLP_PROT_RDY BIT(16) 41 42 #define SMI_LARB_CMD_THRT_CON 0x24 43 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4) 44 #define SMI_LARB_THRT_RD_NU_LMT (5 << 4) 45 46 #define SMI_LARB_SW_FLAG 0x40 47 #define SMI_LARB_SW_FLAG_1 0x1 48 49 #define SMI_LARB_OSTDL_PORT 0x200 50 #define SMI_LARB_OSTDL_PORTx(id) (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2)) 51 52 /* Below are about mmu enable registers, they are different in SoCs */ 53 /* gen1: mt2701 */ 54 #define REG_SMI_SECUR_CON_BASE 0x5c0 55 56 /* every register control 8 port, register offset 0x4 */ 57 #define REG_SMI_SECUR_CON_OFFSET(id) (((id) >> 3) << 2) 58 #define REG_SMI_SECUR_CON_ADDR(id) \ 59 (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id)) 60 61 /* 62 * every port have 4 bit to control, bit[port + 3] control virtual or physical, 63 * bit[port + 2 : port + 1] control the domain, bit[port] control the security 64 * or non-security. 65 */ 66 #define SMI_SECUR_CON_VAL_MSK(id) (~(0xf << (((id) & 0x7) << 2))) 67 #define SMI_SECUR_CON_VAL_VIRT(id) BIT((((id) & 0x7) << 2) + 3) 68 /* mt2701 domain should be set to 3 */ 69 #define SMI_SECUR_CON_VAL_DOMAIN(id) (0x3 << ((((id) & 0x7) << 2) + 1)) 70 71 /* gen2: */ 72 /* mt8167 */ 73 #define MT8167_SMI_LARB_MMU_EN 0xfc0 74 75 /* mt8173 */ 76 #define MT8173_SMI_LARB_MMU_EN 0xf00 77 78 /* general */ 79 #define SMI_LARB_NONSEC_CON(id) (0x380 + ((id) * 4)) 80 #define F_MMU_EN BIT(0) 81 #define BANK_SEL(id) ({ \ 82 u32 _id = (id) & 0x3; \ 83 (_id << 8 | _id << 10 | _id << 12 | _id << 14); \ 84 }) 85 86 #define SMI_COMMON_INIT_REGS_NR 6 87 #define SMI_LARB_PORT_NR_MAX 32 88 89 #define MTK_SMI_FLAG_THRT_UPDATE BIT(0) 90 #define MTK_SMI_FLAG_SW_FLAG BIT(1) 91 #define MTK_SMI_FLAG_SLEEP_CTL BIT(2) 92 #define MTK_SMI_CAPS(flags, _x) (!!((flags) & (_x))) 93 94 struct mtk_smi_reg_pair { 95 unsigned int offset; 96 u32 value; 97 }; 98 99 enum mtk_smi_type { 100 MTK_SMI_GEN1, 101 MTK_SMI_GEN2, /* gen2 smi common */ 102 MTK_SMI_GEN2_SUB_COMM, /* gen2 smi sub common */ 103 }; 104 105 /* larbs: Require apb/smi clocks while gals is optional. */ 106 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"}; 107 #define MTK_SMI_LARB_REQ_CLK_NR 2 108 #define MTK_SMI_LARB_OPT_CLK_NR 1 109 110 /* 111 * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required. 112 * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required. 113 */ 114 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"}; 115 #define MTK_SMI_CLK_NR_MAX ARRAY_SIZE(mtk_smi_common_clks) 116 #define MTK_SMI_COM_REQ_CLK_NR 2 117 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX 118 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3 119 120 struct mtk_smi_common_plat { 121 enum mtk_smi_type type; 122 bool has_gals; 123 u32 bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */ 124 125 const struct mtk_smi_reg_pair *init; 126 }; 127 128 struct mtk_smi_larb_gen { 129 int port_in_larb[MTK_LARB_NR_MAX + 1]; 130 void (*config_port)(struct device *dev); 131 unsigned int larb_direct_to_common_mask; 132 unsigned int flags_general; 133 const u8 (*ostd)[SMI_LARB_PORT_NR_MAX]; 134 }; 135 136 struct mtk_smi { 137 struct device *dev; 138 unsigned int clk_num; 139 struct clk_bulk_data clks[MTK_SMI_CLK_NR_MAX]; 140 struct clk *clk_async; /*only needed by mt2701*/ 141 union { 142 void __iomem *smi_ao_base; /* only for gen1 */ 143 void __iomem *base; /* only for gen2 */ 144 }; 145 struct device *smi_common_dev; /* for sub common */ 146 const struct mtk_smi_common_plat *plat; 147 }; 148 149 struct mtk_smi_larb { /* larb: local arbiter */ 150 struct mtk_smi smi; 151 void __iomem *base; 152 struct device *smi_common_dev; /* common or sub-common dev */ 153 const struct mtk_smi_larb_gen *larb_gen; 154 int larbid; 155 u32 *mmu; 156 unsigned char *bank; 157 }; 158 159 static int 160 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data) 161 { 162 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 163 struct mtk_smi_larb_iommu *larb_mmu = data; 164 unsigned int i; 165 166 for (i = 0; i < MTK_LARB_NR_MAX; i++) { 167 if (dev == larb_mmu[i].dev) { 168 larb->larbid = i; 169 larb->mmu = &larb_mmu[i].mmu; 170 larb->bank = larb_mmu[i].bank; 171 return 0; 172 } 173 } 174 return -ENODEV; 175 } 176 177 static void 178 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data) 179 { 180 /* Do nothing as the iommu is always enabled. */ 181 } 182 183 static const struct component_ops mtk_smi_larb_component_ops = { 184 .bind = mtk_smi_larb_bind, 185 .unbind = mtk_smi_larb_unbind, 186 }; 187 188 static void mtk_smi_larb_config_port_gen1(struct device *dev) 189 { 190 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 191 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 192 struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev); 193 int i, m4u_port_id, larb_port_num; 194 u32 sec_con_val, reg_val; 195 196 m4u_port_id = larb_gen->port_in_larb[larb->larbid]; 197 larb_port_num = larb_gen->port_in_larb[larb->larbid + 1] 198 - larb_gen->port_in_larb[larb->larbid]; 199 200 for (i = 0; i < larb_port_num; i++, m4u_port_id++) { 201 if (*larb->mmu & BIT(i)) { 202 /* bit[port + 3] controls the virtual or physical */ 203 sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id); 204 } else { 205 /* do not need to enable m4u for this port */ 206 continue; 207 } 208 reg_val = readl(common->smi_ao_base 209 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 210 reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id); 211 reg_val |= sec_con_val; 212 reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id); 213 writel(reg_val, 214 common->smi_ao_base 215 + REG_SMI_SECUR_CON_ADDR(m4u_port_id)); 216 } 217 } 218 219 static void mtk_smi_larb_config_port_mt8167(struct device *dev) 220 { 221 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 222 223 writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN); 224 } 225 226 static void mtk_smi_larb_config_port_mt8173(struct device *dev) 227 { 228 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 229 230 writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN); 231 } 232 233 static void mtk_smi_larb_config_port_gen2_general(struct device *dev) 234 { 235 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 236 u32 reg, flags_general = larb->larb_gen->flags_general; 237 const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL; 238 int i; 239 240 if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask) 241 return; 242 243 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) { 244 reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON); 245 reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK; 246 reg |= SMI_LARB_THRT_RD_NU_LMT; 247 writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON); 248 } 249 250 if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG)) 251 writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG); 252 253 for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++) 254 writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i)); 255 256 for_each_set_bit(i, (unsigned long *)larb->mmu, 32) { 257 reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i)); 258 reg |= F_MMU_EN; 259 reg |= BANK_SEL(larb->bank[i]); 260 writel(reg, larb->base + SMI_LARB_NONSEC_CON(i)); 261 } 262 } 263 264 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = { 265 [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */ 266 [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */ 267 [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,}, /* ... */ 268 [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,}, 269 [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,}, 270 [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,}, 271 [6] = {0x06, 0x01, 0x06, 0x0a,}, 272 [7] = {0x0c, 0x0c, 0x12,}, 273 [8] = {0x0c, 0x0c, 0x12,}, 274 [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a, 275 0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,}, 276 [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10, 277 0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d, 278 0x0d, 0x06, 0x10, 0x10,}, 279 [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,}, 280 [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,}, 281 [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,}, 282 [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01, 283 0x01, 0x02, 0x02, 0x08, 0x02,}, 284 [15] = {}, 285 [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a, 286 0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,}, 287 [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 288 [18] = {0x12, 0x06, 0x12, 0x06,}, 289 [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 290 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 291 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 292 [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01, 293 0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06, 294 0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,}, 295 [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 296 [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,}, 297 [23] = {0x18, 0x01,}, 298 [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01, 299 0x01, 0x01,}, 300 [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 301 0x02, 0x01,}, 302 [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 303 0x02, 0x01,}, 304 [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16, 305 0x02, 0x01,}, 306 [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,}, 307 }; 308 309 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = { 310 .port_in_larb = { 311 LARB0_PORT_OFFSET, LARB1_PORT_OFFSET, 312 LARB2_PORT_OFFSET, LARB3_PORT_OFFSET 313 }, 314 .config_port = mtk_smi_larb_config_port_gen1, 315 }; 316 317 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = { 318 .config_port = mtk_smi_larb_config_port_gen2_general, 319 .larb_direct_to_common_mask = BIT(8) | BIT(9), /* bdpsys */ 320 }; 321 322 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = { 323 .config_port = mtk_smi_larb_config_port_gen2_general, 324 .larb_direct_to_common_mask = 325 BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13), 326 /* DUMMY | IPU0 | IPU1 | CCU | MDLA */ 327 }; 328 329 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = { 330 /* mt8167 do not need the port in larb */ 331 .config_port = mtk_smi_larb_config_port_mt8167, 332 }; 333 334 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = { 335 /* mt8173 do not need the port in larb */ 336 .config_port = mtk_smi_larb_config_port_mt8173, 337 }; 338 339 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = { 340 .config_port = mtk_smi_larb_config_port_gen2_general, 341 .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7), 342 /* IPU0 | IPU1 | CCU */ 343 }; 344 345 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = { 346 .config_port = mtk_smi_larb_config_port_gen2_general, 347 .flags_general = MTK_SMI_FLAG_SLEEP_CTL, 348 }; 349 350 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = { 351 .config_port = mtk_smi_larb_config_port_gen2_general, 352 }; 353 354 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = { 355 .config_port = mtk_smi_larb_config_port_gen2_general, 356 .flags_general = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG | 357 MTK_SMI_FLAG_SLEEP_CTL, 358 .ostd = mtk_smi_larb_mt8195_ostd, 359 }; 360 361 static const struct of_device_id mtk_smi_larb_of_ids[] = { 362 {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701}, 363 {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712}, 364 {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779}, 365 {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173}, 366 {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167}, 367 {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173}, 368 {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183}, 369 {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186}, 370 {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192}, 371 {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195}, 372 {} 373 }; 374 375 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb) 376 { 377 int ret; 378 u32 tmp; 379 380 writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON); 381 ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON, 382 tmp, !!(tmp & SLP_PROT_RDY), 10, 1000); 383 if (ret) { 384 /* TODO: Reset this larb if it fails here. */ 385 dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp); 386 } 387 return ret; 388 } 389 390 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb) 391 { 392 writel_relaxed(0, larb->base + SMI_LARB_SLP_CON); 393 } 394 395 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev) 396 { 397 struct platform_device *smi_com_pdev; 398 struct device_node *smi_com_node; 399 struct device *smi_com_dev; 400 struct device_link *link; 401 402 smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0); 403 if (!smi_com_node) 404 return -EINVAL; 405 406 smi_com_pdev = of_find_device_by_node(smi_com_node); 407 of_node_put(smi_com_node); 408 if (smi_com_pdev) { 409 /* smi common is the supplier, Make sure it is ready before */ 410 if (!platform_get_drvdata(smi_com_pdev)) { 411 put_device(&smi_com_pdev->dev); 412 return -EPROBE_DEFER; 413 } 414 smi_com_dev = &smi_com_pdev->dev; 415 link = device_link_add(dev, smi_com_dev, 416 DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS); 417 if (!link) { 418 dev_err(dev, "Unable to link smi-common dev\n"); 419 put_device(&smi_com_pdev->dev); 420 return -ENODEV; 421 } 422 *com_dev = smi_com_dev; 423 } else { 424 dev_err(dev, "Failed to get the smi_common device\n"); 425 return -EINVAL; 426 } 427 return 0; 428 } 429 430 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi, 431 const char * const clks[], 432 unsigned int clk_nr_required, 433 unsigned int clk_nr_optional) 434 { 435 int i, ret; 436 437 for (i = 0; i < clk_nr_required; i++) 438 smi->clks[i].id = clks[i]; 439 ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks); 440 if (ret) 441 return ret; 442 443 for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++) 444 smi->clks[i].id = clks[i]; 445 ret = devm_clk_bulk_get_optional(dev, clk_nr_optional, 446 smi->clks + clk_nr_required); 447 smi->clk_num = clk_nr_required + clk_nr_optional; 448 return ret; 449 } 450 451 static int mtk_smi_larb_probe(struct platform_device *pdev) 452 { 453 struct mtk_smi_larb *larb; 454 struct device *dev = &pdev->dev; 455 int ret; 456 457 larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL); 458 if (!larb) 459 return -ENOMEM; 460 461 larb->larb_gen = of_device_get_match_data(dev); 462 larb->base = devm_platform_ioremap_resource(pdev, 0); 463 if (IS_ERR(larb->base)) 464 return PTR_ERR(larb->base); 465 466 ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks, 467 MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR); 468 if (ret) 469 return ret; 470 471 larb->smi.dev = dev; 472 473 ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev); 474 if (ret < 0) 475 return ret; 476 477 pm_runtime_enable(dev); 478 platform_set_drvdata(pdev, larb); 479 ret = component_add(dev, &mtk_smi_larb_component_ops); 480 if (ret) 481 goto err_pm_disable; 482 return 0; 483 484 err_pm_disable: 485 pm_runtime_disable(dev); 486 device_link_remove(dev, larb->smi_common_dev); 487 return ret; 488 } 489 490 static int mtk_smi_larb_remove(struct platform_device *pdev) 491 { 492 struct mtk_smi_larb *larb = platform_get_drvdata(pdev); 493 494 device_link_remove(&pdev->dev, larb->smi_common_dev); 495 pm_runtime_disable(&pdev->dev); 496 component_del(&pdev->dev, &mtk_smi_larb_component_ops); 497 return 0; 498 } 499 500 static int __maybe_unused mtk_smi_larb_resume(struct device *dev) 501 { 502 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 503 const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen; 504 int ret; 505 506 ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks); 507 if (ret) 508 return ret; 509 510 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) 511 mtk_smi_larb_sleep_ctrl_disable(larb); 512 513 /* Configure the basic setting for this larb */ 514 larb_gen->config_port(dev); 515 516 return 0; 517 } 518 519 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev) 520 { 521 struct mtk_smi_larb *larb = dev_get_drvdata(dev); 522 int ret; 523 524 if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) { 525 ret = mtk_smi_larb_sleep_ctrl_enable(larb); 526 if (ret) 527 return ret; 528 } 529 530 clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks); 531 return 0; 532 } 533 534 static const struct dev_pm_ops smi_larb_pm_ops = { 535 SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL) 536 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 537 pm_runtime_force_resume) 538 }; 539 540 static struct platform_driver mtk_smi_larb_driver = { 541 .probe = mtk_smi_larb_probe, 542 .remove = mtk_smi_larb_remove, 543 .driver = { 544 .name = "mtk-smi-larb", 545 .of_match_table = mtk_smi_larb_of_ids, 546 .pm = &smi_larb_pm_ops, 547 } 548 }; 549 550 static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = { 551 {SMI_L1_ARB, 0x1b}, 552 {SMI_M4U_TH, 0xce810c85}, 553 {SMI_FIFO_TH1, 0x43214c8}, 554 {SMI_READ_FIFO_TH, 0x191f}, 555 }; 556 557 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = { 558 {SMI_L1LEN, 0xb}, 559 {SMI_M4U_TH, 0xe100e10}, 560 {SMI_FIFO_TH1, 0x506090a}, 561 {SMI_FIFO_TH2, 0x506090a}, 562 {SMI_DCM, 0x4f1}, 563 {SMI_DUMMY, 0x1}, 564 }; 565 566 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = { 567 .type = MTK_SMI_GEN1, 568 }; 569 570 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = { 571 .type = MTK_SMI_GEN2, 572 }; 573 574 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = { 575 .type = MTK_SMI_GEN2, 576 .has_gals = true, 577 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) | 578 F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7), 579 }; 580 581 static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = { 582 .type = MTK_SMI_GEN2, 583 .bus_sel = F_MMU1_LARB(0), 584 .init = mtk_smi_common_mt6795_init, 585 }; 586 587 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = { 588 .type = MTK_SMI_GEN2, 589 .has_gals = true, 590 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 591 F_MMU1_LARB(7), 592 }; 593 594 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = { 595 .type = MTK_SMI_GEN2, 596 .has_gals = true, 597 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7), 598 }; 599 600 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = { 601 .type = MTK_SMI_GEN2, 602 .has_gals = true, 603 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) | 604 F_MMU1_LARB(6), 605 }; 606 607 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = { 608 .type = MTK_SMI_GEN2, 609 .has_gals = true, 610 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) | 611 F_MMU1_LARB(7), 612 .init = mtk_smi_common_mt8195_init, 613 }; 614 615 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = { 616 .type = MTK_SMI_GEN2, 617 .has_gals = true, 618 .bus_sel = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7), 619 .init = mtk_smi_common_mt8195_init, 620 }; 621 622 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = { 623 .type = MTK_SMI_GEN2_SUB_COMM, 624 .has_gals = true, 625 }; 626 627 static const struct of_device_id mtk_smi_common_of_ids[] = { 628 {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1}, 629 {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2}, 630 {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779}, 631 {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795}, 632 {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2}, 633 {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2}, 634 {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183}, 635 {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186}, 636 {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192}, 637 {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo}, 638 {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp}, 639 {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195}, 640 {} 641 }; 642 643 static int mtk_smi_common_probe(struct platform_device *pdev) 644 { 645 struct device *dev = &pdev->dev; 646 struct mtk_smi *common; 647 int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR; 648 649 common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL); 650 if (!common) 651 return -ENOMEM; 652 common->dev = dev; 653 common->plat = of_device_get_match_data(dev); 654 655 if (common->plat->has_gals) { 656 if (common->plat->type == MTK_SMI_GEN2) 657 clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR; 658 else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 659 clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR; 660 } 661 ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0); 662 if (ret) 663 return ret; 664 665 /* 666 * for mtk smi gen 1, we need to get the ao(always on) base to config 667 * m4u port, and we need to enable the aync clock for transform the smi 668 * clock into emi clock domain, but for mtk smi gen2, there's no smi ao 669 * base. 670 */ 671 if (common->plat->type == MTK_SMI_GEN1) { 672 common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0); 673 if (IS_ERR(common->smi_ao_base)) 674 return PTR_ERR(common->smi_ao_base); 675 676 common->clk_async = devm_clk_get(dev, "async"); 677 if (IS_ERR(common->clk_async)) 678 return PTR_ERR(common->clk_async); 679 680 ret = clk_prepare_enable(common->clk_async); 681 if (ret) 682 return ret; 683 } else { 684 common->base = devm_platform_ioremap_resource(pdev, 0); 685 if (IS_ERR(common->base)) 686 return PTR_ERR(common->base); 687 } 688 689 /* link its smi-common if this is smi-sub-common */ 690 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) { 691 ret = mtk_smi_device_link_common(dev, &common->smi_common_dev); 692 if (ret < 0) 693 return ret; 694 } 695 696 pm_runtime_enable(dev); 697 platform_set_drvdata(pdev, common); 698 return 0; 699 } 700 701 static int mtk_smi_common_remove(struct platform_device *pdev) 702 { 703 struct mtk_smi *common = dev_get_drvdata(&pdev->dev); 704 705 if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) 706 device_link_remove(&pdev->dev, common->smi_common_dev); 707 pm_runtime_disable(&pdev->dev); 708 return 0; 709 } 710 711 static int __maybe_unused mtk_smi_common_resume(struct device *dev) 712 { 713 struct mtk_smi *common = dev_get_drvdata(dev); 714 const struct mtk_smi_reg_pair *init = common->plat->init; 715 u32 bus_sel = common->plat->bus_sel; /* default is 0 */ 716 int ret, i; 717 718 ret = clk_bulk_prepare_enable(common->clk_num, common->clks); 719 if (ret) 720 return ret; 721 722 if (common->plat->type != MTK_SMI_GEN2) 723 return 0; 724 725 for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++) 726 writel_relaxed(init[i].value, common->base + init[i].offset); 727 728 writel(bus_sel, common->base + SMI_BUS_SEL); 729 return 0; 730 } 731 732 static int __maybe_unused mtk_smi_common_suspend(struct device *dev) 733 { 734 struct mtk_smi *common = dev_get_drvdata(dev); 735 736 clk_bulk_disable_unprepare(common->clk_num, common->clks); 737 return 0; 738 } 739 740 static const struct dev_pm_ops smi_common_pm_ops = { 741 SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL) 742 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 743 pm_runtime_force_resume) 744 }; 745 746 static struct platform_driver mtk_smi_common_driver = { 747 .probe = mtk_smi_common_probe, 748 .remove = mtk_smi_common_remove, 749 .driver = { 750 .name = "mtk-smi-common", 751 .of_match_table = mtk_smi_common_of_ids, 752 .pm = &smi_common_pm_ops, 753 } 754 }; 755 756 static struct platform_driver * const smidrivers[] = { 757 &mtk_smi_common_driver, 758 &mtk_smi_larb_driver, 759 }; 760 761 static int __init mtk_smi_init(void) 762 { 763 return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 764 } 765 module_init(mtk_smi_init); 766 767 static void __exit mtk_smi_exit(void) 768 { 769 platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers)); 770 } 771 module_exit(mtk_smi_exit); 772 773 MODULE_DESCRIPTION("MediaTek SMI driver"); 774 MODULE_LICENSE("GPL v2"); 775