1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs 4 * 5 * Copyright (c) 2017 Broadcom 6 */ 7 8 /* 9 * This driver provides access to the DPFE interface of Broadcom STB SoCs. 10 * The firmware running on the DCPU inside the DDR PHY can provide current 11 * information about the system's RAM, for instance the DRAM refresh rate. 12 * This can be used as an indirect indicator for the DRAM's temperature. 13 * Slower refresh rate means cooler RAM, higher refresh rate means hotter 14 * RAM. 15 * 16 * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which 17 * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls. 18 * 19 * Note regarding the loading of the firmware image: we use be32_to_cpu() 20 * and le_32_to_cpu(), so we can support the following four cases: 21 * - LE kernel + LE firmware image (the most common case) 22 * - LE kernel + BE firmware image 23 * - BE kernel + LE firmware image 24 * - BE kernel + BE firmware image 25 * 26 * The DPCU always runs in big endian mode. The firmware image, however, can 27 * be in either format. Also, communication between host CPU and DCPU is 28 * always in little endian. 29 */ 30 31 #include <linux/delay.h> 32 #include <linux/firmware.h> 33 #include <linux/io.h> 34 #include <linux/module.h> 35 #include <linux/of.h> 36 #include <linux/platform_device.h> 37 38 #define DRVNAME "brcmstb-dpfe" 39 40 /* DCPU register offsets */ 41 #define REG_DCPU_RESET 0x0 42 #define REG_TO_DCPU_MBOX 0x10 43 #define REG_TO_HOST_MBOX 0x14 44 45 /* Macros to process offsets returned by the DCPU */ 46 #define DRAM_MSG_ADDR_OFFSET 0x0 47 #define DRAM_MSG_TYPE_OFFSET 0x1c 48 #define DRAM_MSG_ADDR_MASK ((1UL << DRAM_MSG_TYPE_OFFSET) - 1) 49 #define DRAM_MSG_TYPE_MASK ((1UL << \ 50 (BITS_PER_LONG - DRAM_MSG_TYPE_OFFSET)) - 1) 51 52 /* Message RAM */ 53 #define DCPU_MSG_RAM_START 0x100 54 #define DCPU_MSG_RAM(x) (DCPU_MSG_RAM_START + (x) * sizeof(u32)) 55 56 /* DRAM Info Offsets & Masks */ 57 #define DRAM_INFO_INTERVAL 0x0 58 #define DRAM_INFO_MR4 0x4 59 #define DRAM_INFO_ERROR 0x8 60 #define DRAM_INFO_MR4_MASK 0xff 61 #define DRAM_INFO_MR4_SHIFT 24 /* We need to look at byte 3 */ 62 63 /* DRAM MR4 Offsets & Masks */ 64 #define DRAM_MR4_REFRESH 0x0 /* Refresh rate */ 65 #define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */ 66 #define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */ 67 #define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */ 68 #define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */ 69 70 #define DRAM_MR4_REFRESH_MASK 0x7 71 #define DRAM_MR4_SR_ABORT_MASK 0x1 72 #define DRAM_MR4_PPRE_MASK 0x1 73 #define DRAM_MR4_TH_OFFS_MASK 0x3 74 #define DRAM_MR4_TUF_MASK 0x1 75 76 /* DRAM Vendor Offsets & Masks (API v2) */ 77 #define DRAM_VENDOR_MR5 0x0 78 #define DRAM_VENDOR_MR6 0x4 79 #define DRAM_VENDOR_MR7 0x8 80 #define DRAM_VENDOR_MR8 0xc 81 #define DRAM_VENDOR_ERROR 0x10 82 #define DRAM_VENDOR_MASK 0xff 83 #define DRAM_VENDOR_SHIFT 24 /* We need to look at byte 3 */ 84 85 /* DRAM Information Offsets & Masks (API v3) */ 86 #define DRAM_DDR_INFO_MR4 0x0 87 #define DRAM_DDR_INFO_MR5 0x4 88 #define DRAM_DDR_INFO_MR6 0x8 89 #define DRAM_DDR_INFO_MR7 0xc 90 #define DRAM_DDR_INFO_MR8 0x10 91 #define DRAM_DDR_INFO_ERROR 0x14 92 #define DRAM_DDR_INFO_MASK 0xff 93 94 /* Reset register bits & masks */ 95 #define DCPU_RESET_SHIFT 0x0 96 #define DCPU_RESET_MASK 0x1 97 #define DCPU_CLK_DISABLE_SHIFT 0x2 98 99 /* DCPU return codes */ 100 #define DCPU_RET_ERROR_BIT BIT(31) 101 #define DCPU_RET_SUCCESS 0x1 102 #define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0)) 103 #define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1)) 104 #define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2)) 105 #define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3)) 106 /* This error code is not firmware defined and only used in the driver. */ 107 #define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4)) 108 109 /* Firmware magic */ 110 #define DPFE_BE_MAGIC 0xfe1010fe 111 #define DPFE_LE_MAGIC 0xfe0101fe 112 113 /* Error codes */ 114 #define ERR_INVALID_MAGIC -1 115 #define ERR_INVALID_SIZE -2 116 #define ERR_INVALID_CHKSUM -3 117 118 /* Message types */ 119 #define DPFE_MSG_TYPE_COMMAND 1 120 #define DPFE_MSG_TYPE_RESPONSE 2 121 122 #define DELAY_LOOP_MAX 1000 123 124 enum dpfe_msg_fields { 125 MSG_HEADER, 126 MSG_COMMAND, 127 MSG_ARG_COUNT, 128 MSG_ARG0, 129 MSG_FIELD_MAX = 16 /* Max number of arguments */ 130 }; 131 132 enum dpfe_commands { 133 DPFE_CMD_GET_INFO, 134 DPFE_CMD_GET_REFRESH, 135 DPFE_CMD_GET_VENDOR, 136 DPFE_CMD_MAX /* Last entry */ 137 }; 138 139 /* 140 * Format of the binary firmware file: 141 * 142 * entry 143 * 0 header 144 * value: 0xfe0101fe <== little endian 145 * 0xfe1010fe <== big endian 146 * 1 sequence: 147 * [31:16] total segments on this build 148 * [15:0] this segment sequence. 149 * 2 FW version 150 * 3 IMEM byte size 151 * 4 DMEM byte size 152 * IMEM 153 * DMEM 154 * last checksum ==> sum of everything 155 */ 156 struct dpfe_firmware_header { 157 u32 magic; 158 u32 sequence; 159 u32 version; 160 u32 imem_size; 161 u32 dmem_size; 162 }; 163 164 /* Things we only need during initialization. */ 165 struct init_data { 166 unsigned int dmem_len; 167 unsigned int imem_len; 168 unsigned int chksum; 169 bool is_big_endian; 170 }; 171 172 /* API version and corresponding commands */ 173 struct dpfe_api { 174 int version; 175 const char *fw_name; 176 const struct attribute_group **sysfs_attrs; 177 u32 command[DPFE_CMD_MAX][MSG_FIELD_MAX]; 178 }; 179 180 /* Things we need for as long as we are active. */ 181 struct brcmstb_dpfe_priv { 182 void __iomem *regs; 183 void __iomem *dmem; 184 void __iomem *imem; 185 resource_size_t regs_size; 186 resource_size_t dmem_size; 187 struct device *dev; 188 const struct dpfe_api *dpfe_api; 189 struct mutex lock; 190 }; 191 192 /* 193 * Forward declaration of our sysfs attribute functions, so we can declare the 194 * attribute data structures early. 195 */ 196 static ssize_t show_info(struct device *, struct device_attribute *, char *); 197 static ssize_t show_refresh(struct device *, struct device_attribute *, char *); 198 static ssize_t store_refresh(struct device *, struct device_attribute *, 199 const char *, size_t); 200 static ssize_t show_vendor(struct device *, struct device_attribute *, char *); 201 static ssize_t show_dram(struct device *, struct device_attribute *, char *); 202 203 /* 204 * Declare our attributes early, so they can be referenced in the API data 205 * structure. We need to do this, because the attributes depend on the API 206 * version. 207 */ 208 static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL); 209 static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh); 210 static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL); 211 static DEVICE_ATTR(dpfe_dram, 0444, show_dram, NULL); 212 213 /* API v2 sysfs attributes */ 214 static struct attribute *dpfe_v2_attrs[] = { 215 &dev_attr_dpfe_info.attr, 216 &dev_attr_dpfe_refresh.attr, 217 &dev_attr_dpfe_vendor.attr, 218 NULL 219 }; 220 ATTRIBUTE_GROUPS(dpfe_v2); 221 222 /* API v3 sysfs attributes */ 223 static struct attribute *dpfe_v3_attrs[] = { 224 &dev_attr_dpfe_info.attr, 225 &dev_attr_dpfe_dram.attr, 226 NULL 227 }; 228 ATTRIBUTE_GROUPS(dpfe_v3); 229 230 /* 231 * Old API v2 firmware commands, as defined in the rev 0.61 specification, we 232 * use a version set to 1 to denote that it is not compatible with the new API 233 * v2 and onwards. 234 */ 235 static const struct dpfe_api dpfe_api_old_v2 = { 236 .version = 1, 237 .fw_name = "dpfe.bin", 238 .sysfs_attrs = dpfe_v2_groups, 239 .command = { 240 [DPFE_CMD_GET_INFO] = { 241 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 242 [MSG_COMMAND] = 1, 243 [MSG_ARG_COUNT] = 1, 244 [MSG_ARG0] = 1, 245 }, 246 [DPFE_CMD_GET_REFRESH] = { 247 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 248 [MSG_COMMAND] = 2, 249 [MSG_ARG_COUNT] = 1, 250 [MSG_ARG0] = 1, 251 }, 252 [DPFE_CMD_GET_VENDOR] = { 253 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 254 [MSG_COMMAND] = 2, 255 [MSG_ARG_COUNT] = 1, 256 [MSG_ARG0] = 2, 257 }, 258 } 259 }; 260 261 /* 262 * API v2 firmware commands, as defined in the rev 0.8 specification, named new 263 * v2 here 264 */ 265 static const struct dpfe_api dpfe_api_new_v2 = { 266 .version = 2, 267 .fw_name = NULL, /* We expect the firmware to have been downloaded! */ 268 .sysfs_attrs = dpfe_v2_groups, 269 .command = { 270 [DPFE_CMD_GET_INFO] = { 271 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 272 [MSG_COMMAND] = 0x101, 273 }, 274 [DPFE_CMD_GET_REFRESH] = { 275 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 276 [MSG_COMMAND] = 0x201, 277 }, 278 [DPFE_CMD_GET_VENDOR] = { 279 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 280 [MSG_COMMAND] = 0x202, 281 }, 282 } 283 }; 284 285 /* API v3 firmware commands */ 286 static const struct dpfe_api dpfe_api_v3 = { 287 .version = 3, 288 .fw_name = NULL, /* We expect the firmware to have been downloaded! */ 289 .sysfs_attrs = dpfe_v3_groups, 290 .command = { 291 [DPFE_CMD_GET_INFO] = { 292 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 293 [MSG_COMMAND] = 0x0101, 294 [MSG_ARG_COUNT] = 1, 295 [MSG_ARG0] = 1, 296 }, 297 [DPFE_CMD_GET_REFRESH] = { 298 [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, 299 [MSG_COMMAND] = 0x0202, 300 [MSG_ARG_COUNT] = 0, 301 }, 302 /* There's no GET_VENDOR command in API v3. */ 303 }, 304 }; 305 306 static const char *get_error_text(unsigned int i) 307 { 308 static const char * const error_text[] = { 309 "Success", "Header code incorrect", 310 "Unknown command or argument", "Incorrect checksum", 311 "Malformed command", "Timed out", "Unknown error", 312 }; 313 314 if (unlikely(i >= ARRAY_SIZE(error_text))) 315 i = ARRAY_SIZE(error_text) - 1; 316 317 return error_text[i]; 318 } 319 320 static bool is_dcpu_enabled(struct brcmstb_dpfe_priv *priv) 321 { 322 u32 val; 323 324 mutex_lock(&priv->lock); 325 val = readl_relaxed(priv->regs + REG_DCPU_RESET); 326 mutex_unlock(&priv->lock); 327 328 return !(val & DCPU_RESET_MASK); 329 } 330 331 static void __disable_dcpu(struct brcmstb_dpfe_priv *priv) 332 { 333 u32 val; 334 335 if (!is_dcpu_enabled(priv)) 336 return; 337 338 mutex_lock(&priv->lock); 339 340 /* Put DCPU in reset if it's running. */ 341 val = readl_relaxed(priv->regs + REG_DCPU_RESET); 342 val |= (1 << DCPU_RESET_SHIFT); 343 writel_relaxed(val, priv->regs + REG_DCPU_RESET); 344 345 mutex_unlock(&priv->lock); 346 } 347 348 static void __enable_dcpu(struct brcmstb_dpfe_priv *priv) 349 { 350 void __iomem *regs = priv->regs; 351 u32 val; 352 353 mutex_lock(&priv->lock); 354 355 /* Clear mailbox registers. */ 356 writel_relaxed(0, regs + REG_TO_DCPU_MBOX); 357 writel_relaxed(0, regs + REG_TO_HOST_MBOX); 358 359 /* Disable DCPU clock gating */ 360 val = readl_relaxed(regs + REG_DCPU_RESET); 361 val &= ~(1 << DCPU_CLK_DISABLE_SHIFT); 362 writel_relaxed(val, regs + REG_DCPU_RESET); 363 364 /* Take DCPU out of reset */ 365 val = readl_relaxed(regs + REG_DCPU_RESET); 366 val &= ~(1 << DCPU_RESET_SHIFT); 367 writel_relaxed(val, regs + REG_DCPU_RESET); 368 369 mutex_unlock(&priv->lock); 370 } 371 372 static unsigned int get_msg_chksum(const u32 msg[], unsigned int max) 373 { 374 unsigned int sum = 0; 375 unsigned int i; 376 377 /* Don't include the last field in the checksum. */ 378 for (i = 0; i < max; i++) 379 sum += msg[i]; 380 381 return sum; 382 } 383 384 static void __iomem *get_msg_ptr(struct brcmstb_dpfe_priv *priv, u32 response, 385 char *buf, ssize_t *size) 386 { 387 unsigned int msg_type; 388 unsigned int offset; 389 void __iomem *ptr = NULL; 390 391 /* There is no need to use this function for API v3 or later. */ 392 if (unlikely(priv->dpfe_api->version >= 3)) 393 return NULL; 394 395 msg_type = (response >> DRAM_MSG_TYPE_OFFSET) & DRAM_MSG_TYPE_MASK; 396 offset = (response >> DRAM_MSG_ADDR_OFFSET) & DRAM_MSG_ADDR_MASK; 397 398 /* 399 * msg_type == 1: the offset is relative to the message RAM 400 * msg_type == 0: the offset is relative to the data RAM (this is the 401 * previous way of passing data) 402 * msg_type is anything else: there's critical hardware problem 403 */ 404 switch (msg_type) { 405 case 1: 406 if (DCPU_MSG_RAM_START + offset + DRAM_VENDOR_ERROR + 407 sizeof(u32) > priv->regs_size) 408 goto bad_offset; 409 ptr = priv->regs + DCPU_MSG_RAM_START + offset; 410 break; 411 case 0: 412 if (offset + DRAM_VENDOR_ERROR + sizeof(u32) > priv->dmem_size) 413 goto bad_offset; 414 ptr = priv->dmem + offset; 415 break; 416 default: 417 dev_emerg(priv->dev, "invalid message reply from DCPU: %#x\n", 418 response); 419 if (buf && size) 420 *size = sprintf(buf, 421 "FATAL: communication error with DCPU\n"); 422 } 423 424 return ptr; 425 426 bad_offset: 427 dev_err(priv->dev, "DCPU returned out-of-range offset %#x\n", offset); 428 if (buf && size) 429 *size = sprintf(buf, "ERROR: DCPU offset out of range\n"); 430 return NULL; 431 } 432 433 static void __finalize_command(struct brcmstb_dpfe_priv *priv) 434 { 435 unsigned int release_mbox; 436 437 /* 438 * It depends on the API version which MBOX register we have to write to 439 * signal we are done. 440 */ 441 release_mbox = (priv->dpfe_api->version < 2) 442 ? REG_TO_HOST_MBOX : REG_TO_DCPU_MBOX; 443 writel_relaxed(0, priv->regs + release_mbox); 444 } 445 446 static int __send_command(struct brcmstb_dpfe_priv *priv, unsigned int cmd, 447 u32 result[]) 448 { 449 void __iomem *regs = priv->regs; 450 unsigned int i, chksum, chksum_idx; 451 const u32 *msg; 452 int ret = 0; 453 u32 resp; 454 455 if (cmd >= DPFE_CMD_MAX) 456 return -1; 457 458 msg = priv->dpfe_api->command[cmd]; 459 460 mutex_lock(&priv->lock); 461 462 /* Wait for DCPU to become ready */ 463 for (i = 0; i < DELAY_LOOP_MAX; i++) { 464 resp = readl_relaxed(regs + REG_TO_HOST_MBOX); 465 if (resp == 0) 466 break; 467 msleep(1); 468 } 469 if (resp != 0) { 470 mutex_unlock(&priv->lock); 471 return -ffs(DCPU_RET_ERR_TIMEDOUT); 472 } 473 474 /* Compute checksum over the message */ 475 chksum_idx = msg[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1; 476 chksum = get_msg_chksum(msg, chksum_idx); 477 478 /* Write command and arguments to message area */ 479 for (i = 0; i < MSG_FIELD_MAX; i++) { 480 if (i == chksum_idx) 481 writel_relaxed(chksum, regs + DCPU_MSG_RAM(i)); 482 else 483 writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i)); 484 } 485 486 /* Tell DCPU there is a command waiting */ 487 writel_relaxed(1, regs + REG_TO_DCPU_MBOX); 488 489 /* Wait for DCPU to process the command */ 490 for (i = 0; i < DELAY_LOOP_MAX; i++) { 491 /* Read response code */ 492 resp = readl_relaxed(regs + REG_TO_HOST_MBOX); 493 if (resp > 0) 494 break; 495 msleep(1); 496 } 497 498 if (i == DELAY_LOOP_MAX) { 499 resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT); 500 ret = -ffs(resp); 501 } else { 502 /* Read response data */ 503 for (i = 0; i < MSG_FIELD_MAX; i++) 504 result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i)); 505 chksum_idx = result[MSG_ARG_COUNT] + MSG_ARG_COUNT + 1; 506 if (chksum_idx >= MSG_FIELD_MAX) 507 ret = -EINVAL; 508 } 509 510 /* Tell DCPU we are done */ 511 __finalize_command(priv); 512 513 mutex_unlock(&priv->lock); 514 515 if (ret) 516 return ret; 517 518 /* Verify response */ 519 chksum = get_msg_chksum(result, chksum_idx); 520 if (chksum != result[chksum_idx]) 521 resp = DCPU_RET_ERR_CHKSUM; 522 523 if (resp != DCPU_RET_SUCCESS) { 524 resp &= ~DCPU_RET_ERROR_BIT; 525 ret = -ffs(resp); 526 } 527 528 return ret; 529 } 530 531 /* Ensure that the firmware file loaded meets all the requirements. */ 532 static int __verify_firmware(struct init_data *init, 533 const struct firmware *fw) 534 { 535 const struct dpfe_firmware_header *header = (void *)fw->data; 536 unsigned int dmem_size, imem_size; 537 bool is_big_endian = false; 538 const u32 *chksum_ptr; 539 size_t payload_size; 540 541 if (fw->size < sizeof(*header) + sizeof(*chksum_ptr)) 542 return ERR_INVALID_SIZE; 543 544 payload_size = fw->size - sizeof(*header) - sizeof(*chksum_ptr); 545 546 if (header->magic == DPFE_BE_MAGIC) 547 is_big_endian = true; 548 else if (header->magic != DPFE_LE_MAGIC) 549 return ERR_INVALID_MAGIC; 550 551 if (is_big_endian) { 552 dmem_size = be32_to_cpu(header->dmem_size); 553 imem_size = be32_to_cpu(header->imem_size); 554 } else { 555 dmem_size = le32_to_cpu(header->dmem_size); 556 imem_size = le32_to_cpu(header->imem_size); 557 } 558 559 /* Data and instruction sections are 32 bit words. */ 560 if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0) 561 return ERR_INVALID_SIZE; 562 563 /* The data and instruction sections must fill the payload exactly. */ 564 if (dmem_size > payload_size || imem_size != payload_size - dmem_size) 565 return ERR_INVALID_SIZE; 566 567 /* The checksum comes at the very end. */ 568 chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size; 569 570 init->is_big_endian = is_big_endian; 571 init->dmem_len = dmem_size; 572 init->imem_len = imem_size; 573 init->chksum = (is_big_endian) 574 ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr); 575 576 return 0; 577 } 578 579 /* Verify checksum by reading back the firmware from co-processor RAM. */ 580 static int __verify_fw_checksum(struct init_data *init, 581 struct brcmstb_dpfe_priv *priv, 582 const struct dpfe_firmware_header *header, 583 u32 checksum) 584 { 585 u32 magic, sequence, version, sum; 586 u32 __iomem *dmem = priv->dmem; 587 u32 __iomem *imem = priv->imem; 588 unsigned int i; 589 590 if (init->is_big_endian) { 591 magic = be32_to_cpu(header->magic); 592 sequence = be32_to_cpu(header->sequence); 593 version = be32_to_cpu(header->version); 594 } else { 595 magic = le32_to_cpu(header->magic); 596 sequence = le32_to_cpu(header->sequence); 597 version = le32_to_cpu(header->version); 598 } 599 600 sum = magic + sequence + version + init->dmem_len + init->imem_len; 601 602 for (i = 0; i < init->dmem_len / sizeof(u32); i++) 603 sum += readl_relaxed(dmem + i); 604 605 for (i = 0; i < init->imem_len / sizeof(u32); i++) 606 sum += readl_relaxed(imem + i); 607 608 return (sum == checksum) ? 0 : -1; 609 } 610 611 static int __write_firmware(u32 __iomem *mem, const u32 *fw, 612 unsigned int size, bool is_big_endian) 613 { 614 unsigned int i; 615 616 /* Convert size to 32-bit words. */ 617 size /= sizeof(u32); 618 619 /* It is recommended to clear the firmware area first. */ 620 for (i = 0; i < size; i++) 621 writel_relaxed(0, mem + i); 622 623 /* Now copy it. */ 624 if (is_big_endian) { 625 for (i = 0; i < size; i++) 626 writel_relaxed(be32_to_cpu(fw[i]), mem + i); 627 } else { 628 for (i = 0; i < size; i++) 629 writel_relaxed(le32_to_cpu(fw[i]), mem + i); 630 } 631 632 return 0; 633 } 634 635 static int brcmstb_dpfe_download_firmware(struct brcmstb_dpfe_priv *priv) 636 { 637 const struct dpfe_firmware_header *header; 638 unsigned int dmem_size, imem_size; 639 struct device *dev = priv->dev; 640 bool is_big_endian = false; 641 const struct firmware *fw; 642 const u32 *dmem, *imem; 643 struct init_data init; 644 const void *fw_blob; 645 int ret; 646 647 /* 648 * Skip downloading the firmware if the DCPU is already running and 649 * responding to commands. 650 */ 651 if (is_dcpu_enabled(priv)) { 652 u32 response[MSG_FIELD_MAX]; 653 654 ret = __send_command(priv, DPFE_CMD_GET_INFO, response); 655 if (!ret) 656 return 0; 657 } 658 659 /* 660 * If the firmware filename is NULL it means the boot firmware has to 661 * download the DCPU firmware for us. If that didn't work, we have to 662 * bail, since downloading it ourselves wouldn't work either. 663 */ 664 if (!priv->dpfe_api->fw_name) 665 return -ENODEV; 666 667 ret = firmware_request_nowarn(&fw, priv->dpfe_api->fw_name, dev); 668 /* 669 * Defer the firmware download if the firmware file couldn't be found. 670 * The root file system may not be available yet. 671 */ 672 if (ret) 673 return (ret == -ENOENT) ? -EPROBE_DEFER : ret; 674 675 ret = __verify_firmware(&init, fw); 676 if (ret) { 677 ret = -EFAULT; 678 goto release_fw; 679 } 680 681 __disable_dcpu(priv); 682 683 is_big_endian = init.is_big_endian; 684 dmem_size = init.dmem_len; 685 imem_size = init.imem_len; 686 687 /* At the beginning of the firmware blob is a header. */ 688 header = (struct dpfe_firmware_header *)fw->data; 689 /* Void pointer to the beginning of the actual firmware. */ 690 fw_blob = fw->data + sizeof(*header); 691 /* IMEM comes right after the header. */ 692 imem = fw_blob; 693 /* DMEM follows after IMEM. */ 694 dmem = fw_blob + imem_size; 695 696 ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian); 697 if (ret) 698 goto release_fw; 699 ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian); 700 if (ret) 701 goto release_fw; 702 703 ret = __verify_fw_checksum(&init, priv, header, init.chksum); 704 if (ret) 705 goto release_fw; 706 707 __enable_dcpu(priv); 708 709 release_fw: 710 release_firmware(fw); 711 return ret; 712 } 713 714 static ssize_t generic_show(unsigned int command, u32 response[], 715 struct brcmstb_dpfe_priv *priv, char *buf) 716 { 717 int ret; 718 719 if (!priv) 720 return sprintf(buf, "ERROR: driver private data not set\n"); 721 722 ret = __send_command(priv, command, response); 723 if (ret < 0) 724 return sprintf(buf, "ERROR: %s\n", get_error_text(-ret)); 725 726 return 0; 727 } 728 729 static ssize_t show_info(struct device *dev, struct device_attribute *devattr, 730 char *buf) 731 { 732 u32 response[MSG_FIELD_MAX]; 733 struct brcmstb_dpfe_priv *priv; 734 unsigned int info; 735 ssize_t ret; 736 737 priv = dev_get_drvdata(dev); 738 ret = generic_show(DPFE_CMD_GET_INFO, response, priv, buf); 739 if (ret) 740 return ret; 741 742 info = response[MSG_ARG0]; 743 744 return sprintf(buf, "%u.%u.%u.%u\n", 745 (info >> 24) & 0xff, 746 (info >> 16) & 0xff, 747 (info >> 8) & 0xff, 748 info & 0xff); 749 } 750 751 static ssize_t show_refresh(struct device *dev, 752 struct device_attribute *devattr, char *buf) 753 { 754 u32 response[MSG_FIELD_MAX]; 755 void __iomem *info; 756 struct brcmstb_dpfe_priv *priv; 757 u8 refresh, sr_abort, ppre, thermal_offs, tuf; 758 u32 mr4; 759 ssize_t ret; 760 761 priv = dev_get_drvdata(dev); 762 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf); 763 if (ret) 764 return ret; 765 766 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret); 767 if (!info) 768 return ret; 769 770 mr4 = (readl_relaxed(info + DRAM_INFO_MR4) >> DRAM_INFO_MR4_SHIFT) & 771 DRAM_INFO_MR4_MASK; 772 773 refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK; 774 sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK; 775 ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK; 776 thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK; 777 tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK; 778 779 return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n", 780 readl_relaxed(info + DRAM_INFO_INTERVAL), 781 refresh, sr_abort, ppre, thermal_offs, tuf, 782 readl_relaxed(info + DRAM_INFO_ERROR)); 783 } 784 785 static ssize_t store_refresh(struct device *dev, struct device_attribute *attr, 786 const char *buf, size_t count) 787 { 788 u32 response[MSG_FIELD_MAX]; 789 struct brcmstb_dpfe_priv *priv; 790 void __iomem *info; 791 unsigned long val; 792 int ret; 793 794 if (kstrtoul(buf, 0, &val) < 0) 795 return -EINVAL; 796 797 priv = dev_get_drvdata(dev); 798 ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response); 799 if (ret) 800 return ret; 801 802 info = get_msg_ptr(priv, response[MSG_ARG0], NULL, NULL); 803 if (!info) 804 return -EIO; 805 806 writel_relaxed(val, info + DRAM_INFO_INTERVAL); 807 808 return count; 809 } 810 811 static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr, 812 char *buf) 813 { 814 u32 response[MSG_FIELD_MAX]; 815 struct brcmstb_dpfe_priv *priv; 816 void __iomem *info; 817 ssize_t ret; 818 u32 mr5, mr6, mr7, mr8, err; 819 820 priv = dev_get_drvdata(dev); 821 ret = generic_show(DPFE_CMD_GET_VENDOR, response, priv, buf); 822 if (ret) 823 return ret; 824 825 info = get_msg_ptr(priv, response[MSG_ARG0], buf, &ret); 826 if (!info) 827 return ret; 828 829 mr5 = (readl_relaxed(info + DRAM_VENDOR_MR5) >> DRAM_VENDOR_SHIFT) & 830 DRAM_VENDOR_MASK; 831 mr6 = (readl_relaxed(info + DRAM_VENDOR_MR6) >> DRAM_VENDOR_SHIFT) & 832 DRAM_VENDOR_MASK; 833 mr7 = (readl_relaxed(info + DRAM_VENDOR_MR7) >> DRAM_VENDOR_SHIFT) & 834 DRAM_VENDOR_MASK; 835 mr8 = (readl_relaxed(info + DRAM_VENDOR_MR8) >> DRAM_VENDOR_SHIFT) & 836 DRAM_VENDOR_MASK; 837 err = readl_relaxed(info + DRAM_VENDOR_ERROR) & DRAM_VENDOR_MASK; 838 839 return sprintf(buf, "%#x %#x %#x %#x %#x\n", mr5, mr6, mr7, mr8, err); 840 } 841 842 static ssize_t show_dram(struct device *dev, struct device_attribute *devattr, 843 char *buf) 844 { 845 u32 response[MSG_FIELD_MAX]; 846 struct brcmstb_dpfe_priv *priv; 847 ssize_t ret; 848 u32 mr4, mr5, mr6, mr7, mr8, err; 849 850 priv = dev_get_drvdata(dev); 851 ret = generic_show(DPFE_CMD_GET_REFRESH, response, priv, buf); 852 if (ret) 853 return ret; 854 855 mr4 = response[MSG_ARG0 + 0] & DRAM_INFO_MR4_MASK; 856 mr5 = response[MSG_ARG0 + 1] & DRAM_DDR_INFO_MASK; 857 mr6 = response[MSG_ARG0 + 2] & DRAM_DDR_INFO_MASK; 858 mr7 = response[MSG_ARG0 + 3] & DRAM_DDR_INFO_MASK; 859 mr8 = response[MSG_ARG0 + 4] & DRAM_DDR_INFO_MASK; 860 err = response[MSG_ARG0 + 5] & DRAM_DDR_INFO_MASK; 861 862 return sprintf(buf, "%#x %#x %#x %#x %#x %#x\n", mr4, mr5, mr6, mr7, 863 mr8, err); 864 } 865 866 static int brcmstb_dpfe_resume(struct platform_device *pdev) 867 { 868 struct brcmstb_dpfe_priv *priv = platform_get_drvdata(pdev); 869 870 return brcmstb_dpfe_download_firmware(priv); 871 } 872 873 static int brcmstb_dpfe_probe(struct platform_device *pdev) 874 { 875 struct device *dev = &pdev->dev; 876 struct brcmstb_dpfe_priv *priv; 877 struct resource *res; 878 int ret; 879 880 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 881 if (!priv) 882 return -ENOMEM; 883 884 priv->dev = dev; 885 886 mutex_init(&priv->lock); 887 platform_set_drvdata(pdev, priv); 888 889 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu"); 890 priv->regs = devm_ioremap_resource(dev, res); 891 if (IS_ERR(priv->regs)) { 892 dev_err(dev, "couldn't map DCPU registers\n"); 893 return -ENODEV; 894 } 895 priv->regs_size = resource_size(res); 896 897 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem"); 898 priv->dmem = devm_ioremap_resource(dev, res); 899 if (IS_ERR(priv->dmem)) { 900 dev_err(dev, "Couldn't map DCPU data memory\n"); 901 return -ENOENT; 902 } 903 priv->dmem_size = resource_size(res); 904 905 priv->imem = devm_platform_ioremap_resource_byname(pdev, "dpfe-imem"); 906 if (IS_ERR(priv->imem)) { 907 dev_err(dev, "Couldn't map DCPU instruction memory\n"); 908 return -ENOENT; 909 } 910 911 priv->dpfe_api = of_device_get_match_data(dev); 912 if (unlikely(!priv->dpfe_api)) { 913 /* 914 * It should be impossible to end up here, but to be safe we 915 * check anyway. 916 */ 917 dev_err(dev, "Couldn't determine API\n"); 918 return -ENOENT; 919 } 920 921 ret = brcmstb_dpfe_download_firmware(priv); 922 if (ret) 923 return dev_err_probe(dev, ret, "Couldn't download firmware\n"); 924 925 ret = sysfs_create_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs); 926 if (!ret) 927 dev_info(dev, "registered with API v%d.\n", 928 priv->dpfe_api->version); 929 930 return ret; 931 } 932 933 static void brcmstb_dpfe_remove(struct platform_device *pdev) 934 { 935 struct brcmstb_dpfe_priv *priv = dev_get_drvdata(&pdev->dev); 936 937 sysfs_remove_groups(&pdev->dev.kobj, priv->dpfe_api->sysfs_attrs); 938 } 939 940 static const struct of_device_id brcmstb_dpfe_of_match[] = { 941 /* Use legacy API v2 for a select number of chips */ 942 { .compatible = "brcm,bcm7268-dpfe-cpu", .data = &dpfe_api_old_v2 }, 943 { .compatible = "brcm,bcm7271-dpfe-cpu", .data = &dpfe_api_old_v2 }, 944 { .compatible = "brcm,bcm7278-dpfe-cpu", .data = &dpfe_api_old_v2 }, 945 { .compatible = "brcm,bcm7211-dpfe-cpu", .data = &dpfe_api_new_v2 }, 946 /* API v3 is the default going forward */ 947 { .compatible = "brcm,dpfe-cpu", .data = &dpfe_api_v3 }, 948 {} 949 }; 950 MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match); 951 952 static struct platform_driver brcmstb_dpfe_driver = { 953 .driver = { 954 .name = DRVNAME, 955 .of_match_table = brcmstb_dpfe_of_match, 956 }, 957 .probe = brcmstb_dpfe_probe, 958 .remove = brcmstb_dpfe_remove, 959 .resume = brcmstb_dpfe_resume, 960 }; 961 962 module_platform_driver(brcmstb_dpfe_driver); 963 964 MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>"); 965 MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver"); 966 MODULE_LICENSE("GPL"); 967