1 /* Frontend part of the Linux driver for the Afatech 9005 2 * USB1.1 DVB-T receiver. 3 * 4 * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org) 5 * 6 * Thanks to Afatech who kindly provided information. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 * 22 * see Documentation/dvb/README.dvb-usb for more information 23 */ 24 #include "af9005.h" 25 #include "af9005-script.h" 26 #include "mt2060.h" 27 #include "qt1010.h" 28 #include <asm/div64.h> 29 30 struct af9005_fe_state { 31 struct dvb_usb_device *d; 32 enum fe_status stat; 33 34 /* retraining parameters */ 35 u32 original_fcw; 36 u16 original_rf_top; 37 u16 original_if_top; 38 u16 original_if_min; 39 u16 original_aci0_if_top; 40 u16 original_aci1_if_top; 41 u16 original_aci0_if_min; 42 u8 original_if_unplug_th; 43 u8 original_rf_unplug_th; 44 u8 original_dtop_if_unplug_th; 45 u8 original_dtop_rf_unplug_th; 46 47 /* statistics */ 48 u32 pre_vit_error_count; 49 u32 pre_vit_bit_count; 50 u32 ber; 51 u32 post_vit_error_count; 52 u32 post_vit_bit_count; 53 u32 unc; 54 u16 abort_count; 55 56 int opened; 57 int strong; 58 unsigned long next_status_check; 59 struct dvb_frontend frontend; 60 }; 61 62 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi, 63 u16 reglo, u8 pos, u8 len, u16 value) 64 { 65 int ret; 66 67 if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff)))) 68 return ret; 69 return af9005_write_register_bits(d, reghi, pos, len, 70 (u8) ((value & 0x300) >> 8)); 71 } 72 73 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi, 74 u16 reglo, u8 pos, u8 len, u16 * value) 75 { 76 int ret; 77 u8 temp0, temp1; 78 79 if ((ret = af9005_read_ofdm_register(d, reglo, &temp0))) 80 return ret; 81 if ((ret = af9005_read_ofdm_register(d, reghi, &temp1))) 82 return ret; 83 switch (pos) { 84 case 0: 85 *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0; 86 break; 87 case 2: 88 *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0; 89 break; 90 case 4: 91 *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0; 92 break; 93 case 6: 94 *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0; 95 break; 96 default: 97 err("invalid pos in read word agc"); 98 return -EINVAL; 99 } 100 return 0; 101 102 } 103 104 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available) 105 { 106 struct af9005_fe_state *state = fe->demodulator_priv; 107 int ret; 108 u8 temp; 109 110 *available = false; 111 112 ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en, 113 fec_vtb_rsd_mon_en_pos, 114 fec_vtb_rsd_mon_en_len, &temp); 115 if (ret) 116 return ret; 117 if (temp & 1) { 118 ret = 119 af9005_read_register_bits(state->d, 120 xd_p_reg_ofsm_read_rbc_en, 121 reg_ofsm_read_rbc_en_pos, 122 reg_ofsm_read_rbc_en_len, &temp); 123 if (ret) 124 return ret; 125 if ((temp & 1) == 0) 126 *available = true; 127 128 } 129 return 0; 130 } 131 132 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe, 133 u32 * post_err_count, 134 u32 * post_cw_count, 135 u16 * abort_count) 136 { 137 struct af9005_fe_state *state = fe->demodulator_priv; 138 int ret; 139 u32 err_count; 140 u32 cw_count; 141 u8 temp, temp0, temp1, temp2; 142 u16 loc_abort_count; 143 144 *post_err_count = 0; 145 *post_cw_count = 0; 146 147 /* check if error bit count is ready */ 148 ret = 149 af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy, 150 fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len, 151 &temp); 152 if (ret) 153 return ret; 154 if (!temp) { 155 deb_info("rsd counter not ready\n"); 156 return 100; 157 } 158 /* get abort count */ 159 ret = 160 af9005_read_ofdm_register(state->d, 161 xd_r_fec_rsd_abort_packet_cnt_7_0, 162 &temp0); 163 if (ret) 164 return ret; 165 ret = 166 af9005_read_ofdm_register(state->d, 167 xd_r_fec_rsd_abort_packet_cnt_15_8, 168 &temp1); 169 if (ret) 170 return ret; 171 loc_abort_count = ((u16) temp1 << 8) + temp0; 172 173 /* get error count */ 174 ret = 175 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0, 176 &temp0); 177 if (ret) 178 return ret; 179 ret = 180 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8, 181 &temp1); 182 if (ret) 183 return ret; 184 ret = 185 af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16, 186 &temp2); 187 if (ret) 188 return ret; 189 err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0; 190 *post_err_count = err_count - (u32) loc_abort_count *8 * 8; 191 192 /* get RSD packet number */ 193 ret = 194 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0, 195 &temp0); 196 if (ret) 197 return ret; 198 ret = 199 af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8, 200 &temp1); 201 if (ret) 202 return ret; 203 cw_count = ((u32) temp1 << 8) + temp0; 204 if (cw_count == 0) { 205 err("wrong RSD packet count"); 206 return -EIO; 207 } 208 deb_info("POST abort count %d err count %d rsd packets %d\n", 209 loc_abort_count, err_count, cw_count); 210 *post_cw_count = cw_count - (u32) loc_abort_count; 211 *abort_count = loc_abort_count; 212 return 0; 213 214 } 215 216 static int af9005_get_post_vit_ber(struct dvb_frontend *fe, 217 u32 * post_err_count, u32 * post_cw_count, 218 u16 * abort_count) 219 { 220 u32 loc_cw_count = 0, loc_err_count; 221 u16 loc_abort_count = 0; 222 int ret; 223 224 ret = 225 af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count, 226 &loc_abort_count); 227 if (ret) 228 return ret; 229 *post_err_count = loc_err_count; 230 *post_cw_count = loc_cw_count * 204 * 8; 231 *abort_count = loc_abort_count; 232 233 return 0; 234 } 235 236 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe, 237 u32 * pre_err_count, 238 u32 * pre_bit_count) 239 { 240 struct af9005_fe_state *state = fe->demodulator_priv; 241 u8 temp, temp0, temp1, temp2; 242 u32 super_frame_count, x, bits; 243 int ret; 244 245 ret = 246 af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy, 247 fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len, 248 &temp); 249 if (ret) 250 return ret; 251 if (!temp) { 252 deb_info("viterbi counter not ready\n"); 253 return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */ 254 } 255 ret = 256 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0, 257 &temp0); 258 if (ret) 259 return ret; 260 ret = 261 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8, 262 &temp1); 263 if (ret) 264 return ret; 265 ret = 266 af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16, 267 &temp2); 268 if (ret) 269 return ret; 270 *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0; 271 272 ret = 273 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0, 274 &temp0); 275 if (ret) 276 return ret; 277 ret = 278 af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8, 279 &temp1); 280 if (ret) 281 return ret; 282 super_frame_count = ((u32) temp1 << 8) + temp0; 283 if (super_frame_count == 0) { 284 deb_info("super frame count 0\n"); 285 return 102; 286 } 287 288 /* read fft mode */ 289 ret = 290 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod, 291 reg_tpsd_txmod_pos, reg_tpsd_txmod_len, 292 &temp); 293 if (ret) 294 return ret; 295 if (temp == 0) { 296 /* 2K */ 297 x = 1512; 298 } else if (temp == 1) { 299 /* 8k */ 300 x = 6048; 301 } else { 302 err("Invalid fft mode"); 303 return -EINVAL; 304 } 305 306 /* read modulation mode */ 307 ret = 308 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const, 309 reg_tpsd_const_pos, reg_tpsd_const_len, 310 &temp); 311 if (ret) 312 return ret; 313 switch (temp) { 314 case 0: /* QPSK */ 315 bits = 2; 316 break; 317 case 1: /* QAM_16 */ 318 bits = 4; 319 break; 320 case 2: /* QAM_64 */ 321 bits = 6; 322 break; 323 default: 324 err("invalid modulation mode"); 325 return -EINVAL; 326 } 327 *pre_bit_count = super_frame_count * 68 * 4 * x * bits; 328 deb_info("PRE err count %d frame count %d bit count %d\n", 329 *pre_err_count, super_frame_count, *pre_bit_count); 330 return 0; 331 } 332 333 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe) 334 { 335 struct af9005_fe_state *state = fe->demodulator_priv; 336 int ret; 337 338 /* set super frame count to 1 */ 339 ret = 340 af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0, 341 1 & 0xff); 342 if (ret) 343 return ret; 344 ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8, 345 1 >> 8); 346 if (ret) 347 return ret; 348 /* reset pre viterbi error count */ 349 ret = 350 af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst, 351 fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len, 352 1); 353 354 return ret; 355 } 356 357 static int af9005_reset_post_viterbi(struct dvb_frontend *fe) 358 { 359 struct af9005_fe_state *state = fe->demodulator_priv; 360 int ret; 361 362 /* set packet unit */ 363 ret = 364 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0, 365 10000 & 0xff); 366 if (ret) 367 return ret; 368 ret = 369 af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8, 370 10000 >> 8); 371 if (ret) 372 return ret; 373 /* reset post viterbi error count */ 374 ret = 375 af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst, 376 fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len, 377 1); 378 379 return ret; 380 } 381 382 static int af9005_get_statistic(struct dvb_frontend *fe) 383 { 384 struct af9005_fe_state *state = fe->demodulator_priv; 385 int ret, fecavailable; 386 u64 numerator, denominator; 387 388 deb_info("GET STATISTIC\n"); 389 ret = af9005_is_fecmon_available(fe, &fecavailable); 390 if (ret) 391 return ret; 392 if (!fecavailable) { 393 deb_info("fecmon not available\n"); 394 return 0; 395 } 396 397 ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count, 398 &state->pre_vit_bit_count); 399 if (ret == 0) { 400 af9005_reset_pre_viterbi(fe); 401 if (state->pre_vit_bit_count > 0) { 402 /* according to v 0.0.4 of the dvb api ber should be a multiple 403 of 10E-9 so we have to multiply the error count by 404 10E9=1000000000 */ 405 numerator = 406 (u64) state->pre_vit_error_count * (u64) 1000000000; 407 denominator = (u64) state->pre_vit_bit_count; 408 state->ber = do_div(numerator, denominator); 409 } else { 410 state->ber = 0xffffffff; 411 } 412 } 413 414 ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count, 415 &state->post_vit_bit_count, 416 &state->abort_count); 417 if (ret == 0) { 418 ret = af9005_reset_post_viterbi(fe); 419 state->unc += state->abort_count; 420 if (ret) 421 return ret; 422 } 423 return 0; 424 } 425 426 static int af9005_fe_refresh_state(struct dvb_frontend *fe) 427 { 428 struct af9005_fe_state *state = fe->demodulator_priv; 429 if (time_after(jiffies, state->next_status_check)) { 430 deb_info("REFRESH STATE\n"); 431 432 /* statistics */ 433 if (af9005_get_statistic(fe)) 434 err("get_statistic_failed"); 435 state->next_status_check = jiffies + 250 * HZ / 1000; 436 } 437 return 0; 438 } 439 440 static int af9005_fe_read_status(struct dvb_frontend *fe, 441 enum fe_status *stat) 442 { 443 struct af9005_fe_state *state = fe->demodulator_priv; 444 u8 temp; 445 int ret; 446 447 if (fe->ops.tuner_ops.release == NULL) 448 return -ENODEV; 449 450 *stat = 0; 451 ret = af9005_read_register_bits(state->d, xd_p_agc_lock, 452 agc_lock_pos, agc_lock_len, &temp); 453 if (ret) 454 return ret; 455 if (temp) 456 *stat |= FE_HAS_SIGNAL; 457 458 ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock, 459 fd_tpsd_lock_pos, fd_tpsd_lock_len, 460 &temp); 461 if (ret) 462 return ret; 463 if (temp) 464 *stat |= FE_HAS_CARRIER; 465 466 ret = af9005_read_register_bits(state->d, 467 xd_r_mp2if_sync_byte_locked, 468 mp2if_sync_byte_locked_pos, 469 mp2if_sync_byte_locked_pos, &temp); 470 if (ret) 471 return ret; 472 if (temp) 473 *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK; 474 if (state->opened) 475 af9005_led_control(state->d, *stat & FE_HAS_LOCK); 476 477 ret = 478 af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected, 479 reg_strong_sginal_detected_pos, 480 reg_strong_sginal_detected_len, &temp); 481 if (ret) 482 return ret; 483 if (temp != state->strong) { 484 deb_info("adjust for strong signal %d\n", temp); 485 state->strong = temp; 486 } 487 return 0; 488 } 489 490 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber) 491 { 492 struct af9005_fe_state *state = fe->demodulator_priv; 493 if (fe->ops.tuner_ops.release == NULL) 494 return -ENODEV; 495 af9005_fe_refresh_state(fe); 496 *ber = state->ber; 497 return 0; 498 } 499 500 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc) 501 { 502 struct af9005_fe_state *state = fe->demodulator_priv; 503 if (fe->ops.tuner_ops.release == NULL) 504 return -ENODEV; 505 af9005_fe_refresh_state(fe); 506 *unc = state->unc; 507 return 0; 508 } 509 510 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe, 511 u16 * strength) 512 { 513 struct af9005_fe_state *state = fe->demodulator_priv; 514 int ret; 515 u8 if_gain, rf_gain; 516 517 if (fe->ops.tuner_ops.release == NULL) 518 return -ENODEV; 519 ret = 520 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain, 521 &rf_gain); 522 if (ret) 523 return ret; 524 ret = 525 af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain, 526 &if_gain); 527 if (ret) 528 return ret; 529 /* this value has no real meaning, but i don't have the tables that relate 530 the rf and if gain with the dbm, so I just scale the value */ 531 *strength = (512 - rf_gain - if_gain) << 7; 532 return 0; 533 } 534 535 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr) 536 { 537 /* the snr can be derived from the ber and the modulation 538 but I don't think this kind of complex calculations belong 539 in the driver. I may be wrong.... */ 540 return -ENOSYS; 541 } 542 543 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw) 544 { 545 u8 temp0, temp1, temp2, temp3, buf[4]; 546 int ret; 547 u32 NS_coeff1_2048Nu; 548 u32 NS_coeff1_8191Nu; 549 u32 NS_coeff1_8192Nu; 550 u32 NS_coeff1_8193Nu; 551 u32 NS_coeff2_2k; 552 u32 NS_coeff2_8k; 553 554 switch (bw) { 555 case 6000000: 556 NS_coeff1_2048Nu = 0x2ADB6DC; 557 NS_coeff1_8191Nu = 0xAB7313; 558 NS_coeff1_8192Nu = 0xAB6DB7; 559 NS_coeff1_8193Nu = 0xAB685C; 560 NS_coeff2_2k = 0x156DB6E; 561 NS_coeff2_8k = 0x55B6DC; 562 break; 563 564 case 7000000: 565 NS_coeff1_2048Nu = 0x3200001; 566 NS_coeff1_8191Nu = 0xC80640; 567 NS_coeff1_8192Nu = 0xC80000; 568 NS_coeff1_8193Nu = 0xC7F9C0; 569 NS_coeff2_2k = 0x1900000; 570 NS_coeff2_8k = 0x640000; 571 break; 572 573 case 8000000: 574 NS_coeff1_2048Nu = 0x3924926; 575 NS_coeff1_8191Nu = 0xE4996E; 576 NS_coeff1_8192Nu = 0xE49249; 577 NS_coeff1_8193Nu = 0xE48B25; 578 NS_coeff2_2k = 0x1C92493; 579 NS_coeff2_8k = 0x724925; 580 break; 581 default: 582 err("Invalid bandwidth %d.", bw); 583 return -EINVAL; 584 } 585 586 /* 587 * write NS_coeff1_2048Nu 588 */ 589 590 temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF); 591 temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8); 592 temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16); 593 temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24); 594 595 /* big endian to make 8051 happy */ 596 buf[0] = temp3; 597 buf[1] = temp2; 598 buf[2] = temp1; 599 buf[3] = temp0; 600 601 /* cfoe_NS_2k_coeff1_25_24 */ 602 ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]); 603 if (ret) 604 return ret; 605 606 /* cfoe_NS_2k_coeff1_23_16 */ 607 ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]); 608 if (ret) 609 return ret; 610 611 /* cfoe_NS_2k_coeff1_15_8 */ 612 ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]); 613 if (ret) 614 return ret; 615 616 /* cfoe_NS_2k_coeff1_7_0 */ 617 ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]); 618 if (ret) 619 return ret; 620 621 /* 622 * write NS_coeff2_2k 623 */ 624 625 temp0 = (u8) ((NS_coeff2_2k & 0x0000003F)); 626 temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6); 627 temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14); 628 temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22); 629 630 /* big endian to make 8051 happy */ 631 buf[0] = temp3; 632 buf[1] = temp2; 633 buf[2] = temp1; 634 buf[3] = temp0; 635 636 ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]); 637 if (ret) 638 return ret; 639 640 ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]); 641 if (ret) 642 return ret; 643 644 ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]); 645 if (ret) 646 return ret; 647 648 ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]); 649 if (ret) 650 return ret; 651 652 /* 653 * write NS_coeff1_8191Nu 654 */ 655 656 temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF)); 657 temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8); 658 temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16); 659 temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24); 660 661 /* big endian to make 8051 happy */ 662 buf[0] = temp3; 663 buf[1] = temp2; 664 buf[2] = temp1; 665 buf[3] = temp0; 666 667 ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]); 668 if (ret) 669 return ret; 670 671 ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]); 672 if (ret) 673 return ret; 674 675 ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]); 676 if (ret) 677 return ret; 678 679 ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]); 680 if (ret) 681 return ret; 682 683 /* 684 * write NS_coeff1_8192Nu 685 */ 686 687 temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF); 688 temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8); 689 temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16); 690 temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24); 691 692 /* big endian to make 8051 happy */ 693 buf[0] = temp3; 694 buf[1] = temp2; 695 buf[2] = temp1; 696 buf[3] = temp0; 697 698 ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]); 699 if (ret) 700 return ret; 701 702 ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]); 703 if (ret) 704 return ret; 705 706 ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]); 707 if (ret) 708 return ret; 709 710 ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]); 711 if (ret) 712 return ret; 713 714 /* 715 * write NS_coeff1_8193Nu 716 */ 717 718 temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF)); 719 temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8); 720 temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16); 721 temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24); 722 723 /* big endian to make 8051 happy */ 724 buf[0] = temp3; 725 buf[1] = temp2; 726 buf[2] = temp1; 727 buf[3] = temp0; 728 729 ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]); 730 if (ret) 731 return ret; 732 733 ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]); 734 if (ret) 735 return ret; 736 737 ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]); 738 if (ret) 739 return ret; 740 741 ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]); 742 if (ret) 743 return ret; 744 745 /* 746 * write NS_coeff2_8k 747 */ 748 749 temp0 = (u8) ((NS_coeff2_8k & 0x0000003F)); 750 temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6); 751 temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14); 752 temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22); 753 754 /* big endian to make 8051 happy */ 755 buf[0] = temp3; 756 buf[1] = temp2; 757 buf[2] = temp1; 758 buf[3] = temp0; 759 760 ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]); 761 if (ret) 762 return ret; 763 764 ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]); 765 if (ret) 766 return ret; 767 768 ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]); 769 if (ret) 770 return ret; 771 772 ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]); 773 return ret; 774 775 } 776 777 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw) 778 { 779 u8 temp; 780 switch (bw) { 781 case 6000000: 782 temp = 0; 783 break; 784 case 7000000: 785 temp = 1; 786 break; 787 case 8000000: 788 temp = 2; 789 break; 790 default: 791 err("Invalid bandwidth %d.", bw); 792 return -EINVAL; 793 } 794 return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos, 795 reg_bw_len, temp); 796 } 797 798 static int af9005_fe_power(struct dvb_frontend *fe, int on) 799 { 800 struct af9005_fe_state *state = fe->demodulator_priv; 801 u8 temp = on; 802 int ret; 803 deb_info("power %s tuner\n", on ? "on" : "off"); 804 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0); 805 return ret; 806 } 807 808 static struct mt2060_config af9005_mt2060_config = { 809 0xC0 810 }; 811 812 static struct qt1010_config af9005_qt1010_config = { 813 0xC4 814 }; 815 816 static int af9005_fe_init(struct dvb_frontend *fe) 817 { 818 struct af9005_fe_state *state = fe->demodulator_priv; 819 struct dvb_usb_adapter *adap = fe->dvb->priv; 820 int ret, i, scriptlen; 821 u8 temp, temp0 = 0, temp1 = 0, temp2 = 0; 822 u8 buf[2]; 823 u16 if1; 824 825 deb_info("in af9005_fe_init\n"); 826 827 /* reset */ 828 deb_info("reset\n"); 829 if ((ret = 830 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en, 831 4, 1, 0x01))) 832 return ret; 833 if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0))) 834 return ret; 835 /* clear ofdm reset */ 836 deb_info("clear ofdm reset\n"); 837 for (i = 0; i < 150; i++) { 838 if ((ret = 839 af9005_read_ofdm_register(state->d, 840 xd_I2C_reg_ofdm_rst, &temp))) 841 return ret; 842 if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos)) 843 break; 844 msleep(10); 845 } 846 if (i == 150) 847 return -ETIMEDOUT; 848 849 /*FIXME in the dump 850 write B200 A9 851 write xd_g_reg_ofsm_clk 7 852 read eepr c6 (2) 853 read eepr c7 (2) 854 misc ctrl 3 -> 1 855 read eepr ca (6) 856 write xd_g_reg_ofsm_clk 0 857 write B200 a1 858 */ 859 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9); 860 if (ret) 861 return ret; 862 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07); 863 if (ret) 864 return ret; 865 temp = 0x01; 866 ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0); 867 if (ret) 868 return ret; 869 ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00); 870 if (ret) 871 return ret; 872 ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1); 873 if (ret) 874 return ret; 875 876 temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos; 877 if ((ret = 878 af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst, 879 reg_ofdm_rst_pos, reg_ofdm_rst_len, 1))) 880 return ret; 881 ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst, 882 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0); 883 884 if (ret) 885 return ret; 886 /* don't know what register aefc is, but this is what the windows driver does */ 887 ret = af9005_write_ofdm_register(state->d, 0xaefc, 0); 888 if (ret) 889 return ret; 890 891 /* set stand alone chip */ 892 deb_info("set stand alone chip\n"); 893 if ((ret = 894 af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone, 895 reg_dca_stand_alone_pos, 896 reg_dca_stand_alone_len, 1))) 897 return ret; 898 899 /* set dca upper & lower chip */ 900 deb_info("set dca upper & lower chip\n"); 901 if ((ret = 902 af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip, 903 reg_dca_upper_chip_pos, 904 reg_dca_upper_chip_len, 0))) 905 return ret; 906 if ((ret = 907 af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip, 908 reg_dca_lower_chip_pos, 909 reg_dca_lower_chip_len, 0))) 910 return ret; 911 912 /* set 2wire master clock to 0x14 (for 60KHz) */ 913 deb_info("set 2wire master clock to 0x14 (for 60KHz)\n"); 914 if ((ret = 915 af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14))) 916 return ret; 917 918 /* clear dca enable chip */ 919 deb_info("clear dca enable chip\n"); 920 if ((ret = 921 af9005_write_register_bits(state->d, xd_p_reg_dca_en, 922 reg_dca_en_pos, reg_dca_en_len, 0))) 923 return ret; 924 /* FIXME these are register bits, but I don't know which ones */ 925 ret = af9005_write_ofdm_register(state->d, 0xa16c, 1); 926 if (ret) 927 return ret; 928 ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0); 929 if (ret) 930 return ret; 931 932 /* init other parameters: program cfoe and select bandwidth */ 933 deb_info("program cfoe\n"); 934 ret = af9005_fe_program_cfoe(state->d, 6000000); 935 if (ret) 936 return ret; 937 /* set read-update bit for modulation */ 938 deb_info("set read-update bit for modulation\n"); 939 if ((ret = 940 af9005_write_register_bits(state->d, xd_p_reg_feq_read_update, 941 reg_feq_read_update_pos, 942 reg_feq_read_update_len, 1))) 943 return ret; 944 945 /* sample code has a set MPEG TS code here 946 but sniffing reveals that it doesn't do it */ 947 948 /* set read-update bit to 1 for DCA modulation */ 949 deb_info("set read-update bit 1 for DCA modulation\n"); 950 if ((ret = 951 af9005_write_register_bits(state->d, xd_p_reg_dca_read_update, 952 reg_dca_read_update_pos, 953 reg_dca_read_update_len, 1))) 954 return ret; 955 956 /* enable fec monitor */ 957 deb_info("enable fec monitor\n"); 958 if ((ret = 959 af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en, 960 fec_vtb_rsd_mon_en_pos, 961 fec_vtb_rsd_mon_en_len, 1))) 962 return ret; 963 964 /* FIXME should be register bits, I don't know which ones */ 965 ret = af9005_write_ofdm_register(state->d, 0xa601, 0); 966 967 /* set api_retrain_never_freeze */ 968 deb_info("set api_retrain_never_freeze\n"); 969 if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01))) 970 return ret; 971 972 /* load init script */ 973 deb_info("load init script\n"); 974 scriptlen = sizeof(script) / sizeof(RegDesc); 975 for (i = 0; i < scriptlen; i++) { 976 if ((ret = 977 af9005_write_register_bits(state->d, script[i].reg, 978 script[i].pos, 979 script[i].len, script[i].val))) 980 return ret; 981 /* save 3 bytes of original fcw */ 982 if (script[i].reg == 0xae18) 983 temp2 = script[i].val; 984 if (script[i].reg == 0xae19) 985 temp1 = script[i].val; 986 if (script[i].reg == 0xae1a) 987 temp0 = script[i].val; 988 989 /* save original unplug threshold */ 990 if (script[i].reg == xd_p_reg_unplug_th) 991 state->original_if_unplug_th = script[i].val; 992 if (script[i].reg == xd_p_reg_unplug_rf_gain_th) 993 state->original_rf_unplug_th = script[i].val; 994 if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th) 995 state->original_dtop_if_unplug_th = script[i].val; 996 if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th) 997 state->original_dtop_rf_unplug_th = script[i].val; 998 999 } 1000 state->original_fcw = 1001 ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0; 1002 1003 1004 /* save original TOPs */ 1005 deb_info("save original TOPs\n"); 1006 1007 /* RF TOP */ 1008 ret = 1009 af9005_read_word_agc(state->d, 1010 xd_p_reg_aagc_rf_top_numerator_9_8, 1011 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2, 1012 &state->original_rf_top); 1013 if (ret) 1014 return ret; 1015 1016 /* IF TOP */ 1017 ret = 1018 af9005_read_word_agc(state->d, 1019 xd_p_reg_aagc_if_top_numerator_9_8, 1020 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2, 1021 &state->original_if_top); 1022 if (ret) 1023 return ret; 1024 1025 /* ACI 0 IF TOP */ 1026 ret = 1027 af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2, 1028 &state->original_aci0_if_top); 1029 if (ret) 1030 return ret; 1031 1032 /* ACI 1 IF TOP */ 1033 ret = 1034 af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2, 1035 &state->original_aci1_if_top); 1036 if (ret) 1037 return ret; 1038 1039 /* attach tuner and init */ 1040 if (fe->ops.tuner_ops.release == NULL) { 1041 /* read tuner and board id from eeprom */ 1042 ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2); 1043 if (ret) { 1044 err("Impossible to read EEPROM\n"); 1045 return ret; 1046 } 1047 deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]); 1048 switch (buf[0]) { 1049 case 2: /* MT2060 */ 1050 /* read if1 from eeprom */ 1051 ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2); 1052 if (ret) { 1053 err("Impossible to read EEPROM\n"); 1054 return ret; 1055 } 1056 if1 = (u16) (buf[0] << 8) + buf[1]; 1057 if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap, 1058 &af9005_mt2060_config, if1) == NULL) { 1059 deb_info("MT2060 attach failed\n"); 1060 return -ENODEV; 1061 } 1062 break; 1063 case 3: /* QT1010 */ 1064 case 9: /* QT1010B */ 1065 if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap, 1066 &af9005_qt1010_config) ==NULL) { 1067 deb_info("QT1010 attach failed\n"); 1068 return -ENODEV; 1069 } 1070 break; 1071 default: 1072 err("Unsupported tuner type %d", buf[0]); 1073 return -ENODEV; 1074 } 1075 ret = fe->ops.tuner_ops.init(fe); 1076 if (ret) 1077 return ret; 1078 } 1079 1080 deb_info("profit!\n"); 1081 return 0; 1082 } 1083 1084 static int af9005_fe_sleep(struct dvb_frontend *fe) 1085 { 1086 return af9005_fe_power(fe, 0); 1087 } 1088 1089 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire) 1090 { 1091 struct af9005_fe_state *state = fe->demodulator_priv; 1092 1093 if (acquire) { 1094 state->opened++; 1095 } else { 1096 1097 state->opened--; 1098 if (!state->opened) 1099 af9005_led_control(state->d, 0); 1100 } 1101 return 0; 1102 } 1103 1104 static int af9005_fe_set_frontend(struct dvb_frontend *fe) 1105 { 1106 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; 1107 struct af9005_fe_state *state = fe->demodulator_priv; 1108 int ret; 1109 u8 temp, temp0, temp1, temp2; 1110 1111 deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency, 1112 fep->bandwidth_hz); 1113 if (fe->ops.tuner_ops.release == NULL) { 1114 err("Tuner not attached"); 1115 return -ENODEV; 1116 } 1117 1118 deb_info("turn off led\n"); 1119 /* not in the log */ 1120 ret = af9005_led_control(state->d, 0); 1121 if (ret) 1122 return ret; 1123 /* not sure about the bits */ 1124 ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0); 1125 if (ret) 1126 return ret; 1127 1128 /* set FCW to default value */ 1129 deb_info("set FCW to default value\n"); 1130 temp0 = (u8) (state->original_fcw & 0x000000ff); 1131 temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8); 1132 temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16); 1133 ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0); 1134 if (ret) 1135 return ret; 1136 ret = af9005_write_ofdm_register(state->d, 0xae19, temp1); 1137 if (ret) 1138 return ret; 1139 ret = af9005_write_ofdm_register(state->d, 0xae18, temp2); 1140 if (ret) 1141 return ret; 1142 1143 /* restore original TOPs */ 1144 deb_info("restore original TOPs\n"); 1145 ret = 1146 af9005_write_word_agc(state->d, 1147 xd_p_reg_aagc_rf_top_numerator_9_8, 1148 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2, 1149 state->original_rf_top); 1150 if (ret) 1151 return ret; 1152 ret = 1153 af9005_write_word_agc(state->d, 1154 xd_p_reg_aagc_if_top_numerator_9_8, 1155 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2, 1156 state->original_if_top); 1157 if (ret) 1158 return ret; 1159 ret = 1160 af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2, 1161 state->original_aci0_if_top); 1162 if (ret) 1163 return ret; 1164 ret = 1165 af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2, 1166 state->original_aci1_if_top); 1167 if (ret) 1168 return ret; 1169 1170 /* select bandwidth */ 1171 deb_info("select bandwidth"); 1172 ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz); 1173 if (ret) 1174 return ret; 1175 ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz); 1176 if (ret) 1177 return ret; 1178 1179 /* clear easy mode flag */ 1180 deb_info("clear easy mode flag\n"); 1181 ret = af9005_write_ofdm_register(state->d, 0xaefd, 0); 1182 if (ret) 1183 return ret; 1184 1185 /* set unplug threshold to original value */ 1186 deb_info("set unplug threshold to original value\n"); 1187 ret = 1188 af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th, 1189 state->original_if_unplug_th); 1190 if (ret) 1191 return ret; 1192 /* set tuner */ 1193 deb_info("set tuner\n"); 1194 ret = fe->ops.tuner_ops.set_params(fe); 1195 if (ret) 1196 return ret; 1197 1198 /* trigger ofsm */ 1199 deb_info("trigger ofsm\n"); 1200 temp = 0; 1201 ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1); 1202 if (ret) 1203 return ret; 1204 1205 /* clear retrain and freeze flag */ 1206 deb_info("clear retrain and freeze flag\n"); 1207 ret = 1208 af9005_write_register_bits(state->d, 1209 xd_p_reg_api_retrain_request, 1210 reg_api_retrain_request_pos, 2, 0); 1211 if (ret) 1212 return ret; 1213 1214 /* reset pre viterbi and post viterbi registers and statistics */ 1215 af9005_reset_pre_viterbi(fe); 1216 af9005_reset_post_viterbi(fe); 1217 state->pre_vit_error_count = 0; 1218 state->pre_vit_bit_count = 0; 1219 state->ber = 0; 1220 state->post_vit_error_count = 0; 1221 /* state->unc = 0; commented out since it should be ever increasing */ 1222 state->abort_count = 0; 1223 1224 state->next_status_check = jiffies; 1225 state->strong = -1; 1226 1227 return 0; 1228 } 1229 1230 static int af9005_fe_get_frontend(struct dvb_frontend *fe) 1231 { 1232 struct dtv_frontend_properties *fep = &fe->dtv_property_cache; 1233 struct af9005_fe_state *state = fe->demodulator_priv; 1234 int ret; 1235 u8 temp; 1236 1237 /* mode */ 1238 ret = 1239 af9005_read_register_bits(state->d, xd_g_reg_tpsd_const, 1240 reg_tpsd_const_pos, reg_tpsd_const_len, 1241 &temp); 1242 if (ret) 1243 return ret; 1244 deb_info("===== fe_get_frontend_legacy = =============\n"); 1245 deb_info("CONSTELLATION "); 1246 switch (temp) { 1247 case 0: 1248 fep->modulation = QPSK; 1249 deb_info("QPSK\n"); 1250 break; 1251 case 1: 1252 fep->modulation = QAM_16; 1253 deb_info("QAM_16\n"); 1254 break; 1255 case 2: 1256 fep->modulation = QAM_64; 1257 deb_info("QAM_64\n"); 1258 break; 1259 } 1260 1261 /* tps hierarchy and alpha value */ 1262 ret = 1263 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier, 1264 reg_tpsd_hier_pos, reg_tpsd_hier_len, 1265 &temp); 1266 if (ret) 1267 return ret; 1268 deb_info("HIERARCHY "); 1269 switch (temp) { 1270 case 0: 1271 fep->hierarchy = HIERARCHY_NONE; 1272 deb_info("NONE\n"); 1273 break; 1274 case 1: 1275 fep->hierarchy = HIERARCHY_1; 1276 deb_info("1\n"); 1277 break; 1278 case 2: 1279 fep->hierarchy = HIERARCHY_2; 1280 deb_info("2\n"); 1281 break; 1282 case 3: 1283 fep->hierarchy = HIERARCHY_4; 1284 deb_info("4\n"); 1285 break; 1286 } 1287 1288 /* high/low priority */ 1289 ret = 1290 af9005_read_register_bits(state->d, xd_g_reg_dec_pri, 1291 reg_dec_pri_pos, reg_dec_pri_len, &temp); 1292 if (ret) 1293 return ret; 1294 /* if temp is set = high priority */ 1295 deb_info("PRIORITY %s\n", temp ? "high" : "low"); 1296 1297 /* high coderate */ 1298 ret = 1299 af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr, 1300 reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len, 1301 &temp); 1302 if (ret) 1303 return ret; 1304 deb_info("CODERATE HP "); 1305 switch (temp) { 1306 case 0: 1307 fep->code_rate_HP = FEC_1_2; 1308 deb_info("FEC_1_2\n"); 1309 break; 1310 case 1: 1311 fep->code_rate_HP = FEC_2_3; 1312 deb_info("FEC_2_3\n"); 1313 break; 1314 case 2: 1315 fep->code_rate_HP = FEC_3_4; 1316 deb_info("FEC_3_4\n"); 1317 break; 1318 case 3: 1319 fep->code_rate_HP = FEC_5_6; 1320 deb_info("FEC_5_6\n"); 1321 break; 1322 case 4: 1323 fep->code_rate_HP = FEC_7_8; 1324 deb_info("FEC_7_8\n"); 1325 break; 1326 } 1327 1328 /* low coderate */ 1329 ret = 1330 af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr, 1331 reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len, 1332 &temp); 1333 if (ret) 1334 return ret; 1335 deb_info("CODERATE LP "); 1336 switch (temp) { 1337 case 0: 1338 fep->code_rate_LP = FEC_1_2; 1339 deb_info("FEC_1_2\n"); 1340 break; 1341 case 1: 1342 fep->code_rate_LP = FEC_2_3; 1343 deb_info("FEC_2_3\n"); 1344 break; 1345 case 2: 1346 fep->code_rate_LP = FEC_3_4; 1347 deb_info("FEC_3_4\n"); 1348 break; 1349 case 3: 1350 fep->code_rate_LP = FEC_5_6; 1351 deb_info("FEC_5_6\n"); 1352 break; 1353 case 4: 1354 fep->code_rate_LP = FEC_7_8; 1355 deb_info("FEC_7_8\n"); 1356 break; 1357 } 1358 1359 /* guard interval */ 1360 ret = 1361 af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi, 1362 reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp); 1363 if (ret) 1364 return ret; 1365 deb_info("GUARD INTERVAL "); 1366 switch (temp) { 1367 case 0: 1368 fep->guard_interval = GUARD_INTERVAL_1_32; 1369 deb_info("1_32\n"); 1370 break; 1371 case 1: 1372 fep->guard_interval = GUARD_INTERVAL_1_16; 1373 deb_info("1_16\n"); 1374 break; 1375 case 2: 1376 fep->guard_interval = GUARD_INTERVAL_1_8; 1377 deb_info("1_8\n"); 1378 break; 1379 case 3: 1380 fep->guard_interval = GUARD_INTERVAL_1_4; 1381 deb_info("1_4\n"); 1382 break; 1383 } 1384 1385 /* fft */ 1386 ret = 1387 af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod, 1388 reg_tpsd_txmod_pos, reg_tpsd_txmod_len, 1389 &temp); 1390 if (ret) 1391 return ret; 1392 deb_info("TRANSMISSION MODE "); 1393 switch (temp) { 1394 case 0: 1395 fep->transmission_mode = TRANSMISSION_MODE_2K; 1396 deb_info("2K\n"); 1397 break; 1398 case 1: 1399 fep->transmission_mode = TRANSMISSION_MODE_8K; 1400 deb_info("8K\n"); 1401 break; 1402 } 1403 1404 /* bandwidth */ 1405 ret = 1406 af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos, 1407 reg_bw_len, &temp); 1408 deb_info("BANDWIDTH "); 1409 switch (temp) { 1410 case 0: 1411 fep->bandwidth_hz = 6000000; 1412 deb_info("6\n"); 1413 break; 1414 case 1: 1415 fep->bandwidth_hz = 7000000; 1416 deb_info("7\n"); 1417 break; 1418 case 2: 1419 fep->bandwidth_hz = 8000000; 1420 deb_info("8\n"); 1421 break; 1422 } 1423 return 0; 1424 } 1425 1426 static void af9005_fe_release(struct dvb_frontend *fe) 1427 { 1428 struct af9005_fe_state *state = 1429 (struct af9005_fe_state *)fe->demodulator_priv; 1430 kfree(state); 1431 } 1432 1433 static struct dvb_frontend_ops af9005_fe_ops; 1434 1435 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d) 1436 { 1437 struct af9005_fe_state *state = NULL; 1438 1439 /* allocate memory for the internal state */ 1440 state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL); 1441 if (state == NULL) 1442 goto error; 1443 1444 deb_info("attaching frontend af9005\n"); 1445 1446 state->d = d; 1447 state->opened = 0; 1448 1449 memcpy(&state->frontend.ops, &af9005_fe_ops, 1450 sizeof(struct dvb_frontend_ops)); 1451 state->frontend.demodulator_priv = state; 1452 1453 return &state->frontend; 1454 error: 1455 return NULL; 1456 } 1457 1458 static struct dvb_frontend_ops af9005_fe_ops = { 1459 .delsys = { SYS_DVBT }, 1460 .info = { 1461 .name = "AF9005 USB DVB-T", 1462 .frequency_min = 44250000, 1463 .frequency_max = 867250000, 1464 .frequency_stepsize = 250000, 1465 .caps = FE_CAN_INVERSION_AUTO | 1466 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 1467 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO | 1468 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 1469 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO | 1470 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | 1471 FE_CAN_HIERARCHY_AUTO, 1472 }, 1473 1474 .release = af9005_fe_release, 1475 1476 .init = af9005_fe_init, 1477 .sleep = af9005_fe_sleep, 1478 .ts_bus_ctrl = af9005_ts_bus_ctrl, 1479 1480 .set_frontend = af9005_fe_set_frontend, 1481 .get_frontend = af9005_fe_get_frontend, 1482 1483 .read_status = af9005_fe_read_status, 1484 .read_ber = af9005_fe_read_ber, 1485 .read_signal_strength = af9005_fe_read_signal_strength, 1486 .read_snr = af9005_fe_read_snr, 1487 .read_ucblocks = af9005_fe_read_unc_blocks, 1488 }; 1489