1 /* 2 * Realtek RTL28xxU DVB USB driver 3 * 4 * Copyright (C) 2009 Antti Palosaari <crope@iki.fi> 5 * Copyright (C) 2011 Antti Palosaari <crope@iki.fi> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, write to the Free Software Foundation, Inc., 19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 20 */ 21 22 #ifndef RTL28XXU_H 23 #define RTL28XXU_H 24 25 #include "dvb_usb.h" 26 27 /* 28 * USB commands 29 * (usb_control_msg() index parameter) 30 */ 31 32 #define DEMOD 0x0000 33 #define USB 0x0100 34 #define SYS 0x0200 35 #define I2C 0x0300 36 #define I2C_DA 0x0600 37 38 #define CMD_WR_FLAG 0x0010 39 #define CMD_DEMOD_RD 0x0000 40 #define CMD_DEMOD_WR 0x0010 41 #define CMD_USB_RD 0x0100 42 #define CMD_USB_WR 0x0110 43 #define CMD_SYS_RD 0x0200 44 #define CMD_IR_RD 0x0201 45 #define CMD_IR_WR 0x0211 46 #define CMD_SYS_WR 0x0210 47 #define CMD_I2C_RD 0x0300 48 #define CMD_I2C_WR 0x0310 49 #define CMD_I2C_DA_RD 0x0600 50 #define CMD_I2C_DA_WR 0x0610 51 52 53 struct rtl28xxu_priv { 54 u8 chip_id; 55 u8 tuner; 56 char *tuner_name; 57 u8 page; /* integrated demod active register page */ 58 bool rc_active; 59 }; 60 61 enum rtl28xxu_chip_id { 62 CHIP_ID_NONE, 63 CHIP_ID_RTL2831U, 64 CHIP_ID_RTL2832U, 65 }; 66 67 /* XXX: Hack. This must be keep sync with rtl2832 demod driver. */ 68 enum rtl28xxu_tuner { 69 TUNER_NONE, 70 71 TUNER_RTL2830_QT1010 = 0x10, 72 TUNER_RTL2830_MT2060, 73 TUNER_RTL2830_MXL5005S, 74 75 TUNER_RTL2832_MT2266 = 0x20, 76 TUNER_RTL2832_FC2580, 77 TUNER_RTL2832_MT2063, 78 TUNER_RTL2832_MAX3543, 79 TUNER_RTL2832_TUA9001, 80 TUNER_RTL2832_MXL5007T, 81 TUNER_RTL2832_FC0012, 82 TUNER_RTL2832_E4000, 83 TUNER_RTL2832_TDA18272, 84 TUNER_RTL2832_FC0013, 85 }; 86 87 struct rtl28xxu_req { 88 u16 value; 89 u16 index; 90 u16 size; 91 u8 *data; 92 }; 93 94 struct rtl28xxu_reg_val { 95 u16 reg; 96 u8 val; 97 }; 98 99 /* 100 * memory map 101 * 102 * 0x0000 DEMOD : demodulator 103 * 0x2000 USB : SIE, USB endpoint, debug, DMA 104 * 0x3000 SYS : system 105 * 0xfc00 RC : remote controller (not RTL2831U) 106 */ 107 108 /* 109 * USB registers 110 */ 111 /* SIE Control Registers */ 112 #define USB_SYSCTL 0x2000 /* USB system control */ 113 #define USB_SYSCTL_0 0x2000 /* USB system control */ 114 #define USB_SYSCTL_1 0x2001 /* USB system control */ 115 #define USB_SYSCTL_2 0x2002 /* USB system control */ 116 #define USB_SYSCTL_3 0x2003 /* USB system control */ 117 #define USB_IRQSTAT 0x2008 /* SIE interrupt status */ 118 #define USB_IRQEN 0x200C /* SIE interrupt enable */ 119 #define USB_CTRL 0x2010 /* USB control */ 120 #define USB_STAT 0x2014 /* USB status */ 121 #define USB_DEVADDR 0x2018 /* USB device address */ 122 #define USB_TEST 0x201C /* USB test mode */ 123 #define USB_FRAME_NUMBER 0x2020 /* frame number */ 124 #define USB_FIFO_ADDR 0x2028 /* address of SIE FIFO RAM */ 125 #define USB_FIFO_CMD 0x202A /* SIE FIFO RAM access command */ 126 #define USB_FIFO_DATA 0x2030 /* SIE FIFO RAM data */ 127 /* Endpoint Registers */ 128 #define EP0_SETUPA 0x20F8 /* EP 0 setup packet lower byte */ 129 #define EP0_SETUPB 0x20FC /* EP 0 setup packet higher byte */ 130 #define USB_EP0_CFG 0x2104 /* EP 0 configure */ 131 #define USB_EP0_CTL 0x2108 /* EP 0 control */ 132 #define USB_EP0_STAT 0x210C /* EP 0 status */ 133 #define USB_EP0_IRQSTAT 0x2110 /* EP 0 interrupt status */ 134 #define USB_EP0_IRQEN 0x2114 /* EP 0 interrupt enable */ 135 #define USB_EP0_MAXPKT 0x2118 /* EP 0 max packet size */ 136 #define USB_EP0_BC 0x2120 /* EP 0 FIFO byte counter */ 137 #define USB_EPA_CFG 0x2144 /* EP A configure */ 138 #define USB_EPA_CFG_0 0x2144 /* EP A configure */ 139 #define USB_EPA_CFG_1 0x2145 /* EP A configure */ 140 #define USB_EPA_CFG_2 0x2146 /* EP A configure */ 141 #define USB_EPA_CFG_3 0x2147 /* EP A configure */ 142 #define USB_EPA_CTL 0x2148 /* EP A control */ 143 #define USB_EPA_CTL_0 0x2148 /* EP A control */ 144 #define USB_EPA_CTL_1 0x2149 /* EP A control */ 145 #define USB_EPA_CTL_2 0x214A /* EP A control */ 146 #define USB_EPA_CTL_3 0x214B /* EP A control */ 147 #define USB_EPA_STAT 0x214C /* EP A status */ 148 #define USB_EPA_IRQSTAT 0x2150 /* EP A interrupt status */ 149 #define USB_EPA_IRQEN 0x2154 /* EP A interrupt enable */ 150 #define USB_EPA_MAXPKT 0x2158 /* EP A max packet size */ 151 #define USB_EPA_MAXPKT_0 0x2158 /* EP A max packet size */ 152 #define USB_EPA_MAXPKT_1 0x2159 /* EP A max packet size */ 153 #define USB_EPA_MAXPKT_2 0x215A /* EP A max packet size */ 154 #define USB_EPA_MAXPKT_3 0x215B /* EP A max packet size */ 155 #define USB_EPA_FIFO_CFG 0x2160 /* EP A FIFO configure */ 156 #define USB_EPA_FIFO_CFG_0 0x2160 /* EP A FIFO configure */ 157 #define USB_EPA_FIFO_CFG_1 0x2161 /* EP A FIFO configure */ 158 #define USB_EPA_FIFO_CFG_2 0x2162 /* EP A FIFO configure */ 159 #define USB_EPA_FIFO_CFG_3 0x2163 /* EP A FIFO configure */ 160 /* Debug Registers */ 161 #define USB_PHYTSTDIS 0x2F04 /* PHY test disable */ 162 #define USB_TOUT_VAL 0x2F08 /* USB time-out time */ 163 #define USB_VDRCTRL 0x2F10 /* UTMI vendor signal control */ 164 #define USB_VSTAIN 0x2F14 /* UTMI vendor signal status in */ 165 #define USB_VLOADM 0x2F18 /* UTMI load vendor signal status in */ 166 #define USB_VSTAOUT 0x2F1C /* UTMI vendor signal status out */ 167 #define USB_UTMI_TST 0x2F80 /* UTMI test */ 168 #define USB_UTMI_STATUS 0x2F84 /* UTMI status */ 169 #define USB_TSTCTL 0x2F88 /* test control */ 170 #define USB_TSTCTL2 0x2F8C /* test control 2 */ 171 #define USB_PID_FORCE 0x2F90 /* force PID */ 172 #define USB_PKTERR_CNT 0x2F94 /* packet error counter */ 173 #define USB_RXERR_CNT 0x2F98 /* RX error counter */ 174 #define USB_MEM_BIST 0x2F9C /* MEM BIST test */ 175 #define USB_SLBBIST 0x2FA0 /* self-loop-back BIST */ 176 #define USB_CNTTEST 0x2FA4 /* counter test */ 177 #define USB_PHYTST 0x2FC0 /* USB PHY test */ 178 #define USB_DBGIDX 0x2FF0 /* select individual block debug signal */ 179 #define USB_DBGMUX 0x2FF4 /* debug signal module mux */ 180 181 /* 182 * SYS registers 183 */ 184 /* demod control registers */ 185 #define SYS_SYS0 0x3000 /* include DEMOD_CTL, GPO, GPI, GPOE */ 186 #define SYS_DEMOD_CTL 0x3000 /* control register for DVB-T demodulator */ 187 /* GPIO registers */ 188 #define SYS_GPIO_OUT_VAL 0x3001 /* output value of GPIO */ 189 #define SYS_GPIO_IN_VAL 0x3002 /* input value of GPIO */ 190 #define SYS_GPIO_OUT_EN 0x3003 /* output enable of GPIO */ 191 #define SYS_SYS1 0x3004 /* include GPD, SYSINTE, SYSINTS, GP_CFG0 */ 192 #define SYS_GPIO_DIR 0x3004 /* direction control for GPIO */ 193 #define SYS_SYSINTE 0x3005 /* system interrupt enable */ 194 #define SYS_SYSINTS 0x3006 /* system interrupt status */ 195 #define SYS_GPIO_CFG0 0x3007 /* PAD configuration for GPIO0-GPIO3 */ 196 #define SYS_SYS2 0x3008 /* include GP_CFG1 and 3 reserved bytes */ 197 #define SYS_GPIO_CFG1 0x3008 /* PAD configuration for GPIO4 */ 198 #define SYS_DEMOD_CTL1 0x300B 199 200 /* IrDA registers */ 201 #define SYS_IRRC_PSR 0x3020 /* IR protocol selection */ 202 #define SYS_IRRC_PER 0x3024 /* IR protocol extension */ 203 #define SYS_IRRC_SF 0x3028 /* IR sampling frequency */ 204 #define SYS_IRRC_DPIR 0x302C /* IR data package interval */ 205 #define SYS_IRRC_CR 0x3030 /* IR control */ 206 #define SYS_IRRC_RP 0x3034 /* IR read port */ 207 #define SYS_IRRC_SR 0x3038 /* IR status */ 208 /* I2C master registers */ 209 #define SYS_I2CCR 0x3040 /* I2C clock */ 210 #define SYS_I2CMCR 0x3044 /* I2C master control */ 211 #define SYS_I2CMSTR 0x3048 /* I2C master SCL timing */ 212 #define SYS_I2CMSR 0x304C /* I2C master status */ 213 #define SYS_I2CMFR 0x3050 /* I2C master FIFO */ 214 215 /* 216 * IR registers 217 */ 218 #define IR_RX_BUF 0xFC00 219 #define IR_RX_IE 0xFD00 220 #define IR_RX_IF 0xFD01 221 #define IR_RX_CTRL 0xFD02 222 #define IR_RX_CFG 0xFD03 223 #define IR_MAX_DURATION0 0xFD04 224 #define IR_MAX_DURATION1 0xFD05 225 #define IR_IDLE_LEN0 0xFD06 226 #define IR_IDLE_LEN1 0xFD07 227 #define IR_GLITCH_LEN 0xFD08 228 #define IR_RX_BUF_CTRL 0xFD09 229 #define IR_RX_BUF_DATA 0xFD0A 230 #define IR_RX_BC 0xFD0B 231 #define IR_RX_CLK 0xFD0C 232 #define IR_RX_C_COUNT_L 0xFD0D 233 #define IR_RX_C_COUNT_H 0xFD0E 234 #define IR_SUSPEND_CTRL 0xFD10 235 #define IR_ERR_TOL_CTRL 0xFD11 236 #define IR_UNIT_LEN 0xFD12 237 #define IR_ERR_TOL_LEN 0xFD13 238 #define IR_MAX_H_TOL_LEN 0xFD14 239 #define IR_MAX_L_TOL_LEN 0xFD15 240 #define IR_MASK_CTRL 0xFD16 241 #define IR_MASK_DATA 0xFD17 242 #define IR_RES_MASK_ADDR 0xFD18 243 #define IR_RES_MASK_T_LEN 0xFD19 244 245 #endif 246