1 /* 2 * mxl111sf-reg.h - driver for the MaxLinear MXL111SF 3 * 4 * Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org> 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #ifndef _DVB_USB_MXL111SF_REG_H_ 22 #define _DVB_USB_MXL111SF_REG_H_ 23 24 #define CHIP_ID_REG 0xFC 25 #define TOP_CHIP_REV_ID_REG 0xFA 26 27 #define V6_SNR_RB_LSB_REG 0x27 28 #define V6_SNR_RB_MSB_REG 0x28 29 30 #define V6_N_ACCUMULATE_REG 0x11 31 #define V6_RS_AVG_ERRORS_LSB_REG 0x2C 32 #define V6_RS_AVG_ERRORS_MSB_REG 0x2D 33 34 #define V6_IRQ_STATUS_REG 0x24 35 #define IRQ_MASK_FEC_LOCK 0x10 36 37 #define V6_SYNC_LOCK_REG 0x28 38 #define SYNC_LOCK_MASK 0x10 39 40 #define V6_RS_LOCK_DET_REG 0x28 41 #define RS_LOCK_DET_MASK 0x08 42 43 #define V6_INITACQ_NODETECT_REG 0x20 44 #define V6_FORCE_NFFT_CPSIZE_REG 0x20 45 46 #define V6_CODE_RATE_TPS_REG 0x29 47 #define V6_CODE_RATE_TPS_MASK 0x07 48 49 50 #define V6_CP_LOCK_DET_REG 0x28 51 #define V6_CP_LOCK_DET_MASK 0x04 52 53 #define V6_TPS_HIERACHY_REG 0x29 54 #define V6_TPS_HIERARCHY_INFO_MASK 0x40 55 56 #define V6_MODORDER_TPS_REG 0x2A 57 #define V6_PARAM_CONSTELLATION_MASK 0x30 58 59 #define V6_MODE_TPS_REG 0x2A 60 #define V6_PARAM_FFT_MODE_MASK 0x0C 61 62 63 #define V6_CP_TPS_REG 0x29 64 #define V6_PARAM_GI_MASK 0x30 65 66 #define V6_TPS_LOCK_REG 0x2A 67 #define V6_PARAM_TPS_LOCK_MASK 0x40 68 69 #define V6_FEC_PER_COUNT_REG 0x2E 70 #define V6_FEC_PER_SCALE_REG 0x2B 71 #define V6_FEC_PER_SCALE_MASK 0x03 72 #define V6_FEC_PER_CLR_REG 0x20 73 #define V6_FEC_PER_CLR_MASK 0x01 74 75 #define V6_PIN_MUX_MODE_REG 0x1B 76 #define V6_ENABLE_PIN_MUX 0x1E 77 78 #define V6_I2S_NUM_SAMPLES_REG 0x16 79 80 #define V6_MPEG_IN_CLK_INV_REG 0x17 81 #define V6_MPEG_IN_CTRL_REG 0x18 82 83 #define V6_INVERTED_CLK_PHASE 0x20 84 #define V6_MPEG_IN_DATA_PARALLEL 0x01 85 #define V6_MPEG_IN_DATA_SERIAL 0x02 86 87 #define V6_INVERTED_MPEG_SYNC 0x04 88 #define V6_INVERTED_MPEG_VALID 0x08 89 90 #define TSIF_INPUT_PARALLEL 0 91 #define TSIF_INPUT_SERIAL 1 92 #define TSIF_NORMAL 0 93 94 #define V6_MPEG_INOUT_BIT_ORDER_CTRL_REG 0x19 95 #define V6_MPEG_SER_MSB_FIRST 0x80 96 #define MPEG_SER_MSB_FIRST_ENABLED 0x01 97 98 #define V6_656_I2S_BUFF_STATUS_REG 0x2F 99 #define V6_656_OVERFLOW_MASK_BIT 0x08 100 #define V6_I2S_OVERFLOW_MASK_BIT 0x01 101 102 #define V6_I2S_STREAM_START_BIT_REG 0x14 103 #define V6_I2S_STREAM_END_BIT_REG 0x15 104 #define I2S_RIGHT_JUSTIFIED 0 105 #define I2S_LEFT_JUSTIFIED 1 106 #define I2S_DATA_FORMAT 2 107 108 #define V6_TUNER_LOOP_THRU_CONTROL_REG 0x09 109 #define V6_ENABLE_LOOP_THRU 0x01 110 111 #define TOTAL_NUM_IF_OUTPUT_FREQ 16 112 113 #define TUNER_NORMAL_IF_SPECTRUM 0x0 114 #define TUNER_INVERT_IF_SPECTRUM 0x10 115 116 #define V6_TUNER_IF_SEL_REG 0x06 117 #define V6_TUNER_IF_FCW_REG 0x3C 118 #define V6_TUNER_IF_FCW_BYP_REG 0x3D 119 #define V6_RF_LOCK_STATUS_REG 0x23 120 121 #define NUM_DIG_TV_CHANNEL 1000 122 123 #define V6_DIG_CLK_FREQ_SEL_REG 0x07 124 #define V6_REF_SYNTH_INT_REG 0x5C 125 #define V6_REF_SYNTH_REMAIN_REG 0x58 126 #define V6_DIG_RFREFSELECT_REG 0x32 127 #define V6_XTAL_CLK_OUT_GAIN_REG 0x31 128 #define V6_TUNER_LOOP_THRU_CTRL_REG 0x09 129 #define V6_DIG_XTAL_ENABLE_REG 0x06 130 #define V6_DIG_XTAL_BIAS_REG 0x66 131 #define V6_XTAL_CAP_REG 0x08 132 133 #define V6_GPO_CTRL_REG 0x18 134 #define MXL_GPO_0 0x00 135 #define MXL_GPO_1 0x01 136 #define V6_GPO_0_MASK 0x10 137 #define V6_GPO_1_MASK 0x20 138 139 #define V6_111SF_GPO_CTRL_REG 0x19 140 #define MXL_111SF_GPO_1 0x00 141 #define MXL_111SF_GPO_2 0x01 142 #define MXL_111SF_GPO_3 0x02 143 #define MXL_111SF_GPO_4 0x03 144 #define MXL_111SF_GPO_5 0x04 145 #define MXL_111SF_GPO_6 0x05 146 #define MXL_111SF_GPO_7 0x06 147 148 #define MXL_111SF_GPO_0_MASK 0x01 149 #define MXL_111SF_GPO_1_MASK 0x02 150 #define MXL_111SF_GPO_2_MASK 0x04 151 #define MXL_111SF_GPO_3_MASK 0x08 152 #define MXL_111SF_GPO_4_MASK 0x10 153 #define MXL_111SF_GPO_5_MASK 0x20 154 #define MXL_111SF_GPO_6_MASK 0x40 155 156 #define V6_ATSC_CONFIG_REG 0x0A 157 158 #define MXL_MODE_REG 0x03 159 #define START_TUNE_REG 0x1C 160 161 #define V6_IDAC_HYSTERESIS_REG 0x0B 162 #define V6_IDAC_SETTINGS_REG 0x0C 163 #define IDAC_MANUAL_CONTROL 1 164 #define IDAC_CURRENT_SINKING_ENABLE 1 165 #define IDAC_MANUAL_CONTROL_BIT_MASK 0x80 166 #define IDAC_CURRENT_SINKING_BIT_MASK 0x40 167 168 #define V8_SPI_MODE_REG 0xE9 169 170 #define V6_DIG_RF_PWR_LSB_REG 0x46 171 #define V6_DIG_RF_PWR_MSB_REG 0x47 172 173 #endif /* _DVB_USB_MXL111SF_REG_H_ */ 174