1 /* 2 cx231xx_avcore.c - driver for Conexant Cx23100/101/102 3 USB video capture devices 4 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 6 7 This program contains the specific code to control the avdecoder chip and 8 other related usb control functions for cx231xx based chipset. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 2 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program; if not, write to the Free Software 22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/list.h> 27 #include <linux/module.h> 28 #include <linux/kernel.h> 29 #include <linux/bitmap.h> 30 #include <linux/usb.h> 31 #include <linux/i2c.h> 32 #include <linux/mm.h> 33 #include <linux/mutex.h> 34 #include <media/tuner.h> 35 36 #include <media/v4l2-common.h> 37 #include <media/v4l2-ioctl.h> 38 #include <media/v4l2-chip-ident.h> 39 40 #include "cx231xx.h" 41 #include "cx231xx-dif.h" 42 43 #define TUNER_MODE_FM_RADIO 0 44 /****************************************************************************** 45 -: BLOCK ARRANGEMENT :- 46 I2S block ----------------------| 47 [I2S audio] | 48 | 49 Analog Front End --> Direct IF -|-> Cx25840 --> Audio 50 [video & audio] | [Audio] 51 | 52 |-> Cx25840 --> Video 53 [Video] 54 55 *******************************************************************************/ 56 /****************************************************************************** 57 * VERVE REGISTER * 58 * * 59 ******************************************************************************/ 60 static int verve_write_byte(struct cx231xx *dev, u8 saddr, u8 data) 61 { 62 return cx231xx_write_i2c_data(dev, VERVE_I2C_ADDRESS, 63 saddr, 1, data, 1); 64 } 65 66 static int verve_read_byte(struct cx231xx *dev, u8 saddr, u8 *data) 67 { 68 int status; 69 u32 temp = 0; 70 71 status = cx231xx_read_i2c_data(dev, VERVE_I2C_ADDRESS, 72 saddr, 1, &temp, 1); 73 *data = (u8) temp; 74 return status; 75 } 76 void initGPIO(struct cx231xx *dev) 77 { 78 u32 _gpio_direction = 0; 79 u32 value = 0; 80 u8 val = 0; 81 82 _gpio_direction = _gpio_direction & 0xFC0003FF; 83 _gpio_direction = _gpio_direction | 0x03FDFC00; 84 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); 85 86 verve_read_byte(dev, 0x07, &val); 87 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 88 verve_write_byte(dev, 0x07, 0xF4); 89 verve_read_byte(dev, 0x07, &val); 90 cx231xx_info(" verve_read_byte address0x07=0x%x\n", val); 91 92 cx231xx_capture_start(dev, 1, Vbi); 93 94 cx231xx_mode_register(dev, EP_MODE_SET, 0x0500FE00); 95 cx231xx_mode_register(dev, GBULK_BIT_EN, 0xFFFDFFFF); 96 97 } 98 void uninitGPIO(struct cx231xx *dev) 99 { 100 u8 value[4] = { 0, 0, 0, 0 }; 101 102 cx231xx_capture_start(dev, 0, Vbi); 103 verve_write_byte(dev, 0x07, 0x14); 104 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 105 0x68, value, 4); 106 } 107 108 /****************************************************************************** 109 * A F E - B L O C K C O N T R O L functions * 110 * [ANALOG FRONT END] * 111 ******************************************************************************/ 112 static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 113 { 114 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS, 115 saddr, 2, data, 1); 116 } 117 118 static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 119 { 120 int status; 121 u32 temp = 0; 122 123 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS, 124 saddr, 2, &temp, 1); 125 *data = (u8) temp; 126 return status; 127 } 128 129 int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count) 130 { 131 int status = 0; 132 u8 temp = 0; 133 u8 afe_power_status = 0; 134 int i = 0; 135 136 /* super block initialize */ 137 temp = (u8) (ref_count & 0xff); 138 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp); 139 if (status < 0) 140 return status; 141 142 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status); 143 if (status < 0) 144 return status; 145 146 temp = (u8) ((ref_count & 0x300) >> 8); 147 temp |= 0x40; 148 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp); 149 if (status < 0) 150 return status; 151 152 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f); 153 if (status < 0) 154 return status; 155 156 /* enable pll */ 157 while (afe_power_status != 0x18) { 158 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18); 159 if (status < 0) { 160 cx231xx_info( 161 ": Init Super Block failed in send cmd\n"); 162 break; 163 } 164 165 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status); 166 afe_power_status &= 0xff; 167 if (status < 0) { 168 cx231xx_info( 169 ": Init Super Block failed in receive cmd\n"); 170 break; 171 } 172 i++; 173 if (i == 10) { 174 cx231xx_info( 175 ": Init Super Block force break in loop !!!!\n"); 176 status = -1; 177 break; 178 } 179 } 180 181 if (status < 0) 182 return status; 183 184 /* start tuning filter */ 185 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40); 186 if (status < 0) 187 return status; 188 189 msleep(5); 190 191 /* exit tuning */ 192 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00); 193 194 return status; 195 } 196 197 int cx231xx_afe_init_channels(struct cx231xx *dev) 198 { 199 int status = 0; 200 201 /* power up all 3 channels, clear pd_buffer */ 202 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00); 203 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00); 204 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00); 205 206 /* Enable quantizer calibration */ 207 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02); 208 209 /* channel initialize, force modulator (fb) reset */ 210 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17); 211 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17); 212 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17); 213 214 /* start quantilizer calibration */ 215 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10); 216 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10); 217 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10); 218 msleep(5); 219 220 /* exit modulator (fb) reset */ 221 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07); 222 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07); 223 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07); 224 225 /* enable the pre_clamp in each channel for single-ended input */ 226 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0); 227 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0); 228 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0); 229 230 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 231 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 232 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 233 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 234 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 235 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8, 236 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 237 238 /* dynamic element matching off */ 239 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03); 240 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03); 241 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03); 242 243 return status; 244 } 245 246 int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev) 247 { 248 u8 c_value = 0; 249 int status = 0; 250 251 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value); 252 c_value &= (~(0x50)); 253 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value); 254 255 return status; 256 } 257 258 /* 259 The Analog Front End in Cx231xx has 3 channels. These 260 channels are used to share between different inputs 261 like tuner, s-video and composite inputs. 262 263 channel 1 ----- pin 1 to pin4(in reg is 1-4) 264 channel 2 ----- pin 5 to pin8(in reg is 5-8) 265 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 266 */ 267 int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux) 268 { 269 u8 ch1_setting = (u8) input_mux; 270 u8 ch2_setting = (u8) (input_mux >> 8); 271 u8 ch3_setting = (u8) (input_mux >> 16); 272 int status = 0; 273 u8 value = 0; 274 275 if (ch1_setting != 0) { 276 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); 277 value &= ~INPUT_SEL_MASK; 278 value |= (ch1_setting - 1) << 4; 279 value &= 0xff; 280 status = afe_write_byte(dev, ADC_INPUT_CH1, value); 281 } 282 283 if (ch2_setting != 0) { 284 status = afe_read_byte(dev, ADC_INPUT_CH2, &value); 285 value &= ~INPUT_SEL_MASK; 286 value |= (ch2_setting - 1) << 4; 287 value &= 0xff; 288 status = afe_write_byte(dev, ADC_INPUT_CH2, value); 289 } 290 291 /* For ch3_setting, the value to put in the register is 292 7 less than the input number */ 293 if (ch3_setting != 0) { 294 status = afe_read_byte(dev, ADC_INPUT_CH3, &value); 295 value &= ~INPUT_SEL_MASK; 296 value |= (ch3_setting - 1) << 4; 297 value &= 0xff; 298 status = afe_write_byte(dev, ADC_INPUT_CH3, value); 299 } 300 301 return status; 302 } 303 304 int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 305 { 306 int status = 0; 307 308 /* 309 * FIXME: We need to implement the AFE code for LOW IF and for HI IF. 310 * Currently, only baseband works. 311 */ 312 313 switch (mode) { 314 case AFE_MODE_LOW_IF: 315 cx231xx_Setup_AFE_for_LowIF(dev); 316 break; 317 case AFE_MODE_BASEBAND: 318 status = cx231xx_afe_setup_AFE_for_baseband(dev); 319 break; 320 case AFE_MODE_EU_HI_IF: 321 /* SetupAFEforEuHiIF(); */ 322 break; 323 case AFE_MODE_US_HI_IF: 324 /* SetupAFEforUsHiIF(); */ 325 break; 326 case AFE_MODE_JAPAN_HI_IF: 327 /* SetupAFEforJapanHiIF(); */ 328 break; 329 } 330 331 if ((mode != dev->afe_mode) && 332 (dev->video_input == CX231XX_VMUX_TELEVISION)) 333 status = cx231xx_afe_adjust_ref_count(dev, 334 CX231XX_VMUX_TELEVISION); 335 336 dev->afe_mode = mode; 337 338 return status; 339 } 340 341 int cx231xx_afe_update_power_control(struct cx231xx *dev, 342 enum AV_MODE avmode) 343 { 344 u8 afe_power_status = 0; 345 int status = 0; 346 347 switch (dev->model) { 348 case CX231XX_BOARD_CNXT_CARRAERA: 349 case CX231XX_BOARD_CNXT_RDE_250: 350 case CX231XX_BOARD_CNXT_SHELBY: 351 case CX231XX_BOARD_CNXT_RDU_250: 352 case CX231XX_BOARD_CNXT_RDE_253S: 353 case CX231XX_BOARD_CNXT_RDU_253S: 354 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 355 case CX231XX_BOARD_HAUPPAUGE_EXETER: 356 case CX231XX_BOARD_HAUPPAUGE_USBLIVE2: 357 case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID: 358 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 359 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 360 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 361 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 362 FLD_PWRDN_ENABLE_PLL)) { 363 status = afe_write_byte(dev, SUP_BLK_PWRDN, 364 FLD_PWRDN_TUNING_BIAS | 365 FLD_PWRDN_ENABLE_PLL); 366 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 367 &afe_power_status); 368 if (status < 0) 369 break; 370 } 371 372 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 373 0x00); 374 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 375 0x00); 376 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 377 0x00); 378 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 379 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 380 0x70); 381 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 382 0x70); 383 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 384 0x70); 385 386 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 387 &afe_power_status); 388 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 389 FLD_PWRDN_PD_BIAS | 390 FLD_PWRDN_PD_TUNECK; 391 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 392 afe_power_status); 393 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 394 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 395 FLD_PWRDN_ENABLE_PLL)) { 396 status = afe_write_byte(dev, SUP_BLK_PWRDN, 397 FLD_PWRDN_TUNING_BIAS | 398 FLD_PWRDN_ENABLE_PLL); 399 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 400 &afe_power_status); 401 if (status < 0) 402 break; 403 } 404 405 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 406 0x00); 407 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 408 0x00); 409 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 410 0x00); 411 } else { 412 cx231xx_info("Invalid AV mode input\n"); 413 status = -1; 414 } 415 break; 416 default: 417 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 418 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 419 FLD_PWRDN_ENABLE_PLL)) { 420 status = afe_write_byte(dev, SUP_BLK_PWRDN, 421 FLD_PWRDN_TUNING_BIAS | 422 FLD_PWRDN_ENABLE_PLL); 423 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 424 &afe_power_status); 425 if (status < 0) 426 break; 427 } 428 429 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 430 0x40); 431 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 432 0x40); 433 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 434 0x00); 435 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 436 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 437 0x70); 438 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 439 0x70); 440 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 441 0x70); 442 443 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 444 &afe_power_status); 445 afe_power_status |= FLD_PWRDN_PD_BANDGAP | 446 FLD_PWRDN_PD_BIAS | 447 FLD_PWRDN_PD_TUNECK; 448 status |= afe_write_byte(dev, SUP_BLK_PWRDN, 449 afe_power_status); 450 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 451 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS | 452 FLD_PWRDN_ENABLE_PLL)) { 453 status = afe_write_byte(dev, SUP_BLK_PWRDN, 454 FLD_PWRDN_TUNING_BIAS | 455 FLD_PWRDN_ENABLE_PLL); 456 status |= afe_read_byte(dev, SUP_BLK_PWRDN, 457 &afe_power_status); 458 if (status < 0) 459 break; 460 } 461 462 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 463 0x00); 464 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 465 0x00); 466 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 467 0x40); 468 } else { 469 cx231xx_info("Invalid AV mode input\n"); 470 status = -1; 471 } 472 } /* switch */ 473 474 return status; 475 } 476 477 int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input) 478 { 479 u8 input_mode = 0; 480 u8 ntf_mode = 0; 481 int status = 0; 482 483 dev->video_input = video_input; 484 485 if (video_input == CX231XX_VMUX_TELEVISION) { 486 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode); 487 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 488 &ntf_mode); 489 } else { 490 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode); 491 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 492 &ntf_mode); 493 } 494 495 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 496 497 switch (input_mode) { 498 case SINGLE_ENDED: 499 dev->afe_ref_count = 0x23C; 500 break; 501 case LOW_IF: 502 dev->afe_ref_count = 0x24C; 503 break; 504 case EU_IF: 505 dev->afe_ref_count = 0x258; 506 break; 507 case US_IF: 508 dev->afe_ref_count = 0x260; 509 break; 510 default: 511 break; 512 } 513 514 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count); 515 516 return status; 517 } 518 519 /****************************************************************************** 520 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 521 ******************************************************************************/ 522 static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data) 523 { 524 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 525 saddr, 2, data, 1); 526 } 527 528 static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data) 529 { 530 int status; 531 u32 temp = 0; 532 533 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 534 saddr, 2, &temp, 1); 535 *data = (u8) temp; 536 return status; 537 } 538 539 static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data) 540 { 541 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS, 542 saddr, 2, data, 4); 543 } 544 545 static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data) 546 { 547 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS, 548 saddr, 2, data, 4); 549 } 550 int cx231xx_check_fw(struct cx231xx *dev) 551 { 552 u8 temp = 0; 553 int status = 0; 554 status = vid_blk_read_byte(dev, DL_CTL_ADDRESS_LOW, &temp); 555 if (status < 0) 556 return status; 557 else 558 return temp; 559 560 } 561 562 int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 563 { 564 int status = 0; 565 566 switch (INPUT(input)->type) { 567 case CX231XX_VMUX_COMPOSITE1: 568 case CX231XX_VMUX_SVIDEO: 569 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 570 (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) { 571 /* External AV */ 572 status = cx231xx_set_power_mode(dev, 573 POLARIS_AVMODE_ENXTERNAL_AV); 574 if (status < 0) { 575 cx231xx_errdev("%s: set_power_mode : Failed to" 576 " set Power - errCode [%d]!\n", 577 __func__, status); 578 return status; 579 } 580 } 581 status = cx231xx_set_decoder_video_input(dev, 582 INPUT(input)->type, 583 INPUT(input)->vmux); 584 break; 585 case CX231XX_VMUX_TELEVISION: 586 case CX231XX_VMUX_CABLE: 587 if ((dev->current_pcb_config.type == USB_BUS_POWER) && 588 (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) { 589 /* Tuner */ 590 status = cx231xx_set_power_mode(dev, 591 POLARIS_AVMODE_ANALOGT_TV); 592 if (status < 0) { 593 cx231xx_errdev("%s: set_power_mode:Failed" 594 " to set Power - errCode [%d]!\n", 595 __func__, status); 596 return status; 597 } 598 } 599 if (dev->tuner_type == TUNER_NXP_TDA18271) 600 status = cx231xx_set_decoder_video_input(dev, 601 CX231XX_VMUX_TELEVISION, 602 INPUT(input)->vmux); 603 else 604 status = cx231xx_set_decoder_video_input(dev, 605 CX231XX_VMUX_COMPOSITE1, 606 INPUT(input)->vmux); 607 608 break; 609 default: 610 cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n", 611 __func__, INPUT(input)->type); 612 break; 613 } 614 615 /* save the selection */ 616 dev->video_input = input; 617 618 return status; 619 } 620 621 int cx231xx_set_decoder_video_input(struct cx231xx *dev, 622 u8 pin_type, u8 input) 623 { 624 int status = 0; 625 u32 value = 0; 626 627 if (pin_type != dev->video_input) { 628 status = cx231xx_afe_adjust_ref_count(dev, pin_type); 629 if (status < 0) { 630 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 631 "AFE input mux - errCode [%d]!\n", 632 __func__, status); 633 return status; 634 } 635 } 636 637 /* call afe block to set video inputs */ 638 status = cx231xx_afe_set_input_mux(dev, input); 639 if (status < 0) { 640 cx231xx_errdev("%s: set_input_mux :Failed to set" 641 " AFE input mux - errCode [%d]!\n", 642 __func__, status); 643 return status; 644 } 645 646 switch (pin_type) { 647 case CX231XX_VMUX_COMPOSITE1: 648 status = vid_blk_read_word(dev, AFE_CTRL, &value); 649 value |= (0 << 13) | (1 << 4); 650 value &= ~(1 << 5); 651 652 /* set [24:23] [22:15] to 0 */ 653 value &= (~(0x1ff8000)); 654 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 655 value |= 0x1000000; 656 status = vid_blk_write_word(dev, AFE_CTRL, value); 657 658 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 659 value |= (1 << 7); 660 status = vid_blk_write_word(dev, OUT_CTRL1, value); 661 662 /* Set output mode */ 663 status = cx231xx_read_modify_write_i2c_dword(dev, 664 VID_BLK_I2C_ADDRESS, 665 OUT_CTRL1, 666 FLD_OUT_MODE, 667 dev->board.output_mode); 668 669 /* Tell DIF object to go to baseband mode */ 670 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 671 if (status < 0) { 672 cx231xx_errdev("%s: cx231xx_dif set to By pass" 673 " mode- errCode [%d]!\n", 674 __func__, status); 675 return status; 676 } 677 678 /* Read the DFE_CTRL1 register */ 679 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 680 681 /* enable the VBI_GATE_EN */ 682 value |= FLD_VBI_GATE_EN; 683 684 /* Enable the auto-VGA enable */ 685 value |= FLD_VGA_AUTO_EN; 686 687 /* Write it back */ 688 status = vid_blk_write_word(dev, DFE_CTRL1, value); 689 690 /* Disable auto config of registers */ 691 status = cx231xx_read_modify_write_i2c_dword(dev, 692 VID_BLK_I2C_ADDRESS, 693 MODE_CTRL, FLD_ACFG_DIS, 694 cx231xx_set_field(FLD_ACFG_DIS, 1)); 695 696 /* Set CVBS input mode */ 697 status = cx231xx_read_modify_write_i2c_dword(dev, 698 VID_BLK_I2C_ADDRESS, 699 MODE_CTRL, FLD_INPUT_MODE, 700 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 701 break; 702 case CX231XX_VMUX_SVIDEO: 703 /* Disable the use of DIF */ 704 705 status = vid_blk_read_word(dev, AFE_CTRL, &value); 706 707 /* set [24:23] [22:15] to 0 */ 708 value &= (~(0x1ff8000)); 709 /* set FUNC_MODE[24:23] = 2 710 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 711 value |= 0x1000010; 712 status = vid_blk_write_word(dev, AFE_CTRL, value); 713 714 /* Tell DIF object to go to baseband mode */ 715 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 716 if (status < 0) { 717 cx231xx_errdev("%s: cx231xx_dif set to By pass" 718 " mode- errCode [%d]!\n", 719 __func__, status); 720 return status; 721 } 722 723 /* Read the DFE_CTRL1 register */ 724 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 725 726 /* enable the VBI_GATE_EN */ 727 value |= FLD_VBI_GATE_EN; 728 729 /* Enable the auto-VGA enable */ 730 value |= FLD_VGA_AUTO_EN; 731 732 /* Write it back */ 733 status = vid_blk_write_word(dev, DFE_CTRL1, value); 734 735 /* Disable auto config of registers */ 736 status = cx231xx_read_modify_write_i2c_dword(dev, 737 VID_BLK_I2C_ADDRESS, 738 MODE_CTRL, FLD_ACFG_DIS, 739 cx231xx_set_field(FLD_ACFG_DIS, 1)); 740 741 /* Set YC input mode */ 742 status = cx231xx_read_modify_write_i2c_dword(dev, 743 VID_BLK_I2C_ADDRESS, 744 MODE_CTRL, 745 FLD_INPUT_MODE, 746 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 747 748 /* Chroma to ADC2 */ 749 status = vid_blk_read_word(dev, AFE_CTRL, &value); 750 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 751 752 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 753 This sets them to use video 754 rather than audio. Only one of the two will be in use. */ 755 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 756 757 status = vid_blk_write_word(dev, AFE_CTRL, value); 758 759 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND); 760 break; 761 case CX231XX_VMUX_TELEVISION: 762 case CX231XX_VMUX_CABLE: 763 default: 764 /* TODO: Test if this is also needed for xc2028/xc3028 */ 765 if (dev->board.tuner_type == TUNER_XC5000) { 766 /* Disable the use of DIF */ 767 768 status = vid_blk_read_word(dev, AFE_CTRL, &value); 769 value |= (0 << 13) | (1 << 4); 770 value &= ~(1 << 5); 771 772 /* set [24:23] [22:15] to 0 */ 773 value &= (~(0x1FF8000)); 774 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 775 value |= 0x1000000; 776 status = vid_blk_write_word(dev, AFE_CTRL, value); 777 778 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 779 value |= (1 << 7); 780 status = vid_blk_write_word(dev, OUT_CTRL1, value); 781 782 /* Set output mode */ 783 status = cx231xx_read_modify_write_i2c_dword(dev, 784 VID_BLK_I2C_ADDRESS, 785 OUT_CTRL1, FLD_OUT_MODE, 786 dev->board.output_mode); 787 788 /* Tell DIF object to go to baseband mode */ 789 status = cx231xx_dif_set_standard(dev, 790 DIF_USE_BASEBAND); 791 if (status < 0) { 792 cx231xx_errdev("%s: cx231xx_dif set to By pass" 793 " mode- errCode [%d]!\n", 794 __func__, status); 795 return status; 796 } 797 798 /* Read the DFE_CTRL1 register */ 799 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 800 801 /* enable the VBI_GATE_EN */ 802 value |= FLD_VBI_GATE_EN; 803 804 /* Enable the auto-VGA enable */ 805 value |= FLD_VGA_AUTO_EN; 806 807 /* Write it back */ 808 status = vid_blk_write_word(dev, DFE_CTRL1, value); 809 810 /* Disable auto config of registers */ 811 status = cx231xx_read_modify_write_i2c_dword(dev, 812 VID_BLK_I2C_ADDRESS, 813 MODE_CTRL, FLD_ACFG_DIS, 814 cx231xx_set_field(FLD_ACFG_DIS, 1)); 815 816 /* Set CVBS input mode */ 817 status = cx231xx_read_modify_write_i2c_dword(dev, 818 VID_BLK_I2C_ADDRESS, 819 MODE_CTRL, FLD_INPUT_MODE, 820 cx231xx_set_field(FLD_INPUT_MODE, 821 INPUT_MODE_CVBS_0)); 822 } else { 823 /* Enable the DIF for the tuner */ 824 825 /* Reinitialize the DIF */ 826 status = cx231xx_dif_set_standard(dev, dev->norm); 827 if (status < 0) { 828 cx231xx_errdev("%s: cx231xx_dif set to By pass" 829 " mode- errCode [%d]!\n", 830 __func__, status); 831 return status; 832 } 833 834 /* Make sure bypass is cleared */ 835 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value); 836 837 /* Clear the bypass bit */ 838 value &= ~FLD_DIF_DIF_BYPASS; 839 840 /* Enable the use of the DIF block */ 841 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value); 842 843 /* Read the DFE_CTRL1 register */ 844 status = vid_blk_read_word(dev, DFE_CTRL1, &value); 845 846 /* Disable the VBI_GATE_EN */ 847 value &= ~FLD_VBI_GATE_EN; 848 849 /* Enable the auto-VGA enable, AGC, and 850 set the skip count to 2 */ 851 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 852 853 /* Write it back */ 854 status = vid_blk_write_word(dev, DFE_CTRL1, value); 855 856 /* Wait until AGC locks up */ 857 msleep(1); 858 859 /* Disable the auto-VGA enable AGC */ 860 value &= ~(FLD_VGA_AUTO_EN); 861 862 /* Write it back */ 863 status = vid_blk_write_word(dev, DFE_CTRL1, value); 864 865 /* Enable Polaris B0 AGC output */ 866 status = vid_blk_read_word(dev, PIN_CTRL, &value); 867 value |= (FLD_OEF_AGC_RF) | 868 (FLD_OEF_AGC_IFVGA) | 869 (FLD_OEF_AGC_IF); 870 status = vid_blk_write_word(dev, PIN_CTRL, value); 871 872 /* Set output mode */ 873 status = cx231xx_read_modify_write_i2c_dword(dev, 874 VID_BLK_I2C_ADDRESS, 875 OUT_CTRL1, FLD_OUT_MODE, 876 dev->board.output_mode); 877 878 /* Disable auto config of registers */ 879 status = cx231xx_read_modify_write_i2c_dword(dev, 880 VID_BLK_I2C_ADDRESS, 881 MODE_CTRL, FLD_ACFG_DIS, 882 cx231xx_set_field(FLD_ACFG_DIS, 1)); 883 884 /* Set CVBS input mode */ 885 status = cx231xx_read_modify_write_i2c_dword(dev, 886 VID_BLK_I2C_ADDRESS, 887 MODE_CTRL, FLD_INPUT_MODE, 888 cx231xx_set_field(FLD_INPUT_MODE, 889 INPUT_MODE_CVBS_0)); 890 891 /* Set some bits in AFE_CTRL so that channel 2 or 3 892 * is ready to receive audio */ 893 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 894 /* Clear droop comp (bit 19-20) */ 895 /* Set VGA_SEL (for audio control) (bit 7-8) */ 896 status = vid_blk_read_word(dev, AFE_CTRL, &value); 897 898 /*Set Func mode:01-DIF 10-baseband 11-YUV*/ 899 value &= (~(FLD_FUNC_MODE)); 900 value |= 0x800000; 901 902 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 903 904 status = vid_blk_write_word(dev, AFE_CTRL, value); 905 906 if (dev->tuner_type == TUNER_NXP_TDA18271) { 907 status = vid_blk_read_word(dev, PIN_CTRL, 908 &value); 909 status = vid_blk_write_word(dev, PIN_CTRL, 910 (value & 0xFFFFFFEF)); 911 } 912 913 break; 914 915 } 916 break; 917 } 918 919 /* Set raw VBI mode */ 920 status = cx231xx_read_modify_write_i2c_dword(dev, 921 VID_BLK_I2C_ADDRESS, 922 OUT_CTRL1, FLD_VBIHACTRAW_EN, 923 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 924 925 status = vid_blk_read_word(dev, OUT_CTRL1, &value); 926 if (value & 0x02) { 927 value |= (1 << 19); 928 status = vid_blk_write_word(dev, OUT_CTRL1, value); 929 } 930 931 return status; 932 } 933 934 void cx231xx_enable656(struct cx231xx *dev) 935 { 936 u8 temp = 0; 937 /*enable TS1 data[0:7] as output to export 656*/ 938 939 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0xFF); 940 941 /*enable TS1 clock as output to export 656*/ 942 943 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 944 temp = temp|0x04; 945 946 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 947 } 948 EXPORT_SYMBOL_GPL(cx231xx_enable656); 949 950 void cx231xx_disable656(struct cx231xx *dev) 951 { 952 u8 temp = 0; 953 954 vid_blk_write_byte(dev, TS1_PIN_CTL0, 0x00); 955 956 vid_blk_read_byte(dev, TS1_PIN_CTL1, &temp); 957 temp = temp&0xFB; 958 959 vid_blk_write_byte(dev, TS1_PIN_CTL1, temp); 960 } 961 EXPORT_SYMBOL_GPL(cx231xx_disable656); 962 963 /* 964 * Handle any video-mode specific overrides that are different 965 * on a per video standards basis after touching the MODE_CTRL 966 * register which resets many values for autodetect 967 */ 968 int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev) 969 { 970 int status = 0; 971 972 cx231xx_info("do_mode_ctrl_overrides : 0x%x\n", 973 (unsigned int)dev->norm); 974 975 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 976 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280); 977 978 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 979 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 980 981 /* Move the close caption lines out of active video, 982 adjust the active video start point */ 983 status = cx231xx_read_modify_write_i2c_dword(dev, 984 VID_BLK_I2C_ADDRESS, 985 VERT_TIM_CTRL, 986 FLD_VBLANK_CNT, 0x18); 987 status = cx231xx_read_modify_write_i2c_dword(dev, 988 VID_BLK_I2C_ADDRESS, 989 VERT_TIM_CTRL, 990 FLD_VACTIVE_CNT, 991 0x1E7000); 992 status = cx231xx_read_modify_write_i2c_dword(dev, 993 VID_BLK_I2C_ADDRESS, 994 VERT_TIM_CTRL, 995 FLD_V656BLANK_CNT, 996 0x1C000000); 997 998 status = cx231xx_read_modify_write_i2c_dword(dev, 999 VID_BLK_I2C_ADDRESS, 1000 HORIZ_TIM_CTRL, 1001 FLD_HBLANK_CNT, 1002 cx231xx_set_field 1003 (FLD_HBLANK_CNT, 0x79)); 1004 1005 } else if (dev->norm & V4L2_STD_SECAM) { 1006 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 1007 status = cx231xx_read_modify_write_i2c_dword(dev, 1008 VID_BLK_I2C_ADDRESS, 1009 VERT_TIM_CTRL, 1010 FLD_VBLANK_CNT, 0x20); 1011 status = cx231xx_read_modify_write_i2c_dword(dev, 1012 VID_BLK_I2C_ADDRESS, 1013 VERT_TIM_CTRL, 1014 FLD_VACTIVE_CNT, 1015 cx231xx_set_field 1016 (FLD_VACTIVE_CNT, 1017 0x244)); 1018 status = cx231xx_read_modify_write_i2c_dword(dev, 1019 VID_BLK_I2C_ADDRESS, 1020 VERT_TIM_CTRL, 1021 FLD_V656BLANK_CNT, 1022 cx231xx_set_field 1023 (FLD_V656BLANK_CNT, 1024 0x24)); 1025 /* Adjust the active video horizontal start point */ 1026 status = cx231xx_read_modify_write_i2c_dword(dev, 1027 VID_BLK_I2C_ADDRESS, 1028 HORIZ_TIM_CTRL, 1029 FLD_HBLANK_CNT, 1030 cx231xx_set_field 1031 (FLD_HBLANK_CNT, 0x85)); 1032 } else { 1033 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 1034 status = cx231xx_read_modify_write_i2c_dword(dev, 1035 VID_BLK_I2C_ADDRESS, 1036 VERT_TIM_CTRL, 1037 FLD_VBLANK_CNT, 0x20); 1038 status = cx231xx_read_modify_write_i2c_dword(dev, 1039 VID_BLK_I2C_ADDRESS, 1040 VERT_TIM_CTRL, 1041 FLD_VACTIVE_CNT, 1042 cx231xx_set_field 1043 (FLD_VACTIVE_CNT, 1044 0x244)); 1045 status = cx231xx_read_modify_write_i2c_dword(dev, 1046 VID_BLK_I2C_ADDRESS, 1047 VERT_TIM_CTRL, 1048 FLD_V656BLANK_CNT, 1049 cx231xx_set_field 1050 (FLD_V656BLANK_CNT, 1051 0x24)); 1052 /* Adjust the active video horizontal start point */ 1053 status = cx231xx_read_modify_write_i2c_dword(dev, 1054 VID_BLK_I2C_ADDRESS, 1055 HORIZ_TIM_CTRL, 1056 FLD_HBLANK_CNT, 1057 cx231xx_set_field 1058 (FLD_HBLANK_CNT, 0x85)); 1059 1060 } 1061 1062 return status; 1063 } 1064 1065 int cx231xx_unmute_audio(struct cx231xx *dev) 1066 { 1067 return vid_blk_write_byte(dev, PATH1_VOL_CTL, 0x24); 1068 } 1069 EXPORT_SYMBOL_GPL(cx231xx_unmute_audio); 1070 1071 static int stopAudioFirmware(struct cx231xx *dev) 1072 { 1073 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x03); 1074 } 1075 1076 static int restartAudioFirmware(struct cx231xx *dev) 1077 { 1078 return vid_blk_write_byte(dev, DL_CTL_CONTROL, 0x13); 1079 } 1080 1081 int cx231xx_set_audio_input(struct cx231xx *dev, u8 input) 1082 { 1083 int status = 0; 1084 enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE; 1085 1086 switch (INPUT(input)->amux) { 1087 case CX231XX_AMUX_VIDEO: 1088 ainput = AUDIO_INPUT_TUNER_TV; 1089 break; 1090 case CX231XX_AMUX_LINE_IN: 1091 status = cx231xx_i2s_blk_set_audio_input(dev, input); 1092 ainput = AUDIO_INPUT_LINE; 1093 break; 1094 default: 1095 break; 1096 } 1097 1098 status = cx231xx_set_audio_decoder_input(dev, ainput); 1099 1100 return status; 1101 } 1102 1103 int cx231xx_set_audio_decoder_input(struct cx231xx *dev, 1104 enum AUDIO_INPUT audio_input) 1105 { 1106 u32 dwval; 1107 int status; 1108 u8 gen_ctrl; 1109 u32 value = 0; 1110 1111 /* Put it in soft reset */ 1112 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1113 gen_ctrl |= 1; 1114 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1115 1116 switch (audio_input) { 1117 case AUDIO_INPUT_LINE: 1118 /* setup AUD_IO control from Merlin paralle output */ 1119 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 1120 AUD_CHAN_SRC_PARALLEL); 1121 status = vid_blk_write_word(dev, AUD_IO_CTRL, value); 1122 1123 /* setup input to Merlin, SRC2 connect to AC97 1124 bypass upsample-by-2, slave mode, sony mode, left justify 1125 adr 091c, dat 01000000 */ 1126 status = vid_blk_read_word(dev, AC97_CTL, &dwval); 1127 1128 status = vid_blk_write_word(dev, AC97_CTL, 1129 (dwval | FLD_AC97_UP2X_BYPASS)); 1130 1131 /* select the parallel1 and SRC3 */ 1132 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1133 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 1134 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 1135 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0)); 1136 1137 /* unmute all, AC97 in, independence mode 1138 adr 08d0, data 0x00063073 */ 1139 status = vid_blk_write_word(dev, DL_CTL, 0x3000001); 1140 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073); 1141 1142 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 1143 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval); 1144 status = vid_blk_write_word(dev, PATH1_VOL_CTL, 1145 (dwval | FLD_PATH1_AVC_THRESHOLD)); 1146 1147 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 1148 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval); 1149 status = vid_blk_write_word(dev, PATH1_SC_CTL, 1150 (dwval | FLD_PATH1_SC_THRESHOLD)); 1151 break; 1152 1153 case AUDIO_INPUT_TUNER_TV: 1154 default: 1155 status = stopAudioFirmware(dev); 1156 /* Setup SRC sources and clocks */ 1157 status = vid_blk_write_word(dev, BAND_OUT_SEL, 1158 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 1159 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 1160 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 1161 cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02) | 1162 cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02) | 1163 cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03) | 1164 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00) | 1165 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00) | 1166 cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) | 1167 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1168 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1169 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1170 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01)); 1171 1172 /* Setup the AUD_IO control */ 1173 status = vid_blk_write_word(dev, AUD_IO_CTRL, 1174 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1175 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1176 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1177 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1178 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03)); 1179 1180 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870); 1181 1182 /* setAudioStandard(_audio_standard); */ 1183 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870); 1184 1185 status = restartAudioFirmware(dev); 1186 1187 switch (dev->board.tuner_type) { 1188 case TUNER_XC5000: 1189 /* SIF passthrough at 28.6363 MHz sample rate */ 1190 status = cx231xx_read_modify_write_i2c_dword(dev, 1191 VID_BLK_I2C_ADDRESS, 1192 CHIP_CTRL, 1193 FLD_SIF_EN, 1194 cx231xx_set_field(FLD_SIF_EN, 1)); 1195 break; 1196 case TUNER_NXP_TDA18271: 1197 /* Normal mode: SIF passthrough at 14.32 MHz */ 1198 status = cx231xx_read_modify_write_i2c_dword(dev, 1199 VID_BLK_I2C_ADDRESS, 1200 CHIP_CTRL, 1201 FLD_SIF_EN, 1202 cx231xx_set_field(FLD_SIF_EN, 0)); 1203 break; 1204 default: 1205 /* This is just a casual suggestion to people adding 1206 new boards in case they use a tuner type we don't 1207 currently know about */ 1208 printk(KERN_INFO "Unknown tuner type configuring SIF"); 1209 break; 1210 } 1211 break; 1212 1213 case AUDIO_INPUT_TUNER_FM: 1214 /* use SIF for FM radio 1215 setupFM(); 1216 setAudioStandard(_audio_standard); 1217 */ 1218 break; 1219 1220 case AUDIO_INPUT_MUTE: 1221 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012); 1222 break; 1223 } 1224 1225 /* Take it out of soft reset */ 1226 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl); 1227 gen_ctrl &= ~1; 1228 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl); 1229 1230 return status; 1231 } 1232 1233 /****************************************************************************** 1234 * C H I P Specific C O N T R O L functions * 1235 ******************************************************************************/ 1236 int cx231xx_init_ctrl_pin_status(struct cx231xx *dev) 1237 { 1238 u32 value; 1239 int status = 0; 1240 1241 status = vid_blk_read_word(dev, PIN_CTRL, &value); 1242 value |= (~dev->board.ctl_pin_status_mask); 1243 status = vid_blk_write_word(dev, PIN_CTRL, value); 1244 1245 return status; 1246 } 1247 1248 int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev, 1249 u8 analog_or_digital) 1250 { 1251 int status = 0; 1252 1253 /* first set the direction to output */ 1254 status = cx231xx_set_gpio_direction(dev, 1255 dev->board. 1256 agc_analog_digital_select_gpio, 1); 1257 1258 /* 0 - demod ; 1 - Analog mode */ 1259 status = cx231xx_set_gpio_value(dev, 1260 dev->board.agc_analog_digital_select_gpio, 1261 analog_or_digital); 1262 1263 return status; 1264 } 1265 1266 int cx231xx_enable_i2c_port_3(struct cx231xx *dev, bool is_port_3) 1267 { 1268 u8 value[4] = { 0, 0, 0, 0 }; 1269 int status = 0; 1270 bool current_is_port_3; 1271 1272 if (dev->board.dont_use_port_3) 1273 is_port_3 = false; 1274 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, 1275 PWR_CTL_EN, value, 4); 1276 if (status < 0) 1277 return status; 1278 1279 current_is_port_3 = value[0] & I2C_DEMOD_EN ? true : false; 1280 1281 /* Just return, if already using the right port */ 1282 if (current_is_port_3 == is_port_3) 1283 return 0; 1284 1285 if (is_port_3) 1286 value[0] |= I2C_DEMOD_EN; 1287 else 1288 value[0] &= ~I2C_DEMOD_EN; 1289 1290 cx231xx_info("Changing the i2c master port to %d\n", 1291 is_port_3 ? 3 : 1); 1292 1293 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1294 PWR_CTL_EN, value, 4); 1295 1296 return status; 1297 1298 } 1299 EXPORT_SYMBOL_GPL(cx231xx_enable_i2c_port_3); 1300 1301 void update_HH_register_after_set_DIF(struct cx231xx *dev) 1302 { 1303 /* 1304 u8 status = 0; 1305 u32 value = 0; 1306 1307 vid_blk_write_word(dev, PIN_CTRL, 0xA0FFF82F); 1308 vid_blk_write_word(dev, DIF_MISC_CTRL, 0x0A203F11); 1309 vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0x1BEFBF06); 1310 1311 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1312 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1313 status = vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1314 */ 1315 } 1316 1317 void cx231xx_dump_HH_reg(struct cx231xx *dev) 1318 { 1319 u32 value = 0; 1320 u16 i = 0; 1321 1322 value = 0x45005390; 1323 vid_blk_write_word(dev, 0x104, value); 1324 1325 for (i = 0x100; i < 0x140; i++) { 1326 vid_blk_read_word(dev, i, &value); 1327 cx231xx_info("reg0x%x=0x%x\n", i, value); 1328 i = i+3; 1329 } 1330 1331 for (i = 0x300; i < 0x400; i++) { 1332 vid_blk_read_word(dev, i, &value); 1333 cx231xx_info("reg0x%x=0x%x\n", i, value); 1334 i = i+3; 1335 } 1336 1337 for (i = 0x400; i < 0x440; i++) { 1338 vid_blk_read_word(dev, i, &value); 1339 cx231xx_info("reg0x%x=0x%x\n", i, value); 1340 i = i+3; 1341 } 1342 1343 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1344 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1345 vid_blk_write_word(dev, AFE_CTRL_C2HH_SRC_CTRL, 0x4485D390); 1346 vid_blk_read_word(dev, AFE_CTRL_C2HH_SRC_CTRL, &value); 1347 cx231xx_info("AFE_CTRL_C2HH_SRC_CTRL=0x%x\n", value); 1348 } 1349 1350 void cx231xx_dump_SC_reg(struct cx231xx *dev) 1351 { 1352 u8 value[4] = { 0, 0, 0, 0 }; 1353 cx231xx_info("cx231xx_dump_SC_reg!\n"); 1354 1355 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, 1356 value, 4); 1357 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", BOARD_CFG_STAT, value[0], 1358 value[1], value[2], value[3]); 1359 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS_MODE_REG, 1360 value, 4); 1361 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS_MODE_REG, value[0], 1362 value[1], value[2], value[3]); 1363 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_CFG_REG, 1364 value, 4); 1365 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_CFG_REG, value[0], 1366 value[1], value[2], value[3]); 1367 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS1_LENGTH_REG, 1368 value, 4); 1369 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS1_LENGTH_REG, value[0], 1370 value[1], value[2], value[3]); 1371 1372 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_CFG_REG, 1373 value, 4); 1374 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_CFG_REG, value[0], 1375 value[1], value[2], value[3]); 1376 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, TS2_LENGTH_REG, 1377 value, 4); 1378 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", TS2_LENGTH_REG, value[0], 1379 value[1], value[2], value[3]); 1380 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 1381 value, 4); 1382 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", EP_MODE_SET, value[0], 1383 value[1], value[2], value[3]); 1384 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN1, 1385 value, 4); 1386 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN1, value[0], 1387 value[1], value[2], value[3]); 1388 1389 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN2, 1390 value, 4); 1391 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN2, value[0], 1392 value[1], value[2], value[3]); 1393 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_PTN3, 1394 value, 4); 1395 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_PTN3, value[0], 1396 value[1], value[2], value[3]); 1397 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK0, 1398 value, 4); 1399 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK0, value[0], 1400 value[1], value[2], value[3]); 1401 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK1, 1402 value, 4); 1403 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK1, value[0], 1404 value[1], value[2], value[3]); 1405 1406 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_PWR_MASK2, 1407 value, 4); 1408 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_PWR_MASK2, value[0], 1409 value[1], value[2], value[3]); 1410 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_GAIN, 1411 value, 4); 1412 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_GAIN, value[0], 1413 value[1], value[2], value[3]); 1414 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_CAR_REG, 1415 value, 4); 1416 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_CAR_REG, value[0], 1417 value[1], value[2], value[3]); 1418 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG1, 1419 value, 4); 1420 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG1, value[0], 1421 value[1], value[2], value[3]); 1422 1423 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, CIR_OT_CFG2, 1424 value, 4); 1425 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", CIR_OT_CFG2, value[0], 1426 value[1], value[2], value[3]); 1427 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 1428 value, 4); 1429 cx231xx_info("reg0x%x=0x%x 0x%x 0x%x 0x%x\n", PWR_CTL_EN, value[0], 1430 value[1], value[2], value[3]); 1431 1432 1433 } 1434 1435 void cx231xx_Setup_AFE_for_LowIF(struct cx231xx *dev) 1436 1437 { 1438 u8 value = 0; 1439 1440 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1441 value = (value & 0xFE)|0x01; 1442 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1443 1444 afe_read_byte(dev, ADC_STATUS2_CH3, &value); 1445 value = (value & 0xFE)|0x00; 1446 afe_write_byte(dev, ADC_STATUS2_CH3, value); 1447 1448 1449 /* 1450 config colibri to lo-if mode 1451 1452 FIXME: ntf_mode = 2'b00 by default. But set 0x1 would reduce 1453 the diff IF input by half, 1454 1455 for low-if agc defect 1456 */ 1457 1458 afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3, &value); 1459 value = (value & 0xFC)|0x00; 1460 afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, value); 1461 1462 afe_read_byte(dev, ADC_INPUT_CH3, &value); 1463 value = (value & 0xF9)|0x02; 1464 afe_write_byte(dev, ADC_INPUT_CH3, value); 1465 1466 afe_read_byte(dev, ADC_FB_FRCRST_CH3, &value); 1467 value = (value & 0xFB)|0x04; 1468 afe_write_byte(dev, ADC_FB_FRCRST_CH3, value); 1469 1470 afe_read_byte(dev, ADC_DCSERVO_DEM_CH3, &value); 1471 value = (value & 0xFC)|0x03; 1472 afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, value); 1473 1474 afe_read_byte(dev, ADC_CTRL_DAC1_CH3, &value); 1475 value = (value & 0xFB)|0x04; 1476 afe_write_byte(dev, ADC_CTRL_DAC1_CH3, value); 1477 1478 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1479 value = (value & 0xF8)|0x06; 1480 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1481 1482 afe_read_byte(dev, ADC_CTRL_DAC23_CH3, &value); 1483 value = (value & 0x8F)|0x40; 1484 afe_write_byte(dev, ADC_CTRL_DAC23_CH3, value); 1485 1486 afe_read_byte(dev, ADC_PWRDN_CLAMP_CH3, &value); 1487 value = (value & 0xDF)|0x20; 1488 afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, value); 1489 } 1490 1491 void cx231xx_set_Colibri_For_LowIF(struct cx231xx *dev, u32 if_freq, 1492 u8 spectral_invert, u32 mode) 1493 { 1494 u32 colibri_carrier_offset = 0; 1495 u32 func_mode = 0x01; /* Device has a DIF if this function is called */ 1496 u32 standard = 0; 1497 u8 value[4] = { 0, 0, 0, 0 }; 1498 1499 cx231xx_info("Enter cx231xx_set_Colibri_For_LowIF()\n"); 1500 value[0] = (u8) 0x6F; 1501 value[1] = (u8) 0x6F; 1502 value[2] = (u8) 0x6F; 1503 value[3] = (u8) 0x6F; 1504 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 1505 PWR_CTL_EN, value, 4); 1506 1507 /*Set colibri for low IF*/ 1508 cx231xx_afe_set_mode(dev, AFE_MODE_LOW_IF); 1509 1510 /* Set C2HH for low IF operation.*/ 1511 standard = dev->norm; 1512 cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1513 func_mode, standard); 1514 1515 /* Get colibri offsets.*/ 1516 colibri_carrier_offset = cx231xx_Get_Colibri_CarrierOffset(mode, 1517 standard); 1518 1519 cx231xx_info("colibri_carrier_offset=%d, standard=0x%x\n", 1520 colibri_carrier_offset, standard); 1521 1522 /* Set the band Pass filter for DIF*/ 1523 cx231xx_set_DIF_bandpass(dev, (if_freq+colibri_carrier_offset), 1524 spectral_invert, mode); 1525 } 1526 1527 u32 cx231xx_Get_Colibri_CarrierOffset(u32 mode, u32 standerd) 1528 { 1529 u32 colibri_carrier_offset = 0; 1530 1531 if (mode == TUNER_MODE_FM_RADIO) { 1532 colibri_carrier_offset = 1100000; 1533 } else if (standerd & (V4L2_STD_MN | V4L2_STD_NTSC_M_JP)) { 1534 colibri_carrier_offset = 4832000; /*4.83MHz */ 1535 } else if (standerd & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) { 1536 colibri_carrier_offset = 2700000; /*2.70MHz */ 1537 } else if (standerd & (V4L2_STD_PAL_D | V4L2_STD_PAL_I 1538 | V4L2_STD_SECAM)) { 1539 colibri_carrier_offset = 2100000; /*2.10MHz */ 1540 } 1541 1542 return colibri_carrier_offset; 1543 } 1544 1545 void cx231xx_set_DIF_bandpass(struct cx231xx *dev, u32 if_freq, 1546 u8 spectral_invert, u32 mode) 1547 { 1548 unsigned long pll_freq_word; 1549 u32 dif_misc_ctrl_value = 0; 1550 u64 pll_freq_u64 = 0; 1551 u32 i = 0; 1552 1553 cx231xx_info("if_freq=%d;spectral_invert=0x%x;mode=0x%x\n", 1554 if_freq, spectral_invert, mode); 1555 1556 1557 if (mode == TUNER_MODE_FM_RADIO) { 1558 pll_freq_word = 0x905A1CAC; 1559 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1560 1561 } else /*KSPROPERTY_TUNER_MODE_TV*/{ 1562 /* Calculate the PLL frequency word based on the adjusted if_freq*/ 1563 pll_freq_word = if_freq; 1564 pll_freq_u64 = (u64)pll_freq_word << 28L; 1565 do_div(pll_freq_u64, 50000000); 1566 pll_freq_word = (u32)pll_freq_u64; 1567 /*pll_freq_word = 0x3463497;*/ 1568 vid_blk_write_word(dev, DIF_PLL_FREQ_WORD, pll_freq_word); 1569 1570 if (spectral_invert) { 1571 if_freq -= 400000; 1572 /* Enable Spectral Invert*/ 1573 vid_blk_read_word(dev, DIF_MISC_CTRL, 1574 &dif_misc_ctrl_value); 1575 dif_misc_ctrl_value = dif_misc_ctrl_value | 0x00200000; 1576 vid_blk_write_word(dev, DIF_MISC_CTRL, 1577 dif_misc_ctrl_value); 1578 } else { 1579 if_freq += 400000; 1580 /* Disable Spectral Invert*/ 1581 vid_blk_read_word(dev, DIF_MISC_CTRL, 1582 &dif_misc_ctrl_value); 1583 dif_misc_ctrl_value = dif_misc_ctrl_value & 0xFFDFFFFF; 1584 vid_blk_write_word(dev, DIF_MISC_CTRL, 1585 dif_misc_ctrl_value); 1586 } 1587 1588 if_freq = (if_freq/100000)*100000; 1589 1590 if (if_freq < 3000000) 1591 if_freq = 3000000; 1592 1593 if (if_freq > 16000000) 1594 if_freq = 16000000; 1595 } 1596 1597 cx231xx_info("Enter IF=%zd\n", 1598 ARRAY_SIZE(Dif_set_array)); 1599 for (i = 0; i < ARRAY_SIZE(Dif_set_array); i++) { 1600 if (Dif_set_array[i].if_freq == if_freq) { 1601 vid_blk_write_word(dev, 1602 Dif_set_array[i].register_address, Dif_set_array[i].value); 1603 } 1604 } 1605 } 1606 1607 /****************************************************************************** 1608 * D I F - B L O C K C O N T R O L functions * 1609 ******************************************************************************/ 1610 int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 1611 u32 function_mode, u32 standard) 1612 { 1613 int status = 0; 1614 1615 1616 if (mode == V4L2_TUNER_RADIO) { 1617 /* C2HH */ 1618 /* lo if big signal */ 1619 status = cx231xx_reg_mask_write(dev, 1620 VID_BLK_I2C_ADDRESS, 32, 1621 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1622 /* FUNC_MODE = DIF */ 1623 status = cx231xx_reg_mask_write(dev, 1624 VID_BLK_I2C_ADDRESS, 32, 1625 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1626 /* IF_MODE */ 1627 status = cx231xx_reg_mask_write(dev, 1628 VID_BLK_I2C_ADDRESS, 32, 1629 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1630 /* no inv */ 1631 status = cx231xx_reg_mask_write(dev, 1632 VID_BLK_I2C_ADDRESS, 32, 1633 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1634 } else if (standard != DIF_USE_BASEBAND) { 1635 if (standard & V4L2_STD_MN) { 1636 /* lo if big signal */ 1637 status = cx231xx_reg_mask_write(dev, 1638 VID_BLK_I2C_ADDRESS, 32, 1639 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1640 /* FUNC_MODE = DIF */ 1641 status = cx231xx_reg_mask_write(dev, 1642 VID_BLK_I2C_ADDRESS, 32, 1643 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1644 function_mode); 1645 /* IF_MODE */ 1646 status = cx231xx_reg_mask_write(dev, 1647 VID_BLK_I2C_ADDRESS, 32, 1648 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1649 /* no inv */ 1650 status = cx231xx_reg_mask_write(dev, 1651 VID_BLK_I2C_ADDRESS, 32, 1652 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1653 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1654 status = cx231xx_reg_mask_write(dev, 1655 VID_BLK_I2C_ADDRESS, 32, 1656 AUD_IO_CTRL, 0, 31, 0x00000003); 1657 } else if ((standard == V4L2_STD_PAL_I) | 1658 (standard & V4L2_STD_PAL_D) | 1659 (standard & V4L2_STD_SECAM)) { 1660 /* C2HH setup */ 1661 /* lo if big signal */ 1662 status = cx231xx_reg_mask_write(dev, 1663 VID_BLK_I2C_ADDRESS, 32, 1664 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1665 /* FUNC_MODE = DIF */ 1666 status = cx231xx_reg_mask_write(dev, 1667 VID_BLK_I2C_ADDRESS, 32, 1668 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1669 function_mode); 1670 /* IF_MODE */ 1671 status = cx231xx_reg_mask_write(dev, 1672 VID_BLK_I2C_ADDRESS, 32, 1673 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1674 /* no inv */ 1675 status = cx231xx_reg_mask_write(dev, 1676 VID_BLK_I2C_ADDRESS, 32, 1677 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1678 } else { 1679 /* default PAL BG */ 1680 /* C2HH setup */ 1681 /* lo if big signal */ 1682 status = cx231xx_reg_mask_write(dev, 1683 VID_BLK_I2C_ADDRESS, 32, 1684 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1685 /* FUNC_MODE = DIF */ 1686 status = cx231xx_reg_mask_write(dev, 1687 VID_BLK_I2C_ADDRESS, 32, 1688 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1689 function_mode); 1690 /* IF_MODE */ 1691 status = cx231xx_reg_mask_write(dev, 1692 VID_BLK_I2C_ADDRESS, 32, 1693 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1694 /* no inv */ 1695 status = cx231xx_reg_mask_write(dev, 1696 VID_BLK_I2C_ADDRESS, 32, 1697 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1698 } 1699 } 1700 1701 return status; 1702 } 1703 1704 int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard) 1705 { 1706 int status = 0; 1707 u32 dif_misc_ctrl_value = 0; 1708 u32 func_mode = 0; 1709 1710 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1711 1712 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value); 1713 if (standard != DIF_USE_BASEBAND) 1714 dev->norm = standard; 1715 1716 switch (dev->model) { 1717 case CX231XX_BOARD_CNXT_CARRAERA: 1718 case CX231XX_BOARD_CNXT_RDE_250: 1719 case CX231XX_BOARD_CNXT_SHELBY: 1720 case CX231XX_BOARD_CNXT_RDU_250: 1721 case CX231XX_BOARD_CNXT_VIDEO_GRABBER: 1722 case CX231XX_BOARD_HAUPPAUGE_EXETER: 1723 func_mode = 0x03; 1724 break; 1725 case CX231XX_BOARD_CNXT_RDE_253S: 1726 case CX231XX_BOARD_CNXT_RDU_253S: 1727 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_PAL: 1728 case CX231XX_BOARD_HAUPPAUGE_USB2_FM_NTSC: 1729 func_mode = 0x01; 1730 break; 1731 default: 1732 func_mode = 0x01; 1733 } 1734 1735 status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode, 1736 func_mode, standard); 1737 1738 if (standard == DIF_USE_BASEBAND) { /* base band */ 1739 /* There is a different SRC_PHASE_INC value 1740 for baseband vs. DIF */ 1741 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83); 1742 status = vid_blk_read_word(dev, DIF_MISC_CTRL, 1743 &dif_misc_ctrl_value); 1744 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1745 status = vid_blk_write_word(dev, DIF_MISC_CTRL, 1746 dif_misc_ctrl_value); 1747 } else if (standard & V4L2_STD_PAL_D) { 1748 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1749 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1750 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1751 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1752 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1753 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1754 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1755 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1756 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1757 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1758 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1759 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1760 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1761 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1762 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1763 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1764 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1765 DIF_AGC_IF_INT_CURRENT, 0, 31, 1766 0x26001700); 1767 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1768 DIF_AGC_RF_CURRENT, 0, 31, 1769 0x00002660); 1770 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1771 DIF_VIDEO_AGC_CTRL, 0, 31, 1772 0x72500800); 1773 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1774 DIF_VID_AUD_OVERRIDE, 0, 31, 1775 0x27000100); 1776 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1777 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1778 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1779 DIF_COMP_FLT_CTRL, 0, 31, 1780 0x00000000); 1781 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1782 DIF_SRC_PHASE_INC, 0, 31, 1783 0x1befbf06); 1784 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1785 DIF_SRC_GAIN_CONTROL, 0, 31, 1786 0x000035e8); 1787 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1788 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1789 /* Save the Spec Inversion value */ 1790 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1791 dif_misc_ctrl_value |= 0x3a023F11; 1792 } else if (standard & V4L2_STD_PAL_I) { 1793 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1794 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1795 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1796 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1797 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1798 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1799 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1800 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1801 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1802 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1803 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1804 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1805 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1806 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1807 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1808 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1809 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1810 DIF_AGC_IF_INT_CURRENT, 0, 31, 1811 0x26001700); 1812 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1813 DIF_AGC_RF_CURRENT, 0, 31, 1814 0x00002660); 1815 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1816 DIF_VIDEO_AGC_CTRL, 0, 31, 1817 0x72500800); 1818 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1819 DIF_VID_AUD_OVERRIDE, 0, 31, 1820 0x27000100); 1821 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1822 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1823 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1824 DIF_COMP_FLT_CTRL, 0, 31, 1825 0x00000000); 1826 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1827 DIF_SRC_PHASE_INC, 0, 31, 1828 0x1befbf06); 1829 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1830 DIF_SRC_GAIN_CONTROL, 0, 31, 1831 0x000035e8); 1832 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1833 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1834 /* Save the Spec Inversion value */ 1835 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1836 dif_misc_ctrl_value |= 0x3a033F11; 1837 } else if (standard & V4L2_STD_PAL_M) { 1838 /* improved Low Frequency Phase Noise */ 1839 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1840 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1841 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1842 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1843 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1844 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1845 0x26001700); 1846 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1847 0x00002660); 1848 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1849 0x72500800); 1850 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1851 0x27000100); 1852 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d); 1853 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1854 0x009f50c1); 1855 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1856 0x1befbf06); 1857 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1858 0x000035e8); 1859 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1860 0x00000000); 1861 /* Save the Spec Inversion value */ 1862 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1863 dif_misc_ctrl_value |= 0x3A0A3F10; 1864 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1865 /* improved Low Frequency Phase Noise */ 1866 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C); 1867 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85); 1868 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a); 1869 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 1870 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380); 1871 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 1872 0x26001700); 1873 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 1874 0x00002660); 1875 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 1876 0x72500800); 1877 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 1878 0x27000100); 1879 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 1880 0x012c405d); 1881 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 1882 0x009f50c1); 1883 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 1884 0x1befbf06); 1885 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 1886 0x000035e8); 1887 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB, 1888 0x00000000); 1889 /* Save the Spec Inversion value */ 1890 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1891 dif_misc_ctrl_value = 0x3A093F10; 1892 } else if (standard & 1893 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1894 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1895 1896 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1897 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1898 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1899 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1900 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1901 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1902 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1903 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1904 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1905 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1906 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1907 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1908 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1909 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1910 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1911 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1912 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1913 DIF_AGC_IF_INT_CURRENT, 0, 31, 1914 0x26001700); 1915 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1916 DIF_AGC_RF_CURRENT, 0, 31, 1917 0x00002660); 1918 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1919 DIF_VID_AUD_OVERRIDE, 0, 31, 1920 0x27000100); 1921 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1922 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1923 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1924 DIF_COMP_FLT_CTRL, 0, 31, 1925 0x00000000); 1926 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1927 DIF_SRC_PHASE_INC, 0, 31, 1928 0x1befbf06); 1929 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1930 DIF_SRC_GAIN_CONTROL, 0, 31, 1931 0x000035e8); 1932 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1933 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1934 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1935 DIF_VIDEO_AGC_CTRL, 0, 31, 1936 0xf4000000); 1937 1938 /* Save the Spec Inversion value */ 1939 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1940 dif_misc_ctrl_value |= 0x3a023F11; 1941 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1942 /* Is it SECAM_L1? */ 1943 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1944 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1945 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1946 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1947 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1948 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1949 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1950 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1951 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1952 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1953 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1954 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1955 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1956 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1957 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1958 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1959 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1960 DIF_AGC_IF_INT_CURRENT, 0, 31, 1961 0x26001700); 1962 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1963 DIF_AGC_RF_CURRENT, 0, 31, 1964 0x00002660); 1965 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1966 DIF_VID_AUD_OVERRIDE, 0, 31, 1967 0x27000100); 1968 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1969 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1970 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1971 DIF_COMP_FLT_CTRL, 0, 31, 1972 0x00000000); 1973 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1974 DIF_SRC_PHASE_INC, 0, 31, 1975 0x1befbf06); 1976 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1977 DIF_SRC_GAIN_CONTROL, 0, 31, 1978 0x000035e8); 1979 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1980 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1981 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 1982 DIF_VIDEO_AGC_CTRL, 0, 31, 1983 0xf2560000); 1984 1985 /* Save the Spec Inversion value */ 1986 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1987 dif_misc_ctrl_value |= 0x3a023F11; 1988 1989 } else if (standard & V4L2_STD_NTSC_M) { 1990 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 1991 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1992 1993 /* For NTSC the centre frequency of video coming out of 1994 sidewinder is around 7.1MHz or 3.6MHz depending on the 1995 spectral inversion. so for a non spectrally inverted channel 1996 the pll freq word is 0x03420c49 1997 */ 1998 1999 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C); 2000 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85); 2001 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A); 2002 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800); 2003 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380); 2004 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT, 2005 0x26001700); 2006 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT, 2007 0x00002660); 2008 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL, 2009 0x04000800); 2010 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE, 2011 0x27000100); 2012 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f); 2013 2014 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL, 2015 0x009f50c1); 2016 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 2017 0x1befbf06); 2018 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL, 2019 0x000035e8); 2020 2021 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600); 2022 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT, 2023 0xC2262600); 2024 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600); 2025 2026 /* Save the Spec Inversion value */ 2027 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2028 dif_misc_ctrl_value |= 0x3a003F10; 2029 } else { 2030 /* default PAL BG */ 2031 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2032 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 2033 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2034 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 2035 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2036 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 2037 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2038 DIF_PLL_CTRL3, 0, 31, 0x00008800); 2039 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2040 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 2041 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2042 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 2043 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2044 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 2045 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2046 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 2047 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2048 DIF_AGC_IF_INT_CURRENT, 0, 31, 2049 0x26001700); 2050 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2051 DIF_AGC_RF_CURRENT, 0, 31, 2052 0x00002660); 2053 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2054 DIF_VIDEO_AGC_CTRL, 0, 31, 2055 0x72500800); 2056 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2057 DIF_VID_AUD_OVERRIDE, 0, 31, 2058 0x27000100); 2059 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2060 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 2061 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2062 DIF_COMP_FLT_CTRL, 0, 31, 2063 0x00A653A8); 2064 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2065 DIF_SRC_PHASE_INC, 0, 31, 2066 0x1befbf06); 2067 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2068 DIF_SRC_GAIN_CONTROL, 0, 31, 2069 0x000035e8); 2070 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32, 2071 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 2072 /* Save the Spec Inversion value */ 2073 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 2074 dif_misc_ctrl_value |= 0x3a013F11; 2075 } 2076 2077 /* The AGC values should be the same for all standards, 2078 AUD_SRC_SEL[19] should always be disabled */ 2079 dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL; 2080 2081 /* It is still possible to get Set Standard calls even when we 2082 are in FM mode. 2083 This is done to override the value for FM. */ 2084 if (dev->active_mode == V4L2_TUNER_RADIO) 2085 dif_misc_ctrl_value = 0x7a080000; 2086 2087 /* Write the calculated value for misc ontrol register */ 2088 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value); 2089 2090 return status; 2091 } 2092 2093 int cx231xx_tuner_pre_channel_change(struct cx231xx *dev) 2094 { 2095 int status = 0; 2096 u32 dwval; 2097 2098 /* Set the RF and IF k_agc values to 3 */ 2099 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2100 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2101 dwval |= 0x33000000; 2102 2103 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2104 2105 return status; 2106 } 2107 2108 int cx231xx_tuner_post_channel_change(struct cx231xx *dev) 2109 { 2110 int status = 0; 2111 u32 dwval; 2112 cx231xx_info("cx231xx_tuner_post_channel_change dev->tuner_type =0%d\n", 2113 dev->tuner_type); 2114 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 2115 * SECAM L/B/D standards */ 2116 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval); 2117 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 2118 2119 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 2120 V4L2_STD_SECAM_D)) { 2121 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2122 dwval &= ~FLD_DIF_IF_REF; 2123 dwval |= 0x88000300; 2124 } else 2125 dwval |= 0x88000000; 2126 } else { 2127 if (dev->tuner_type == TUNER_NXP_TDA18271) { 2128 dwval &= ~FLD_DIF_IF_REF; 2129 dwval |= 0xCC000300; 2130 } else 2131 dwval |= 0x44000000; 2132 } 2133 2134 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval); 2135 2136 return status; 2137 } 2138 2139 /****************************************************************************** 2140 * I 2 S - B L O C K C O N T R O L functions * 2141 ******************************************************************************/ 2142 int cx231xx_i2s_blk_initialize(struct cx231xx *dev) 2143 { 2144 int status = 0; 2145 u32 value; 2146 2147 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2148 CH_PWR_CTRL1, 1, &value, 1); 2149 /* enables clock to delta-sigma and decimation filter */ 2150 value |= 0x80; 2151 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2152 CH_PWR_CTRL1, 1, value, 1); 2153 /* power up all channel */ 2154 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2155 CH_PWR_CTRL2, 1, 0x00, 1); 2156 2157 return status; 2158 } 2159 2160 int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev, 2161 enum AV_MODE avmode) 2162 { 2163 int status = 0; 2164 u32 value = 0; 2165 2166 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 2167 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2168 CH_PWR_CTRL2, 1, &value, 1); 2169 value |= 0xfe; 2170 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2171 CH_PWR_CTRL2, 1, value, 1); 2172 } else { 2173 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2174 CH_PWR_CTRL2, 1, 0x00, 1); 2175 } 2176 2177 return status; 2178 } 2179 2180 /* set i2s_blk for audio input types */ 2181 int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input) 2182 { 2183 int status = 0; 2184 2185 switch (audio_input) { 2186 case CX231XX_AMUX_LINE_IN: 2187 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2188 CH_PWR_CTRL2, 1, 0x00, 1); 2189 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS, 2190 CH_PWR_CTRL1, 1, 0x80, 1); 2191 break; 2192 case CX231XX_AMUX_VIDEO: 2193 default: 2194 break; 2195 } 2196 2197 dev->ctl_ainput = audio_input; 2198 2199 return status; 2200 } 2201 2202 /****************************************************************************** 2203 * P O W E R C O N T R O L functions * 2204 ******************************************************************************/ 2205 int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode) 2206 { 2207 u8 value[4] = { 0, 0, 0, 0 }; 2208 u32 tmp = 0; 2209 int status = 0; 2210 2211 if (dev->power_mode != mode) 2212 dev->power_mode = mode; 2213 else { 2214 cx231xx_info(" setPowerMode::mode = %d, No Change req.\n", 2215 mode); 2216 return 0; 2217 } 2218 2219 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2220 4); 2221 if (status < 0) 2222 return status; 2223 2224 tmp = *((u32 *) value); 2225 2226 switch (mode) { 2227 case POLARIS_AVMODE_ENXTERNAL_AV: 2228 2229 tmp &= (~PWR_MODE_MASK); 2230 2231 tmp |= PWR_AV_EN; 2232 value[0] = (u8) tmp; 2233 value[1] = (u8) (tmp >> 8); 2234 value[2] = (u8) (tmp >> 16); 2235 value[3] = (u8) (tmp >> 24); 2236 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2237 PWR_CTL_EN, value, 4); 2238 msleep(PWR_SLEEP_INTERVAL); 2239 2240 tmp |= PWR_ISO_EN; 2241 value[0] = (u8) tmp; 2242 value[1] = (u8) (tmp >> 8); 2243 value[2] = (u8) (tmp >> 16); 2244 value[3] = (u8) (tmp >> 24); 2245 status = 2246 cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2247 value, 4); 2248 msleep(PWR_SLEEP_INTERVAL); 2249 2250 tmp |= POLARIS_AVMODE_ENXTERNAL_AV; 2251 value[0] = (u8) tmp; 2252 value[1] = (u8) (tmp >> 8); 2253 value[2] = (u8) (tmp >> 16); 2254 value[3] = (u8) (tmp >> 24); 2255 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2256 PWR_CTL_EN, value, 4); 2257 2258 /* reset state of xceive tuner */ 2259 dev->xc_fw_load_done = 0; 2260 break; 2261 2262 case POLARIS_AVMODE_ANALOGT_TV: 2263 2264 tmp |= PWR_DEMOD_EN; 2265 tmp |= (I2C_DEMOD_EN); 2266 value[0] = (u8) tmp; 2267 value[1] = (u8) (tmp >> 8); 2268 value[2] = (u8) (tmp >> 16); 2269 value[3] = (u8) (tmp >> 24); 2270 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2271 PWR_CTL_EN, value, 4); 2272 msleep(PWR_SLEEP_INTERVAL); 2273 2274 if (!(tmp & PWR_TUNER_EN)) { 2275 tmp |= (PWR_TUNER_EN); 2276 value[0] = (u8) tmp; 2277 value[1] = (u8) (tmp >> 8); 2278 value[2] = (u8) (tmp >> 16); 2279 value[3] = (u8) (tmp >> 24); 2280 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2281 PWR_CTL_EN, value, 4); 2282 msleep(PWR_SLEEP_INTERVAL); 2283 } 2284 2285 if (!(tmp & PWR_AV_EN)) { 2286 tmp |= PWR_AV_EN; 2287 value[0] = (u8) tmp; 2288 value[1] = (u8) (tmp >> 8); 2289 value[2] = (u8) (tmp >> 16); 2290 value[3] = (u8) (tmp >> 24); 2291 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2292 PWR_CTL_EN, value, 4); 2293 msleep(PWR_SLEEP_INTERVAL); 2294 } 2295 if (!(tmp & PWR_ISO_EN)) { 2296 tmp |= PWR_ISO_EN; 2297 value[0] = (u8) tmp; 2298 value[1] = (u8) (tmp >> 8); 2299 value[2] = (u8) (tmp >> 16); 2300 value[3] = (u8) (tmp >> 24); 2301 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2302 PWR_CTL_EN, value, 4); 2303 msleep(PWR_SLEEP_INTERVAL); 2304 } 2305 2306 if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) { 2307 tmp |= POLARIS_AVMODE_ANALOGT_TV; 2308 value[0] = (u8) tmp; 2309 value[1] = (u8) (tmp >> 8); 2310 value[2] = (u8) (tmp >> 16); 2311 value[3] = (u8) (tmp >> 24); 2312 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2313 PWR_CTL_EN, value, 4); 2314 msleep(PWR_SLEEP_INTERVAL); 2315 } 2316 2317 if (dev->board.tuner_type != TUNER_ABSENT) { 2318 /* Enable tuner */ 2319 cx231xx_enable_i2c_port_3(dev, true); 2320 2321 /* reset the Tuner */ 2322 if (dev->board.tuner_gpio) 2323 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2324 2325 if (dev->cx231xx_reset_analog_tuner) 2326 dev->cx231xx_reset_analog_tuner(dev); 2327 } 2328 2329 break; 2330 2331 case POLARIS_AVMODE_DIGITAL: 2332 if (!(tmp & PWR_TUNER_EN)) { 2333 tmp |= (PWR_TUNER_EN); 2334 value[0] = (u8) tmp; 2335 value[1] = (u8) (tmp >> 8); 2336 value[2] = (u8) (tmp >> 16); 2337 value[3] = (u8) (tmp >> 24); 2338 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2339 PWR_CTL_EN, value, 4); 2340 msleep(PWR_SLEEP_INTERVAL); 2341 } 2342 if (!(tmp & PWR_AV_EN)) { 2343 tmp |= PWR_AV_EN; 2344 value[0] = (u8) tmp; 2345 value[1] = (u8) (tmp >> 8); 2346 value[2] = (u8) (tmp >> 16); 2347 value[3] = (u8) (tmp >> 24); 2348 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2349 PWR_CTL_EN, value, 4); 2350 msleep(PWR_SLEEP_INTERVAL); 2351 } 2352 if (!(tmp & PWR_ISO_EN)) { 2353 tmp |= PWR_ISO_EN; 2354 value[0] = (u8) tmp; 2355 value[1] = (u8) (tmp >> 8); 2356 value[2] = (u8) (tmp >> 16); 2357 value[3] = (u8) (tmp >> 24); 2358 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2359 PWR_CTL_EN, value, 4); 2360 msleep(PWR_SLEEP_INTERVAL); 2361 } 2362 2363 tmp &= (~PWR_AV_MODE); 2364 tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN; 2365 value[0] = (u8) tmp; 2366 value[1] = (u8) (tmp >> 8); 2367 value[2] = (u8) (tmp >> 16); 2368 value[3] = (u8) (tmp >> 24); 2369 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2370 PWR_CTL_EN, value, 4); 2371 msleep(PWR_SLEEP_INTERVAL); 2372 2373 if (!(tmp & PWR_DEMOD_EN)) { 2374 tmp |= PWR_DEMOD_EN; 2375 value[0] = (u8) tmp; 2376 value[1] = (u8) (tmp >> 8); 2377 value[2] = (u8) (tmp >> 16); 2378 value[3] = (u8) (tmp >> 24); 2379 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2380 PWR_CTL_EN, value, 4); 2381 msleep(PWR_SLEEP_INTERVAL); 2382 } 2383 2384 if (dev->board.tuner_type != TUNER_ABSENT) { 2385 /* 2386 * Enable tuner 2387 * Hauppauge Exeter seems to need to do something different! 2388 */ 2389 if (dev->model == CX231XX_BOARD_HAUPPAUGE_EXETER) 2390 cx231xx_enable_i2c_port_3(dev, false); 2391 else 2392 cx231xx_enable_i2c_port_3(dev, true); 2393 2394 /* reset the Tuner */ 2395 if (dev->board.tuner_gpio) 2396 cx231xx_gpio_set(dev, dev->board.tuner_gpio); 2397 2398 if (dev->cx231xx_reset_analog_tuner) 2399 dev->cx231xx_reset_analog_tuner(dev); 2400 } 2401 break; 2402 2403 default: 2404 break; 2405 } 2406 2407 msleep(PWR_SLEEP_INTERVAL); 2408 2409 /* For power saving, only enable Pwr_resetout_n 2410 when digital TV is selected. */ 2411 if (mode == POLARIS_AVMODE_DIGITAL) { 2412 tmp |= PWR_RESETOUT_EN; 2413 value[0] = (u8) tmp; 2414 value[1] = (u8) (tmp >> 8); 2415 value[2] = (u8) (tmp >> 16); 2416 value[3] = (u8) (tmp >> 24); 2417 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2418 PWR_CTL_EN, value, 4); 2419 msleep(PWR_SLEEP_INTERVAL); 2420 } 2421 2422 /* update power control for afe */ 2423 status = cx231xx_afe_update_power_control(dev, mode); 2424 2425 /* update power control for i2s_blk */ 2426 status = cx231xx_i2s_blk_update_power_control(dev, mode); 2427 2428 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 2429 4); 2430 2431 return status; 2432 } 2433 2434 int cx231xx_power_suspend(struct cx231xx *dev) 2435 { 2436 u8 value[4] = { 0, 0, 0, 0 }; 2437 u32 tmp = 0; 2438 int status = 0; 2439 2440 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, 2441 value, 4); 2442 if (status > 0) 2443 return status; 2444 2445 tmp = *((u32 *) value); 2446 tmp &= (~PWR_MODE_MASK); 2447 2448 value[0] = (u8) tmp; 2449 value[1] = (u8) (tmp >> 8); 2450 value[2] = (u8) (tmp >> 16); 2451 value[3] = (u8) (tmp >> 24); 2452 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN, 2453 value, 4); 2454 2455 return status; 2456 } 2457 2458 /****************************************************************************** 2459 * S T R E A M C O N T R O L functions * 2460 ******************************************************************************/ 2461 int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask) 2462 { 2463 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2464 u32 tmp = 0; 2465 int status = 0; 2466 2467 cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask); 2468 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, 2469 value, 4); 2470 if (status < 0) 2471 return status; 2472 2473 tmp = *((u32 *) value); 2474 tmp |= ep_mask; 2475 value[0] = (u8) tmp; 2476 value[1] = (u8) (tmp >> 8); 2477 value[2] = (u8) (tmp >> 16); 2478 value[3] = (u8) (tmp >> 24); 2479 2480 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2481 value, 4); 2482 2483 return status; 2484 } 2485 2486 int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask) 2487 { 2488 u8 value[4] = { 0x0, 0x0, 0x0, 0x0 }; 2489 u32 tmp = 0; 2490 int status = 0; 2491 2492 cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask); 2493 status = 2494 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4); 2495 if (status < 0) 2496 return status; 2497 2498 tmp = *((u32 *) value); 2499 tmp &= (~ep_mask); 2500 value[0] = (u8) tmp; 2501 value[1] = (u8) (tmp >> 8); 2502 value[2] = (u8) (tmp >> 16); 2503 value[3] = (u8) (tmp >> 24); 2504 2505 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET, 2506 value, 4); 2507 2508 return status; 2509 } 2510 2511 int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type) 2512 { 2513 int status = 0; 2514 u32 value = 0; 2515 u8 val[4] = { 0, 0, 0, 0 }; 2516 2517 if (dev->udev->speed == USB_SPEED_HIGH) { 2518 switch (media_type) { 2519 case Audio: 2520 cx231xx_info("%s: Audio enter HANC\n", __func__); 2521 status = 2522 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2523 break; 2524 2525 case Vbi: 2526 cx231xx_info("%s: set vanc registers\n", __func__); 2527 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300); 2528 break; 2529 2530 case Sliced_cc: 2531 cx231xx_info("%s: set hanc registers\n", __func__); 2532 status = 2533 cx231xx_mode_register(dev, TS_MODE_REG, 0x1300); 2534 break; 2535 2536 case Raw_Video: 2537 cx231xx_info("%s: set video registers\n", __func__); 2538 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2539 break; 2540 2541 case TS1_serial_mode: 2542 cx231xx_info("%s: set ts1 registers", __func__); 2543 2544 if (dev->board.has_417) { 2545 cx231xx_info(" MPEG\n"); 2546 value &= 0xFFFFFFFC; 2547 value |= 0x3; 2548 2549 status = cx231xx_mode_register(dev, TS_MODE_REG, value); 2550 2551 val[0] = 0x04; 2552 val[1] = 0xA3; 2553 val[2] = 0x3B; 2554 val[3] = 0x00; 2555 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2556 TS1_CFG_REG, val, 4); 2557 2558 val[0] = 0x00; 2559 val[1] = 0x08; 2560 val[2] = 0x00; 2561 val[3] = 0x08; 2562 status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, 2563 TS1_LENGTH_REG, val, 4); 2564 2565 } else { 2566 cx231xx_info(" BDA\n"); 2567 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2568 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x010); 2569 } 2570 break; 2571 2572 case TS1_parallel_mode: 2573 cx231xx_info("%s: set ts1 parallel mode registers\n", 2574 __func__); 2575 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100); 2576 status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400); 2577 break; 2578 } 2579 } else { 2580 status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101); 2581 } 2582 2583 return status; 2584 } 2585 2586 int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type) 2587 { 2588 int rc = -1; 2589 u32 ep_mask = -1; 2590 struct pcb_config *pcb_config; 2591 2592 /* get EP for media type */ 2593 pcb_config = (struct pcb_config *)&dev->current_pcb_config; 2594 2595 if (pcb_config->config_num) { 2596 switch (media_type) { 2597 case Raw_Video: 2598 ep_mask = ENABLE_EP4; /* ep4 [00:1000] */ 2599 break; 2600 case Audio: 2601 ep_mask = ENABLE_EP3; /* ep3 [00:0100] */ 2602 break; 2603 case Vbi: 2604 ep_mask = ENABLE_EP5; /* ep5 [01:0000] */ 2605 break; 2606 case Sliced_cc: 2607 ep_mask = ENABLE_EP6; /* ep6 [10:0000] */ 2608 break; 2609 case TS1_serial_mode: 2610 case TS1_parallel_mode: 2611 ep_mask = ENABLE_EP1; /* ep1 [00:0001] */ 2612 break; 2613 case TS2: 2614 ep_mask = ENABLE_EP2; /* ep2 [00:0010] */ 2615 break; 2616 } 2617 } 2618 2619 if (start) { 2620 rc = cx231xx_initialize_stream_xfer(dev, media_type); 2621 2622 if (rc < 0) 2623 return rc; 2624 2625 /* enable video capture */ 2626 if (ep_mask > 0) 2627 rc = cx231xx_start_stream(dev, ep_mask); 2628 } else { 2629 /* disable video capture */ 2630 if (ep_mask > 0) 2631 rc = cx231xx_stop_stream(dev, ep_mask); 2632 } 2633 2634 return rc; 2635 } 2636 EXPORT_SYMBOL_GPL(cx231xx_capture_start); 2637 2638 /***************************************************************************** 2639 * G P I O B I T control functions * 2640 ******************************************************************************/ 2641 int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) 2642 { 2643 int status = 0; 2644 2645 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0); 2646 2647 return status; 2648 } 2649 2650 int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 *gpio_val) 2651 { 2652 int status = 0; 2653 2654 status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1); 2655 2656 return status; 2657 } 2658 2659 /* 2660 * cx231xx_set_gpio_direction 2661 * Sets the direction of the GPIO pin to input or output 2662 * 2663 * Parameters : 2664 * pin_number : The GPIO Pin number to program the direction for 2665 * from 0 to 31 2666 * pin_value : The Direction of the GPIO Pin under reference. 2667 * 0 = Input direction 2668 * 1 = Output direction 2669 */ 2670 int cx231xx_set_gpio_direction(struct cx231xx *dev, 2671 int pin_number, int pin_value) 2672 { 2673 int status = 0; 2674 u32 value = 0; 2675 2676 /* Check for valid pin_number - if 32 , bail out */ 2677 if (pin_number >= 32) 2678 return -EINVAL; 2679 2680 /* input */ 2681 if (pin_value == 0) 2682 value = dev->gpio_dir & (~(1 << pin_number)); /* clear */ 2683 else 2684 value = dev->gpio_dir | (1 << pin_number); 2685 2686 status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val); 2687 2688 /* cache the value for future */ 2689 dev->gpio_dir = value; 2690 2691 return status; 2692 } 2693 2694 /* 2695 * cx231xx_set_gpio_value 2696 * Sets the value of the GPIO pin to Logic high or low. The Pin under 2697 * reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2698 * 2699 * Parameters : 2700 * pin_number : The GPIO Pin number to program the direction for 2701 * pin_value : The value of the GPIO Pin under reference. 2702 * 0 = set it to 0 2703 * 1 = set it to 1 2704 */ 2705 int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value) 2706 { 2707 int status = 0; 2708 u32 value = 0; 2709 2710 /* Check for valid pin_number - if 0xFF , bail out */ 2711 if (pin_number >= 32) 2712 return -EINVAL; 2713 2714 /* first do a sanity check - if the Pin is not output, make it output */ 2715 if ((dev->gpio_dir & (1 << pin_number)) == 0x00) { 2716 /* It was in input mode */ 2717 value = dev->gpio_dir | (1 << pin_number); 2718 dev->gpio_dir = value; 2719 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2720 (u8 *) &dev->gpio_val); 2721 value = 0; 2722 } 2723 2724 if (pin_value == 0) 2725 value = dev->gpio_val & (~(1 << pin_number)); 2726 else 2727 value = dev->gpio_val | (1 << pin_number); 2728 2729 /* store the value */ 2730 dev->gpio_val = value; 2731 2732 /* toggle bit0 of GP_IO */ 2733 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2734 2735 return status; 2736 } 2737 2738 /***************************************************************************** 2739 * G P I O I2C related functions * 2740 ******************************************************************************/ 2741 int cx231xx_gpio_i2c_start(struct cx231xx *dev) 2742 { 2743 int status = 0; 2744 2745 /* set SCL to output 1 ; set SDA to output 1 */ 2746 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2747 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2748 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2749 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2750 2751 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2752 if (status < 0) 2753 return -EINVAL; 2754 2755 /* set SCL to output 1; set SDA to output 0 */ 2756 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2757 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2758 2759 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2760 if (status < 0) 2761 return -EINVAL; 2762 2763 /* set SCL to output 0; set SDA to output 0 */ 2764 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2765 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2766 2767 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2768 if (status < 0) 2769 return -EINVAL; 2770 2771 return status; 2772 } 2773 2774 int cx231xx_gpio_i2c_end(struct cx231xx *dev) 2775 { 2776 int status = 0; 2777 2778 /* set SCL to output 0; set SDA to output 0 */ 2779 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2780 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2781 2782 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2783 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2784 2785 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2786 if (status < 0) 2787 return -EINVAL; 2788 2789 /* set SCL to output 1; set SDA to output 0 */ 2790 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2791 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2792 2793 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2794 if (status < 0) 2795 return -EINVAL; 2796 2797 /* set SCL to input ,release SCL cable control 2798 set SDA to input ,release SDA cable control */ 2799 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2800 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2801 2802 status = 2803 cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2804 if (status < 0) 2805 return -EINVAL; 2806 2807 return status; 2808 } 2809 2810 int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data) 2811 { 2812 int status = 0; 2813 u8 i; 2814 2815 /* set SCL to output ; set SDA to output */ 2816 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2817 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2818 2819 for (i = 0; i < 8; i++) { 2820 if (((data << i) & 0x80) == 0) { 2821 /* set SCL to output 0; set SDA to output 0 */ 2822 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2823 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2824 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2825 (u8 *)&dev->gpio_val); 2826 2827 /* set SCL to output 1; set SDA to output 0 */ 2828 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2829 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2830 (u8 *)&dev->gpio_val); 2831 2832 /* set SCL to output 0; set SDA to output 0 */ 2833 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2834 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2835 (u8 *)&dev->gpio_val); 2836 } else { 2837 /* set SCL to output 0; set SDA to output 1 */ 2838 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2839 dev->gpio_val |= 1 << dev->board.tuner_sda_gpio; 2840 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2841 (u8 *)&dev->gpio_val); 2842 2843 /* set SCL to output 1; set SDA to output 1 */ 2844 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2845 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2846 (u8 *)&dev->gpio_val); 2847 2848 /* set SCL to output 0; set SDA to output 1 */ 2849 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2850 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2851 (u8 *)&dev->gpio_val); 2852 } 2853 } 2854 return status; 2855 } 2856 2857 int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 *buf) 2858 { 2859 u8 value = 0; 2860 int status = 0; 2861 u32 gpio_logic_value = 0; 2862 u8 i; 2863 2864 /* read byte */ 2865 for (i = 0; i < 8; i++) { /* send write I2c addr */ 2866 2867 /* set SCL to output 0; set SDA to input */ 2868 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2869 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2870 (u8 *)&dev->gpio_val); 2871 2872 /* set SCL to output 1; set SDA to input */ 2873 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2874 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, 2875 (u8 *)&dev->gpio_val); 2876 2877 /* get SDA data bit */ 2878 gpio_logic_value = dev->gpio_val; 2879 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2880 (u8 *)&dev->gpio_val); 2881 if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0) 2882 value |= (1 << (8 - i - 1)); 2883 2884 dev->gpio_val = gpio_logic_value; 2885 } 2886 2887 /* set SCL to output 0,finish the read latest SCL signal. 2888 !!!set SDA to input, never to modify SDA direction at 2889 the same times */ 2890 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2891 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2892 2893 /* store the value */ 2894 *buf = value & 0xff; 2895 2896 return status; 2897 } 2898 2899 int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev) 2900 { 2901 int status = 0; 2902 u32 gpio_logic_value = 0; 2903 int nCnt = 10; 2904 int nInit = nCnt; 2905 2906 /* clock stretch; set SCL to input; set SDA to input; 2907 get SCL value till SCL = 1 */ 2908 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2909 dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio); 2910 2911 gpio_logic_value = dev->gpio_val; 2912 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2913 2914 do { 2915 msleep(2); 2916 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, 2917 (u8 *)&dev->gpio_val); 2918 nCnt--; 2919 } while (((dev->gpio_val & 2920 (1 << dev->board.tuner_scl_gpio)) == 0) && 2921 (nCnt > 0)); 2922 2923 if (nCnt == 0) 2924 cx231xx_info("No ACK after %d msec -GPIO I2C failed!", 2925 nInit * 10); 2926 2927 /* 2928 * readAck 2929 * through clock stretch, slave has given a SCL signal, 2930 * so the SDA data can be directly read. 2931 */ 2932 status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2933 2934 if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) { 2935 dev->gpio_val = gpio_logic_value; 2936 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2937 status = 0; 2938 } else { 2939 dev->gpio_val = gpio_logic_value; 2940 dev->gpio_val |= (1 << dev->board.tuner_sda_gpio); 2941 } 2942 2943 /* read SDA end, set the SCL to output 0, after this operation, 2944 SDA direction can be changed. */ 2945 dev->gpio_val = gpio_logic_value; 2946 dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio); 2947 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2948 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2949 2950 return status; 2951 } 2952 2953 int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev) 2954 { 2955 int status = 0; 2956 2957 /* set SDA to ouput */ 2958 dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio; 2959 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2960 2961 /* set SCL = 0 (output); set SDA = 0 (output) */ 2962 dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio); 2963 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2964 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2965 2966 /* set SCL = 1 (output); set SDA = 0 (output) */ 2967 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2968 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2969 2970 /* set SCL = 0 (output); set SDA = 0 (output) */ 2971 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2972 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2973 2974 /* set SDA to input,and then the slave will read data from SDA. */ 2975 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2976 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2977 2978 return status; 2979 } 2980 2981 int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev) 2982 { 2983 int status = 0; 2984 2985 /* set scl to output ; set sda to input */ 2986 dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio; 2987 dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio); 2988 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2989 2990 /* set scl to output 0; set sda to input */ 2991 dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio); 2992 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2993 2994 /* set scl to output 1; set sda to input */ 2995 dev->gpio_val |= 1 << dev->board.tuner_scl_gpio; 2996 status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val); 2997 2998 return status; 2999 } 3000 3001 /***************************************************************************** 3002 * G P I O I2C related functions * 3003 ******************************************************************************/ 3004 /* cx231xx_gpio_i2c_read 3005 * Function to read data from gpio based I2C interface 3006 */ 3007 int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3008 { 3009 int status = 0; 3010 int i = 0; 3011 3012 /* get the lock */ 3013 mutex_lock(&dev->gpio_i2c_lock); 3014 3015 /* start */ 3016 status = cx231xx_gpio_i2c_start(dev); 3017 3018 /* write dev_addr */ 3019 status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1); 3020 3021 /* readAck */ 3022 status = cx231xx_gpio_i2c_read_ack(dev); 3023 3024 /* read data */ 3025 for (i = 0; i < len; i++) { 3026 /* read data */ 3027 buf[i] = 0; 3028 status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]); 3029 3030 if ((i + 1) != len) { 3031 /* only do write ack if we more length */ 3032 status = cx231xx_gpio_i2c_write_ack(dev); 3033 } 3034 } 3035 3036 /* write NAK - inform reads are complete */ 3037 status = cx231xx_gpio_i2c_write_nak(dev); 3038 3039 /* write end */ 3040 status = cx231xx_gpio_i2c_end(dev); 3041 3042 /* release the lock */ 3043 mutex_unlock(&dev->gpio_i2c_lock); 3044 3045 return status; 3046 } 3047 3048 /* cx231xx_gpio_i2c_write 3049 * Function to write data to gpio based I2C interface 3050 */ 3051 int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 *buf, u8 len) 3052 { 3053 int i = 0; 3054 3055 /* get the lock */ 3056 mutex_lock(&dev->gpio_i2c_lock); 3057 3058 /* start */ 3059 cx231xx_gpio_i2c_start(dev); 3060 3061 /* write dev_addr */ 3062 cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1); 3063 3064 /* read Ack */ 3065 cx231xx_gpio_i2c_read_ack(dev); 3066 3067 for (i = 0; i < len; i++) { 3068 /* Write data */ 3069 cx231xx_gpio_i2c_write_byte(dev, buf[i]); 3070 3071 /* read Ack */ 3072 cx231xx_gpio_i2c_read_ack(dev); 3073 } 3074 3075 /* write End */ 3076 cx231xx_gpio_i2c_end(dev); 3077 3078 /* release the lock */ 3079 mutex_unlock(&dev->gpio_i2c_lock); 3080 3081 return 0; 3082 } 3083