1 /* 2 * Sharp QM1D1C0042 8PSK tuner driver 3 * 4 * Copyright (C) 2014 Akihiro Tsukada <tskd08@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 /* 18 * NOTICE: 19 * As the disclosed information on the chip is very limited, 20 * this driver lacks some features, including chip config like IF freq. 21 * It assumes that users of this driver (such as a PCI bridge of 22 * DTV receiver cards) know the relevant info and 23 * configure the chip via I2C if necessary. 24 * 25 * Currently, PT3 driver is the only one that uses this driver, 26 * and contains init/config code in its firmware. 27 * Thus some part of the code might be dependent on PT3 specific config. 28 */ 29 30 #include <linux/kernel.h> 31 #include <linux/math64.h> 32 #include "qm1d1c0042.h" 33 34 #define QM1D1C0042_NUM_REGS 0x20 35 36 static const u8 reg_initval[QM1D1C0042_NUM_REGS] = { 37 0x48, 0x1c, 0xa0, 0x10, 0xbc, 0xc5, 0x20, 0x33, 38 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 39 0x00, 0xff, 0xf3, 0x00, 0x2a, 0x64, 0xa6, 0x86, 40 0x8c, 0xcf, 0xb8, 0xf1, 0xa8, 0xf2, 0x89, 0x00 41 }; 42 43 static const struct qm1d1c0042_config default_cfg = { 44 .xtal_freq = 16000, 45 .lpf = 1, 46 .fast_srch = 0, 47 .lpf_wait = 20, 48 .fast_srch_wait = 4, 49 .normal_srch_wait = 15, 50 }; 51 52 struct qm1d1c0042_state { 53 struct qm1d1c0042_config cfg; 54 struct i2c_client *i2c; 55 u8 regs[QM1D1C0042_NUM_REGS]; 56 }; 57 58 static struct qm1d1c0042_state *cfg_to_state(struct qm1d1c0042_config *c) 59 { 60 return container_of(c, struct qm1d1c0042_state, cfg); 61 } 62 63 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) 64 { 65 u8 wbuf[2] = { reg, val }; 66 int ret; 67 68 ret = i2c_master_send(state->i2c, wbuf, sizeof(wbuf)); 69 if (ret >= 0 && ret < sizeof(wbuf)) 70 ret = -EIO; 71 return (ret == sizeof(wbuf)) ? 0 : ret; 72 } 73 74 static int reg_read(struct qm1d1c0042_state *state, u8 reg, u8 *val) 75 { 76 struct i2c_msg msgs[2] = { 77 { 78 .addr = state->i2c->addr, 79 .flags = 0, 80 .buf = ®, 81 .len = 1, 82 }, 83 { 84 .addr = state->i2c->addr, 85 .flags = I2C_M_RD, 86 .buf = val, 87 .len = 1, 88 }, 89 }; 90 int ret; 91 92 ret = i2c_transfer(state->i2c->adapter, msgs, ARRAY_SIZE(msgs)); 93 if (ret >= 0 && ret < ARRAY_SIZE(msgs)) 94 ret = -EIO; 95 return (ret == ARRAY_SIZE(msgs)) ? 0 : ret; 96 } 97 98 99 static int qm1d1c0042_set_srch_mode(struct qm1d1c0042_state *state, bool fast) 100 { 101 if (fast) 102 state->regs[0x03] |= 0x01; /* set fast search mode */ 103 else 104 state->regs[0x03] &= ~0x01 & 0xff; 105 106 return reg_write(state, 0x03, state->regs[0x03]); 107 } 108 109 static int qm1d1c0042_wakeup(struct qm1d1c0042_state *state) 110 { 111 int ret; 112 113 state->regs[0x01] |= 1 << 3; /* BB_Reg_enable */ 114 state->regs[0x01] &= (~(1 << 0)) & 0xff; /* NORMAL (wake-up) */ 115 state->regs[0x05] &= (~(1 << 3)) & 0xff; /* pfd_rst NORMAL */ 116 ret = reg_write(state, 0x01, state->regs[0x01]); 117 if (ret == 0) 118 ret = reg_write(state, 0x05, state->regs[0x05]); 119 120 if (ret < 0) 121 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 122 __func__, state->cfg.fe->dvb->num, state->cfg.fe->id); 123 return ret; 124 } 125 126 /* tuner_ops */ 127 128 static int qm1d1c0042_set_config(struct dvb_frontend *fe, void *priv_cfg) 129 { 130 struct qm1d1c0042_state *state; 131 struct qm1d1c0042_config *cfg; 132 133 state = fe->tuner_priv; 134 cfg = priv_cfg; 135 136 if (cfg->fe) 137 state->cfg.fe = cfg->fe; 138 139 if (cfg->xtal_freq != QM1D1C0042_CFG_XTAL_DFLT) 140 dev_warn(&state->i2c->dev, 141 "(%s) changing xtal_freq not supported. ", __func__); 142 state->cfg.xtal_freq = default_cfg.xtal_freq; 143 144 state->cfg.lpf = cfg->lpf; 145 state->cfg.fast_srch = cfg->fast_srch; 146 147 if (cfg->lpf_wait != QM1D1C0042_CFG_WAIT_DFLT) 148 state->cfg.lpf_wait = cfg->lpf_wait; 149 else 150 state->cfg.lpf_wait = default_cfg.lpf_wait; 151 152 if (cfg->fast_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) 153 state->cfg.fast_srch_wait = cfg->fast_srch_wait; 154 else 155 state->cfg.fast_srch_wait = default_cfg.fast_srch_wait; 156 157 if (cfg->normal_srch_wait != QM1D1C0042_CFG_WAIT_DFLT) 158 state->cfg.normal_srch_wait = cfg->normal_srch_wait; 159 else 160 state->cfg.normal_srch_wait = default_cfg.normal_srch_wait; 161 return 0; 162 } 163 164 /* divisor, vco_band parameters */ 165 /* {maxfreq, param1(band?), param2(div?) */ 166 static const u32 conv_table[9][3] = { 167 { 2151000, 1, 7 }, 168 { 1950000, 1, 6 }, 169 { 1800000, 1, 5 }, 170 { 1600000, 1, 4 }, 171 { 1450000, 1, 3 }, 172 { 1250000, 1, 2 }, 173 { 1200000, 0, 7 }, 174 { 975000, 0, 6 }, 175 { 950000, 0, 0 } 176 }; 177 178 static int qm1d1c0042_set_params(struct dvb_frontend *fe) 179 { 180 struct qm1d1c0042_state *state; 181 u32 freq; 182 int i, ret; 183 u8 val, mask; 184 u32 a, sd; 185 s32 b; 186 187 state = fe->tuner_priv; 188 freq = fe->dtv_property_cache.frequency; 189 190 state->regs[0x08] &= 0xf0; 191 state->regs[0x08] |= 0x09; 192 193 state->regs[0x13] &= 0x9f; 194 state->regs[0x13] |= 0x20; 195 196 /* div2/vco_band */ 197 val = state->regs[0x02] & 0x0f; 198 for (i = 0; i < 8; i++) 199 if (freq < conv_table[i][0] && freq >= conv_table[i + 1][0]) { 200 val |= conv_table[i][1] << 7; 201 val |= conv_table[i][2] << 4; 202 break; 203 } 204 ret = reg_write(state, 0x02, val); 205 if (ret < 0) 206 return ret; 207 208 a = (freq + state->cfg.xtal_freq / 2) / state->cfg.xtal_freq; 209 210 state->regs[0x06] &= 0x40; 211 state->regs[0x06] |= (a - 12) / 4; 212 ret = reg_write(state, 0x06, state->regs[0x06]); 213 if (ret < 0) 214 return ret; 215 216 state->regs[0x07] &= 0xf0; 217 state->regs[0x07] |= (a - 4 * ((a - 12) / 4 + 1) - 5) & 0x0f; 218 ret = reg_write(state, 0x07, state->regs[0x07]); 219 if (ret < 0) 220 return ret; 221 222 /* LPF */ 223 val = state->regs[0x08]; 224 if (state->cfg.lpf) { 225 /* LPF_CLK, LPF_FC */ 226 val &= 0xf0; 227 val |= 0x02; 228 } 229 ret = reg_write(state, 0x08, val); 230 if (ret < 0) 231 return ret; 232 233 /* 234 * b = (freq / state->cfg.xtal_freq - a) << 20; 235 * sd = b (b >= 0) 236 * 1<<22 + b (b < 0) 237 */ 238 b = (s32)div64_s64(((s64) freq) << 20, state->cfg.xtal_freq) 239 - (((s64) a) << 20); 240 241 if (b >= 0) 242 sd = b; 243 else 244 sd = (1 << 22) + b; 245 246 state->regs[0x09] &= 0xc0; 247 state->regs[0x09] |= (sd >> 16) & 0x3f; 248 state->regs[0x0a] = (sd >> 8) & 0xff; 249 state->regs[0x0b] = sd & 0xff; 250 ret = reg_write(state, 0x09, state->regs[0x09]); 251 if (ret == 0) 252 ret = reg_write(state, 0x0a, state->regs[0x0a]); 253 if (ret == 0) 254 ret = reg_write(state, 0x0b, state->regs[0x0b]); 255 if (ret != 0) 256 return ret; 257 258 if (!state->cfg.lpf) { 259 /* CSEL_Offset */ 260 ret = reg_write(state, 0x13, state->regs[0x13]); 261 if (ret < 0) 262 return ret; 263 } 264 265 /* VCO_TM, LPF_TM */ 266 mask = state->cfg.lpf ? 0x3f : 0x7f; 267 val = state->regs[0x0c] & mask; 268 ret = reg_write(state, 0x0c, val); 269 if (ret < 0) 270 return ret; 271 usleep_range(2000, 3000); 272 val = state->regs[0x0c] | ~mask; 273 ret = reg_write(state, 0x0c, val); 274 if (ret < 0) 275 return ret; 276 277 if (state->cfg.lpf) 278 msleep(state->cfg.lpf_wait); 279 else if (state->regs[0x03] & 0x01) 280 msleep(state->cfg.fast_srch_wait); 281 else 282 msleep(state->cfg.normal_srch_wait); 283 284 if (state->cfg.lpf) { 285 /* LPF_FC */ 286 ret = reg_write(state, 0x08, 0x09); 287 if (ret < 0) 288 return ret; 289 290 /* CSEL_Offset */ 291 ret = reg_write(state, 0x13, state->regs[0x13]); 292 if (ret < 0) 293 return ret; 294 } 295 return 0; 296 } 297 298 static int qm1d1c0042_sleep(struct dvb_frontend *fe) 299 { 300 struct qm1d1c0042_state *state; 301 int ret; 302 303 state = fe->tuner_priv; 304 state->regs[0x01] &= (~(1 << 3)) & 0xff; /* BB_Reg_disable */ 305 state->regs[0x01] |= 1 << 0; /* STDBY */ 306 state->regs[0x05] |= 1 << 3; /* pfd_rst STANDBY */ 307 ret = reg_write(state, 0x05, state->regs[0x05]); 308 if (ret == 0) 309 ret = reg_write(state, 0x01, state->regs[0x01]); 310 if (ret < 0) 311 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 312 __func__, fe->dvb->num, fe->id); 313 return ret; 314 } 315 316 static int qm1d1c0042_init(struct dvb_frontend *fe) 317 { 318 struct qm1d1c0042_state *state; 319 u8 val; 320 int i, ret; 321 322 state = fe->tuner_priv; 323 memcpy(state->regs, reg_initval, sizeof(reg_initval)); 324 325 reg_write(state, 0x01, 0x0c); 326 reg_write(state, 0x01, 0x0c); 327 328 ret = reg_write(state, 0x01, 0x0c); /* soft reset on */ 329 if (ret < 0) 330 goto failed; 331 usleep_range(2000, 3000); 332 333 val = state->regs[0x01] | 0x10; 334 ret = reg_write(state, 0x01, val); /* soft reset off */ 335 if (ret < 0) 336 goto failed; 337 338 /* check ID */ 339 ret = reg_read(state, 0x00, &val); 340 if (ret < 0 || val != 0x48) 341 goto failed; 342 usleep_range(2000, 3000); 343 344 state->regs[0x0c] |= 0x40; 345 ret = reg_write(state, 0x0c, state->regs[0x0c]); 346 if (ret < 0) 347 goto failed; 348 msleep(state->cfg.lpf_wait); 349 350 /* set all writable registers */ 351 for (i = 1; i <= 0x0c ; i++) { 352 ret = reg_write(state, i, state->regs[i]); 353 if (ret < 0) 354 goto failed; 355 } 356 for (i = 0x11; i < QM1D1C0042_NUM_REGS; i++) { 357 ret = reg_write(state, i, state->regs[i]); 358 if (ret < 0) 359 goto failed; 360 } 361 362 ret = qm1d1c0042_wakeup(state); 363 if (ret < 0) 364 goto failed; 365 366 ret = qm1d1c0042_set_srch_mode(state, state->cfg.fast_srch); 367 if (ret < 0) 368 goto failed; 369 370 return ret; 371 372 failed: 373 dev_warn(&state->i2c->dev, "(%s) failed. [adap%d-fe%d]\n", 374 __func__, fe->dvb->num, fe->id); 375 return ret; 376 } 377 378 /* I2C driver functions */ 379 380 static const struct dvb_tuner_ops qm1d1c0042_ops = { 381 .info = { 382 .name = "Sharp QM1D1C0042", 383 384 .frequency_min = 950000, 385 .frequency_max = 2150000, 386 }, 387 388 .init = qm1d1c0042_init, 389 .sleep = qm1d1c0042_sleep, 390 .set_config = qm1d1c0042_set_config, 391 .set_params = qm1d1c0042_set_params, 392 }; 393 394 395 static int qm1d1c0042_probe(struct i2c_client *client, 396 const struct i2c_device_id *id) 397 { 398 struct qm1d1c0042_state *state; 399 struct qm1d1c0042_config *cfg; 400 struct dvb_frontend *fe; 401 402 state = kzalloc(sizeof(*state), GFP_KERNEL); 403 if (!state) 404 return -ENOMEM; 405 state->i2c = client; 406 407 cfg = client->dev.platform_data; 408 fe = cfg->fe; 409 fe->tuner_priv = state; 410 qm1d1c0042_set_config(fe, cfg); 411 memcpy(&fe->ops.tuner_ops, &qm1d1c0042_ops, sizeof(qm1d1c0042_ops)); 412 413 i2c_set_clientdata(client, &state->cfg); 414 dev_info(&client->dev, "Sharp QM1D1C0042 attached.\n"); 415 return 0; 416 } 417 418 static int qm1d1c0042_remove(struct i2c_client *client) 419 { 420 struct qm1d1c0042_state *state; 421 422 state = cfg_to_state(i2c_get_clientdata(client)); 423 state->cfg.fe->tuner_priv = NULL; 424 kfree(state); 425 return 0; 426 } 427 428 429 static const struct i2c_device_id qm1d1c0042_id[] = { 430 {"qm1d1c0042", 0}, 431 {} 432 }; 433 MODULE_DEVICE_TABLE(i2c, qm1d1c0042_id); 434 435 static struct i2c_driver qm1d1c0042_driver = { 436 .driver = { 437 .name = "qm1d1c0042", 438 }, 439 .probe = qm1d1c0042_probe, 440 .remove = qm1d1c0042_remove, 441 .id_table = qm1d1c0042_id, 442 }; 443 444 module_i2c_driver(qm1d1c0042_driver); 445 446 MODULE_DESCRIPTION("Sharp QM1D1C0042 tuner"); 447 MODULE_AUTHOR("Akihiro TSUKADA"); 448 MODULE_LICENSE("GPL"); 449