1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * GS1662 device registration. 4 * 5 * Copyright (C) 2015-2016 Nexvision 6 * Author: Charles-Antoine Couret <charles-antoine.couret@nexvision.fr> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/init.h> 11 #include <linux/spi/spi.h> 12 #include <linux/platform_device.h> 13 #include <linux/ctype.h> 14 #include <linux/err.h> 15 #include <linux/device.h> 16 #include <linux/module.h> 17 18 #include <linux/videodev2.h> 19 #include <media/v4l2-common.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-subdev.h> 23 #include <media/v4l2-dv-timings.h> 24 #include <linux/v4l2-dv-timings.h> 25 26 #define REG_STATUS 0x04 27 #define REG_FORCE_FMT 0x06 28 #define REG_LINES_PER_FRAME 0x12 29 #define REG_WORDS_PER_LINE 0x13 30 #define REG_WORDS_PER_ACT_LINE 0x14 31 #define REG_ACT_LINES_PER_FRAME 0x15 32 33 #define MASK_H_LOCK 0x001 34 #define MASK_V_LOCK 0x002 35 #define MASK_STD_LOCK 0x004 36 #define MASK_FORCE_STD 0x020 37 #define MASK_STD_STATUS 0x3E0 38 39 #define GS_WIDTH_MIN 720 40 #define GS_WIDTH_MAX 2048 41 #define GS_HEIGHT_MIN 487 42 #define GS_HEIGHT_MAX 1080 43 #define GS_PIXELCLOCK_MIN 10519200 44 #define GS_PIXELCLOCK_MAX 74250000 45 46 struct gs { 47 struct spi_device *pdev; 48 struct v4l2_subdev sd; 49 struct v4l2_dv_timings current_timings; 50 int enabled; 51 }; 52 53 struct gs_reg_fmt { 54 u16 reg_value; 55 struct v4l2_dv_timings format; 56 }; 57 58 struct gs_reg_fmt_custom { 59 u16 reg_value; 60 __u32 width; 61 __u32 height; 62 __u64 pixelclock; 63 __u32 interlaced; 64 }; 65 66 static const struct spi_device_id gs_id[] = { 67 { "gs1662", 0 }, 68 { } 69 }; 70 MODULE_DEVICE_TABLE(spi, gs_id); 71 72 static const struct v4l2_dv_timings fmt_cap[] = { 73 V4L2_DV_BT_SDI_720X487I60, 74 V4L2_DV_BT_CEA_720X576P50, 75 V4L2_DV_BT_CEA_1280X720P24, 76 V4L2_DV_BT_CEA_1280X720P25, 77 V4L2_DV_BT_CEA_1280X720P30, 78 V4L2_DV_BT_CEA_1280X720P50, 79 V4L2_DV_BT_CEA_1280X720P60, 80 V4L2_DV_BT_CEA_1920X1080P24, 81 V4L2_DV_BT_CEA_1920X1080P25, 82 V4L2_DV_BT_CEA_1920X1080P30, 83 V4L2_DV_BT_CEA_1920X1080I50, 84 V4L2_DV_BT_CEA_1920X1080I60, 85 }; 86 87 static const struct gs_reg_fmt reg_fmt[] = { 88 { 0x00, V4L2_DV_BT_CEA_1280X720P60 }, 89 { 0x01, V4L2_DV_BT_CEA_1280X720P60 }, 90 { 0x02, V4L2_DV_BT_CEA_1280X720P30 }, 91 { 0x03, V4L2_DV_BT_CEA_1280X720P30 }, 92 { 0x04, V4L2_DV_BT_CEA_1280X720P50 }, 93 { 0x05, V4L2_DV_BT_CEA_1280X720P50 }, 94 { 0x06, V4L2_DV_BT_CEA_1280X720P25 }, 95 { 0x07, V4L2_DV_BT_CEA_1280X720P25 }, 96 { 0x08, V4L2_DV_BT_CEA_1280X720P24 }, 97 { 0x09, V4L2_DV_BT_CEA_1280X720P24 }, 98 { 0x0A, V4L2_DV_BT_CEA_1920X1080I60 }, 99 { 0x0B, V4L2_DV_BT_CEA_1920X1080P30 }, 100 101 /* Default value: keep this field before 0xC */ 102 { 0x14, V4L2_DV_BT_CEA_1920X1080I50 }, 103 { 0x0C, V4L2_DV_BT_CEA_1920X1080I50 }, 104 { 0x0D, V4L2_DV_BT_CEA_1920X1080P25 }, 105 { 0x0E, V4L2_DV_BT_CEA_1920X1080P25 }, 106 { 0x10, V4L2_DV_BT_CEA_1920X1080P24 }, 107 { 0x12, V4L2_DV_BT_CEA_1920X1080P24 }, 108 { 0x16, V4L2_DV_BT_SDI_720X487I60 }, 109 { 0x19, V4L2_DV_BT_SDI_720X487I60 }, 110 { 0x18, V4L2_DV_BT_CEA_720X576P50 }, 111 { 0x1A, V4L2_DV_BT_CEA_720X576P50 }, 112 113 /* Implement following timings before enable it. 114 * Because of we don't have access to these theoretical timings yet. 115 * Workaround: use functions to get and set registers for these formats. 116 */ 117 #if 0 118 { 0x0F, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ 119 { 0x11, V4L2_DV_BT_XXX_1920X1080I24 }, /* SMPTE 274M */ 120 { 0x13, V4L2_DV_BT_XXX_1920X1080I25 }, /* SMPTE 274M */ 121 { 0x15, V4L2_DV_BT_XXX_1920X1035I60 }, /* SMPTE 260M */ 122 { 0x17, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ 123 { 0x1B, V4L2_DV_BT_SDI_720X507I60 }, /* SMPTE 125M */ 124 { 0x1C, V4L2_DV_BT_XXX_2048X1080P25 }, /* SMPTE 428.1M */ 125 #endif 126 }; 127 128 static const struct v4l2_dv_timings_cap gs_timings_cap = { 129 .type = V4L2_DV_BT_656_1120, 130 /* keep this initialization for compatibility with GCC < 4.4.6 */ 131 .reserved = { 0 }, 132 V4L2_INIT_BT_TIMINGS(GS_WIDTH_MIN, GS_WIDTH_MAX, GS_HEIGHT_MIN, 133 GS_HEIGHT_MAX, GS_PIXELCLOCK_MIN, 134 GS_PIXELCLOCK_MAX, 135 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_SDI, 136 V4L2_DV_BT_CAP_PROGRESSIVE 137 | V4L2_DV_BT_CAP_INTERLACED) 138 }; 139 140 static int gs_read_register(struct spi_device *spi, u16 addr, u16 *value) 141 { 142 int ret; 143 u16 buf_addr = (0x8000 | (0x0FFF & addr)); 144 u16 buf_value = 0; 145 struct spi_message msg; 146 struct spi_transfer tx[] = { 147 { 148 .tx_buf = &buf_addr, 149 .len = 2, 150 .delay = { 151 .value = 1, 152 .unit = SPI_DELAY_UNIT_USECS 153 }, 154 }, { 155 .rx_buf = &buf_value, 156 .len = 2, 157 .delay = { 158 .value = 1, 159 .unit = SPI_DELAY_UNIT_USECS 160 }, 161 }, 162 }; 163 164 spi_message_init(&msg); 165 spi_message_add_tail(&tx[0], &msg); 166 spi_message_add_tail(&tx[1], &msg); 167 ret = spi_sync(spi, &msg); 168 169 *value = buf_value; 170 171 return ret; 172 } 173 174 static int gs_write_register(struct spi_device *spi, u16 addr, u16 value) 175 { 176 int ret; 177 u16 buf_addr = addr; 178 u16 buf_value = value; 179 struct spi_message msg; 180 struct spi_transfer tx[] = { 181 { 182 .tx_buf = &buf_addr, 183 .len = 2, 184 .delay = { 185 .value = 1, 186 .unit = SPI_DELAY_UNIT_USECS 187 }, 188 }, { 189 .tx_buf = &buf_value, 190 .len = 2, 191 .delay = { 192 .value = 1, 193 .unit = SPI_DELAY_UNIT_USECS 194 }, 195 }, 196 }; 197 198 spi_message_init(&msg); 199 spi_message_add_tail(&tx[0], &msg); 200 spi_message_add_tail(&tx[1], &msg); 201 ret = spi_sync(spi, &msg); 202 203 return ret; 204 } 205 206 #ifdef CONFIG_VIDEO_ADV_DEBUG 207 static int gs_g_register(struct v4l2_subdev *sd, 208 struct v4l2_dbg_register *reg) 209 { 210 struct spi_device *spi = v4l2_get_subdevdata(sd); 211 u16 val; 212 int ret; 213 214 ret = gs_read_register(spi, reg->reg & 0xFFFF, &val); 215 reg->val = val; 216 reg->size = 2; 217 return ret; 218 } 219 220 static int gs_s_register(struct v4l2_subdev *sd, 221 const struct v4l2_dbg_register *reg) 222 { 223 struct spi_device *spi = v4l2_get_subdevdata(sd); 224 225 return gs_write_register(spi, reg->reg & 0xFFFF, reg->val & 0xFFFF); 226 } 227 #endif 228 229 static int gs_status_format(u16 status, struct v4l2_dv_timings *timings) 230 { 231 int std = (status & MASK_STD_STATUS) >> 5; 232 int i; 233 234 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { 235 if (reg_fmt[i].reg_value == std) { 236 *timings = reg_fmt[i].format; 237 return 0; 238 } 239 } 240 241 return -ERANGE; 242 } 243 244 static u16 get_register_timings(struct v4l2_dv_timings *timings) 245 { 246 int i; 247 248 for (i = 0; i < ARRAY_SIZE(reg_fmt); i++) { 249 if (v4l2_match_dv_timings(timings, ®_fmt[i].format, 0, 250 false)) 251 return reg_fmt[i].reg_value | MASK_FORCE_STD; 252 } 253 254 return 0x0; 255 } 256 257 static inline struct gs *to_gs(struct v4l2_subdev *sd) 258 { 259 return container_of(sd, struct gs, sd); 260 } 261 262 static int gs_s_dv_timings(struct v4l2_subdev *sd, 263 struct v4l2_dv_timings *timings) 264 { 265 struct gs *gs = to_gs(sd); 266 int reg_value; 267 268 reg_value = get_register_timings(timings); 269 if (reg_value == 0x0) 270 return -EINVAL; 271 272 gs->current_timings = *timings; 273 return 0; 274 } 275 276 static int gs_g_dv_timings(struct v4l2_subdev *sd, 277 struct v4l2_dv_timings *timings) 278 { 279 struct gs *gs = to_gs(sd); 280 281 *timings = gs->current_timings; 282 return 0; 283 } 284 285 static int gs_query_dv_timings(struct v4l2_subdev *sd, 286 struct v4l2_dv_timings *timings) 287 { 288 struct gs *gs = to_gs(sd); 289 struct v4l2_dv_timings fmt; 290 u16 reg_value, i; 291 int ret; 292 293 if (gs->enabled) 294 return -EBUSY; 295 296 /* 297 * Check if the component detect a line, a frame or something else 298 * which looks like a video signal activity. 299 */ 300 for (i = 0; i < 4; i++) { 301 gs_read_register(gs->pdev, REG_LINES_PER_FRAME + i, ®_value); 302 if (reg_value) 303 break; 304 } 305 306 /* If no register reports a video signal */ 307 if (i >= 4) 308 return -ENOLINK; 309 310 gs_read_register(gs->pdev, REG_STATUS, ®_value); 311 if (!(reg_value & MASK_H_LOCK) || !(reg_value & MASK_V_LOCK)) 312 return -ENOLCK; 313 if (!(reg_value & MASK_STD_LOCK)) 314 return -ERANGE; 315 316 ret = gs_status_format(reg_value, &fmt); 317 318 if (ret < 0) 319 return ret; 320 321 *timings = fmt; 322 return 0; 323 } 324 325 static int gs_enum_dv_timings(struct v4l2_subdev *sd, 326 struct v4l2_enum_dv_timings *timings) 327 { 328 if (timings->index >= ARRAY_SIZE(fmt_cap)) 329 return -EINVAL; 330 331 if (timings->pad != 0) 332 return -EINVAL; 333 334 timings->timings = fmt_cap[timings->index]; 335 return 0; 336 } 337 338 static int gs_s_stream(struct v4l2_subdev *sd, int enable) 339 { 340 struct gs *gs = to_gs(sd); 341 int reg_value; 342 343 if (gs->enabled == enable) 344 return 0; 345 346 gs->enabled = enable; 347 348 if (enable) { 349 /* To force the specific format */ 350 reg_value = get_register_timings(&gs->current_timings); 351 return gs_write_register(gs->pdev, REG_FORCE_FMT, reg_value); 352 } 353 354 /* To renable auto-detection mode */ 355 return gs_write_register(gs->pdev, REG_FORCE_FMT, 0x0); 356 } 357 358 static int gs_g_input_status(struct v4l2_subdev *sd, u32 *status) 359 { 360 struct gs *gs = to_gs(sd); 361 u16 reg_value, i; 362 int ret; 363 364 /* 365 * Check if the component detect a line, a frame or something else 366 * which looks like a video signal activity. 367 */ 368 for (i = 0; i < 4; i++) { 369 ret = gs_read_register(gs->pdev, 370 REG_LINES_PER_FRAME + i, ®_value); 371 if (reg_value) 372 break; 373 if (ret) { 374 *status = V4L2_IN_ST_NO_POWER; 375 return ret; 376 } 377 } 378 379 /* If no register reports a video signal */ 380 if (i >= 4) 381 *status |= V4L2_IN_ST_NO_SIGNAL; 382 383 ret = gs_read_register(gs->pdev, REG_STATUS, ®_value); 384 if (!(reg_value & MASK_H_LOCK)) 385 *status |= V4L2_IN_ST_NO_H_LOCK; 386 if (!(reg_value & MASK_V_LOCK)) 387 *status |= V4L2_IN_ST_NO_V_LOCK; 388 if (!(reg_value & MASK_STD_LOCK)) 389 *status |= V4L2_IN_ST_NO_STD_LOCK; 390 391 return ret; 392 } 393 394 static int gs_dv_timings_cap(struct v4l2_subdev *sd, 395 struct v4l2_dv_timings_cap *cap) 396 { 397 if (cap->pad != 0) 398 return -EINVAL; 399 400 *cap = gs_timings_cap; 401 return 0; 402 } 403 404 /* V4L2 core operation handlers */ 405 static const struct v4l2_subdev_core_ops gs_core_ops = { 406 #ifdef CONFIG_VIDEO_ADV_DEBUG 407 .g_register = gs_g_register, 408 .s_register = gs_s_register, 409 #endif 410 }; 411 412 static const struct v4l2_subdev_video_ops gs_video_ops = { 413 .s_dv_timings = gs_s_dv_timings, 414 .g_dv_timings = gs_g_dv_timings, 415 .s_stream = gs_s_stream, 416 .g_input_status = gs_g_input_status, 417 .query_dv_timings = gs_query_dv_timings, 418 }; 419 420 static const struct v4l2_subdev_pad_ops gs_pad_ops = { 421 .enum_dv_timings = gs_enum_dv_timings, 422 .dv_timings_cap = gs_dv_timings_cap, 423 }; 424 425 /* V4L2 top level operation handlers */ 426 static const struct v4l2_subdev_ops gs_ops = { 427 .core = &gs_core_ops, 428 .video = &gs_video_ops, 429 .pad = &gs_pad_ops, 430 }; 431 432 static int gs_probe(struct spi_device *spi) 433 { 434 int ret; 435 struct gs *gs; 436 struct v4l2_subdev *sd; 437 438 gs = devm_kzalloc(&spi->dev, sizeof(struct gs), GFP_KERNEL); 439 if (!gs) 440 return -ENOMEM; 441 442 gs->pdev = spi; 443 sd = &gs->sd; 444 445 spi->mode = SPI_MODE_0; 446 spi->irq = -1; 447 spi->max_speed_hz = 10000000; 448 spi->bits_per_word = 16; 449 ret = spi_setup(spi); 450 v4l2_spi_subdev_init(sd, spi, &gs_ops); 451 452 gs->current_timings = reg_fmt[0].format; 453 gs->enabled = 0; 454 455 /* Set H_CONFIG to SMPTE timings */ 456 gs_write_register(spi, 0x0, 0x300); 457 458 return ret; 459 } 460 461 static int gs_remove(struct spi_device *spi) 462 { 463 struct v4l2_subdev *sd = spi_get_drvdata(spi); 464 465 v4l2_device_unregister_subdev(sd); 466 467 return 0; 468 } 469 470 static struct spi_driver gs_driver = { 471 .driver = { 472 .name = "gs1662", 473 }, 474 475 .probe = gs_probe, 476 .remove = gs_remove, 477 .id_table = gs_id, 478 }; 479 480 module_spi_driver(gs_driver); 481 482 MODULE_LICENSE("GPL"); 483 MODULE_AUTHOR("Charles-Antoine Couret <charles-antoine.couret@nexvision.fr>"); 484 MODULE_DESCRIPTION("Gennum GS1662 HD/SD-SDI Serializer driver"); 485