1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2013 STMicroelectronics Limited 4 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> 5 */ 6 #include <linux/kernel.h> 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/platform_device.h> 12 #include <linux/reset.h> 13 #include <media/rc-core.h> 14 #include <linux/pinctrl/consumer.h> 15 #include <linux/pm_wakeirq.h> 16 17 struct st_rc_device { 18 struct device *dev; 19 int irq; 20 int irq_wake; 21 struct clk *sys_clock; 22 void __iomem *base; /* Register base address */ 23 void __iomem *rx_base;/* RX Register base address */ 24 struct rc_dev *rdev; 25 bool overclocking; 26 int sample_mult; 27 int sample_div; 28 bool rxuhfmode; 29 struct reset_control *rstc; 30 }; 31 32 /* Registers */ 33 #define IRB_SAMPLE_RATE_COMM 0x64 /* sample freq divisor*/ 34 #define IRB_CLOCK_SEL 0x70 /* clock select */ 35 #define IRB_CLOCK_SEL_STATUS 0x74 /* clock status */ 36 /* IRB IR/UHF receiver registers */ 37 #define IRB_RX_ON 0x40 /* pulse time capture */ 38 #define IRB_RX_SYS 0X44 /* sym period capture */ 39 #define IRB_RX_INT_EN 0x48 /* IRQ enable (R/W) */ 40 #define IRB_RX_INT_STATUS 0x4c /* IRQ status (R/W) */ 41 #define IRB_RX_EN 0x50 /* Receive enable */ 42 #define IRB_MAX_SYM_PERIOD 0x54 /* max sym value */ 43 #define IRB_RX_INT_CLEAR 0x58 /* overrun status */ 44 #define IRB_RX_STATUS 0x6c /* receive status */ 45 #define IRB_RX_NOISE_SUPPR 0x5c /* noise suppression */ 46 #define IRB_RX_POLARITY_INV 0x68 /* polarity inverter */ 47 48 /* 49 * IRQ set: Enable full FIFO 1 -> bit 3; 50 * Enable overrun IRQ 1 -> bit 2; 51 * Enable last symbol IRQ 1 -> bit 1: 52 * Enable RX interrupt 1 -> bit 0; 53 */ 54 #define IRB_RX_INTS 0x0f 55 #define IRB_RX_OVERRUN_INT 0x04 56 /* maximum symbol period (microsecs),timeout to detect end of symbol train */ 57 #define MAX_SYMB_TIME 0x5000 58 #define IRB_SAMPLE_FREQ 10000000 59 #define IRB_FIFO_NOT_EMPTY 0xff00 60 #define IRB_OVERFLOW 0x4 61 #define IRB_TIMEOUT 0xffff 62 #define IR_ST_NAME "st-rc" 63 64 static void st_rc_send_lirc_timeout(struct rc_dev *rdev) 65 { 66 struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout }; 67 ir_raw_event_store(rdev, &ev); 68 } 69 70 /* 71 * RX graphical example to better understand the difference between ST IR block 72 * output and standard definition used by LIRC (and most of the world!) 73 * 74 * mark mark 75 * |-IRB_RX_ON-| |-IRB_RX_ON-| 76 * ___ ___ ___ ___ ___ ___ _ 77 * | | | | | | | | | | | | | 78 * | | | | | | space 0 | | | | | | space 1 | 79 * _____| |__| |__| |____________________________| |__| |__| |_____________| 80 * 81 * |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------| 82 * 83 * |------------- encoding bit 0 -----------|---- encoding bit 1 -----| 84 * 85 * ST hardware returns mark (IRB_RX_ON) and total symbol time (IRB_RX_SYS), so 86 * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark) 87 * The mark time represents the amount of time the carrier (usually 36-40kHz) 88 * is detected.The above examples shows Pulse Width Modulation encoding where 89 * bit 0 is represented by space>mark. 90 */ 91 92 static irqreturn_t st_rc_rx_interrupt(int irq, void *data) 93 { 94 unsigned long timeout; 95 unsigned int symbol, mark = 0; 96 struct st_rc_device *dev = data; 97 int last_symbol = 0; 98 u32 status, int_status; 99 struct ir_raw_event ev = {}; 100 101 if (dev->irq_wake) 102 pm_wakeup_event(dev->dev, 0); 103 104 /* FIXME: is 10ms good enough ? */ 105 timeout = jiffies + msecs_to_jiffies(10); 106 do { 107 status = readl(dev->rx_base + IRB_RX_STATUS); 108 if (!(status & (IRB_FIFO_NOT_EMPTY | IRB_OVERFLOW))) 109 break; 110 111 int_status = readl(dev->rx_base + IRB_RX_INT_STATUS); 112 if (unlikely(int_status & IRB_RX_OVERRUN_INT)) { 113 /* discard the entire collection in case of errors! */ 114 ir_raw_event_reset(dev->rdev); 115 dev_info(dev->dev, "IR RX overrun\n"); 116 writel(IRB_RX_OVERRUN_INT, 117 dev->rx_base + IRB_RX_INT_CLEAR); 118 continue; 119 } 120 121 symbol = readl(dev->rx_base + IRB_RX_SYS); 122 mark = readl(dev->rx_base + IRB_RX_ON); 123 124 if (symbol == IRB_TIMEOUT) 125 last_symbol = 1; 126 127 /* Ignore any noise */ 128 if ((mark > 2) && (symbol > 1)) { 129 symbol -= mark; 130 if (dev->overclocking) { /* adjustments to timings */ 131 symbol *= dev->sample_mult; 132 symbol /= dev->sample_div; 133 mark *= dev->sample_mult; 134 mark /= dev->sample_div; 135 } 136 137 ev.duration = mark; 138 ev.pulse = true; 139 ir_raw_event_store(dev->rdev, &ev); 140 141 if (!last_symbol) { 142 ev.duration = symbol; 143 ev.pulse = false; 144 ir_raw_event_store(dev->rdev, &ev); 145 } else { 146 st_rc_send_lirc_timeout(dev->rdev); 147 } 148 149 } 150 last_symbol = 0; 151 } while (time_is_after_jiffies(timeout)); 152 153 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); 154 155 /* Empty software fifo */ 156 ir_raw_event_handle(dev->rdev); 157 return IRQ_HANDLED; 158 } 159 160 static int st_rc_hardware_init(struct st_rc_device *dev) 161 { 162 int ret; 163 int baseclock, freqdiff; 164 unsigned int rx_max_symbol_per = MAX_SYMB_TIME; 165 unsigned int rx_sampling_freq_div; 166 167 /* Enable the IP */ 168 reset_control_deassert(dev->rstc); 169 170 ret = clk_prepare_enable(dev->sys_clock); 171 if (ret) { 172 dev_err(dev->dev, "Failed to prepare/enable system clock\n"); 173 return ret; 174 } 175 176 baseclock = clk_get_rate(dev->sys_clock); 177 178 /* IRB input pins are inverted internally from high to low. */ 179 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); 180 181 rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ; 182 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); 183 184 freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ); 185 if (freqdiff) { /* over clocking, workout the adjustment factors */ 186 dev->overclocking = true; 187 dev->sample_mult = 1000; 188 dev->sample_div = baseclock / (10000 * rx_sampling_freq_div); 189 rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div; 190 } 191 192 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); 193 194 return 0; 195 } 196 197 static int st_rc_remove(struct platform_device *pdev) 198 { 199 struct st_rc_device *rc_dev = platform_get_drvdata(pdev); 200 201 dev_pm_clear_wake_irq(&pdev->dev); 202 device_init_wakeup(&pdev->dev, false); 203 clk_disable_unprepare(rc_dev->sys_clock); 204 rc_unregister_device(rc_dev->rdev); 205 return 0; 206 } 207 208 static int st_rc_open(struct rc_dev *rdev) 209 { 210 struct st_rc_device *dev = rdev->priv; 211 unsigned long flags; 212 local_irq_save(flags); 213 /* enable interrupts and receiver */ 214 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); 215 writel(0x01, dev->rx_base + IRB_RX_EN); 216 local_irq_restore(flags); 217 218 return 0; 219 } 220 221 static void st_rc_close(struct rc_dev *rdev) 222 { 223 struct st_rc_device *dev = rdev->priv; 224 /* disable interrupts and receiver */ 225 writel(0x00, dev->rx_base + IRB_RX_EN); 226 writel(0x00, dev->rx_base + IRB_RX_INT_EN); 227 } 228 229 static int st_rc_probe(struct platform_device *pdev) 230 { 231 int ret = -EINVAL; 232 struct rc_dev *rdev; 233 struct device *dev = &pdev->dev; 234 struct resource *res; 235 struct st_rc_device *rc_dev; 236 struct device_node *np = pdev->dev.of_node; 237 const char *rx_mode; 238 239 rc_dev = devm_kzalloc(dev, sizeof(struct st_rc_device), GFP_KERNEL); 240 241 if (!rc_dev) 242 return -ENOMEM; 243 244 rdev = rc_allocate_device(RC_DRIVER_IR_RAW); 245 246 if (!rdev) 247 return -ENOMEM; 248 249 if (np && !of_property_read_string(np, "rx-mode", &rx_mode)) { 250 251 if (!strcmp(rx_mode, "uhf")) { 252 rc_dev->rxuhfmode = true; 253 } else if (!strcmp(rx_mode, "infrared")) { 254 rc_dev->rxuhfmode = false; 255 } else { 256 dev_err(dev, "Unsupported rx mode [%s]\n", rx_mode); 257 goto err; 258 } 259 260 } else { 261 goto err; 262 } 263 264 rc_dev->sys_clock = devm_clk_get(dev, NULL); 265 if (IS_ERR(rc_dev->sys_clock)) { 266 dev_err(dev, "System clock not found\n"); 267 ret = PTR_ERR(rc_dev->sys_clock); 268 goto err; 269 } 270 271 rc_dev->irq = platform_get_irq(pdev, 0); 272 if (rc_dev->irq < 0) { 273 ret = rc_dev->irq; 274 goto err; 275 } 276 277 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 278 279 rc_dev->base = devm_ioremap_resource(dev, res); 280 if (IS_ERR(rc_dev->base)) { 281 ret = PTR_ERR(rc_dev->base); 282 goto err; 283 } 284 285 if (rc_dev->rxuhfmode) 286 rc_dev->rx_base = rc_dev->base + 0x40; 287 else 288 rc_dev->rx_base = rc_dev->base; 289 290 rc_dev->rstc = reset_control_get_optional_exclusive(dev, NULL); 291 if (IS_ERR(rc_dev->rstc)) { 292 ret = PTR_ERR(rc_dev->rstc); 293 goto err; 294 } 295 296 rc_dev->dev = dev; 297 platform_set_drvdata(pdev, rc_dev); 298 ret = st_rc_hardware_init(rc_dev); 299 if (ret) 300 goto err; 301 302 rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; 303 /* rx sampling rate is 10Mhz */ 304 rdev->rx_resolution = 100; 305 rdev->timeout = MAX_SYMB_TIME; 306 rdev->priv = rc_dev; 307 rdev->open = st_rc_open; 308 rdev->close = st_rc_close; 309 rdev->driver_name = IR_ST_NAME; 310 rdev->map_name = RC_MAP_EMPTY; 311 rdev->device_name = "ST Remote Control Receiver"; 312 313 ret = rc_register_device(rdev); 314 if (ret < 0) 315 goto clkerr; 316 317 rc_dev->rdev = rdev; 318 if (devm_request_irq(dev, rc_dev->irq, st_rc_rx_interrupt, 319 0, IR_ST_NAME, rc_dev) < 0) { 320 dev_err(dev, "IRQ %d register failed\n", rc_dev->irq); 321 ret = -EINVAL; 322 goto rcerr; 323 } 324 325 /* enable wake via this device */ 326 device_init_wakeup(dev, true); 327 dev_pm_set_wake_irq(dev, rc_dev->irq); 328 329 /* 330 * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW 331 * lircd expects a long space first before a signal train to sync. 332 */ 333 st_rc_send_lirc_timeout(rdev); 334 335 dev_info(dev, "setup in %s mode\n", rc_dev->rxuhfmode ? "UHF" : "IR"); 336 337 return ret; 338 rcerr: 339 rc_unregister_device(rdev); 340 rdev = NULL; 341 clkerr: 342 clk_disable_unprepare(rc_dev->sys_clock); 343 err: 344 rc_free_device(rdev); 345 dev_err(dev, "Unable to register device (%d)\n", ret); 346 return ret; 347 } 348 349 #ifdef CONFIG_PM_SLEEP 350 static int st_rc_suspend(struct device *dev) 351 { 352 struct st_rc_device *rc_dev = dev_get_drvdata(dev); 353 354 if (device_may_wakeup(dev)) { 355 if (!enable_irq_wake(rc_dev->irq)) 356 rc_dev->irq_wake = 1; 357 else 358 return -EINVAL; 359 } else { 360 pinctrl_pm_select_sleep_state(dev); 361 writel(0x00, rc_dev->rx_base + IRB_RX_EN); 362 writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN); 363 clk_disable_unprepare(rc_dev->sys_clock); 364 reset_control_assert(rc_dev->rstc); 365 } 366 367 return 0; 368 } 369 370 static int st_rc_resume(struct device *dev) 371 { 372 int ret; 373 struct st_rc_device *rc_dev = dev_get_drvdata(dev); 374 struct rc_dev *rdev = rc_dev->rdev; 375 376 if (rc_dev->irq_wake) { 377 disable_irq_wake(rc_dev->irq); 378 rc_dev->irq_wake = 0; 379 } else { 380 pinctrl_pm_select_default_state(dev); 381 ret = st_rc_hardware_init(rc_dev); 382 if (ret) 383 return ret; 384 385 if (rdev->users) { 386 writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN); 387 writel(0x01, rc_dev->rx_base + IRB_RX_EN); 388 } 389 } 390 391 return 0; 392 } 393 394 #endif 395 396 static SIMPLE_DEV_PM_OPS(st_rc_pm_ops, st_rc_suspend, st_rc_resume); 397 398 #ifdef CONFIG_OF 399 static const struct of_device_id st_rc_match[] = { 400 { .compatible = "st,comms-irb", }, 401 {}, 402 }; 403 404 MODULE_DEVICE_TABLE(of, st_rc_match); 405 #endif 406 407 static struct platform_driver st_rc_driver = { 408 .driver = { 409 .name = IR_ST_NAME, 410 .of_match_table = of_match_ptr(st_rc_match), 411 .pm = &st_rc_pm_ops, 412 }, 413 .probe = st_rc_probe, 414 .remove = st_rc_remove, 415 }; 416 417 module_platform_driver(st_rc_driver); 418 419 MODULE_DESCRIPTION("RC Transceiver driver for STMicroelectronics platforms"); 420 MODULE_AUTHOR("STMicroelectronics (R&D) Ltd"); 421 MODULE_LICENSE("GPL"); 422