xref: /linux/drivers/media/rc/ite-cir.h (revision 0ec694d6718a9fab0f49a280557feb257c9d7843)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
4  *
5  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
6  */
7 
8 /* platform driver name to register */
9 #define ITE_DRIVER_NAME "ite-cir"
10 
11 /* FIFO sizes */
12 #define ITE_TX_FIFO_LEN 32
13 #define ITE_RX_FIFO_LEN 32
14 
15 /* interrupt types */
16 #define ITE_IRQ_TX_FIFO        1
17 #define ITE_IRQ_RX_FIFO        2
18 #define ITE_IRQ_RX_FIFO_OVERRUN    4
19 
20 /* forward declaration */
21 struct ite_dev;
22 
23 /* struct for storing the parameters of different recognized devices */
24 struct ite_dev_params {
25 	/* model of the device */
26 	const char *model;
27 
28 	/* size of the I/O region */
29 	int io_region_size;
30 
31 	/* IR pnp I/O resource number */
32 	int io_rsrc_no;
33 
34 	/* hw-specific operation function pointers; most of these must be
35 	 * called while holding the spin lock, except for the TX FIFO length
36 	 * one */
37 	/* get pending interrupt causes */
38 	int (*get_irq_causes) (struct ite_dev *dev);
39 
40 	/* enable rx */
41 	void (*enable_rx) (struct ite_dev *dev);
42 
43 	/* make rx enter the idle state; keep listening for a pulse, but stop
44 	 * streaming space bytes */
45 	void (*idle_rx) (struct ite_dev *dev);
46 
47 	/* disable rx completely */
48 	void (*disable_rx) (struct ite_dev *dev);
49 
50 	/* read bytes from RX FIFO; return read count */
51 	int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size);
52 
53 	/* enable tx FIFO space available interrupt */
54 	void (*enable_tx_interrupt) (struct ite_dev *dev);
55 
56 	/* disable tx FIFO space available interrupt */
57 	void (*disable_tx_interrupt) (struct ite_dev *dev);
58 
59 	/* get number of full TX FIFO slots */
60 	int (*get_tx_used_slots) (struct ite_dev *dev);
61 
62 	/* put a byte to the TX FIFO */
63 	void (*put_tx_byte) (struct ite_dev *dev, u8 value);
64 
65 	/* disable hardware completely */
66 	void (*disable) (struct ite_dev *dev);
67 
68 	/* initialize the hardware */
69 	void (*init_hardware) (struct ite_dev *dev);
70 
71 	/* set the carrier parameters */
72 	void (*set_carrier_params) (struct ite_dev *dev, bool high_freq,
73 				    bool use_demodulator, u8 carrier_freq_bits,
74 				    u8 allowance_bits, u8 pulse_width_bits);
75 };
76 
77 /* ITE CIR device structure */
78 struct ite_dev {
79 	struct pnp_dev *pdev;
80 	struct rc_dev *rdev;
81 
82 	/* sync data */
83 	spinlock_t lock;
84 	bool transmitting;
85 
86 	/* transmit support */
87 	wait_queue_head_t tx_queue, tx_ended;
88 
89 	/* rx low carrier frequency, in Hz, 0 means no demodulation */
90 	unsigned int rx_low_carrier_freq;
91 
92 	/* tx high carrier frequency, in Hz, 0 means no demodulation */
93 	unsigned int rx_high_carrier_freq;
94 
95 	/* tx carrier frequency, in Hz */
96 	unsigned int tx_carrier_freq;
97 
98 	/* duty cycle, 0-100 */
99 	int tx_duty_cycle;
100 
101 	/* hardware I/O settings */
102 	unsigned long cir_addr;
103 	int cir_irq;
104 
105 	/* overridable copy of model parameters */
106 	const struct ite_dev_params *params;
107 };
108 
109 /* common values for all kinds of hardware */
110 
111 /* baud rate divisor default */
112 #define ITE_BAUDRATE_DIVISOR		1
113 
114 /* low-speed carrier frequency limits (Hz) */
115 #define ITE_LCF_MIN_CARRIER_FREQ	27000
116 #define ITE_LCF_MAX_CARRIER_FREQ	58000
117 
118 /* high-speed carrier frequency limits (Hz) */
119 #define ITE_HCF_MIN_CARRIER_FREQ	400000
120 #define ITE_HCF_MAX_CARRIER_FREQ	500000
121 
122 /* default carrier freq for when demodulator is off (Hz) */
123 #define ITE_DEFAULT_CARRIER_FREQ	38000
124 
125 /* convert bits to us */
126 #define ITE_BITS_TO_US(bits, sample_period) \
127 ((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000))
128 
129 /*
130  * n in RDCR produces a tolerance of +/- n * 6.25% around the center
131  * carrier frequency...
132  *
133  * From two limit frequencies, L (low) and H (high), we can get both the
134  * center frequency F = (L + H) / 2 and the variation from the center
135  * frequency A = (H - L) / (H + L). We can use this in order to honor the
136  * s_rx_carrier_range() call in ir-core. We'll suppose that any request
137  * setting L=0 means we must shut down the demodulator.
138  */
139 #define ITE_RXDCR_PER_10000_STEP 625
140 
141 /* high speed carrier freq values */
142 #define ITE_CFQ_400		0x03
143 #define ITE_CFQ_450		0x08
144 #define ITE_CFQ_480		0x0b
145 #define ITE_CFQ_500		0x0d
146 
147 /* values for pulse widths */
148 #define ITE_TXMPW_A		0x02
149 #define ITE_TXMPW_B		0x03
150 #define ITE_TXMPW_C		0x04
151 #define ITE_TXMPW_D		0x05
152 #define ITE_TXMPW_E		0x06
153 
154 /* values for demodulator carrier range allowance */
155 #define ITE_RXDCR_DEFAULT	0x01	/* default carrier range */
156 #define ITE_RXDCR_MAX		0x07	/* default carrier range */
157 
158 /* DR TX bits */
159 #define ITE_TX_PULSE		0x00
160 #define ITE_TX_SPACE		0x80
161 #define ITE_TX_MAX_RLE		0x80
162 #define ITE_TX_RLE_MASK		0x7f
163 
164 /*
165  * IT8712F
166  *
167  * hardware data obtained from:
168  *
169  * IT8712F
170  * Environment Control – Low Pin Count Input / Output
171  * (EC - LPC I/O)
172  * Preliminary Specification V0. 81
173  */
174 
175 /* register offsets */
176 #define IT87_DR		0x00	/* data register */
177 #define IT87_IER	0x01	/* interrupt enable register */
178 #define IT87_RCR	0x02	/* receiver control register */
179 #define IT87_TCR1	0x03	/* transmitter control register 1 */
180 #define IT87_TCR2	0x04	/* transmitter control register 2 */
181 #define IT87_TSR	0x05	/* transmitter status register */
182 #define IT87_RSR	0x06	/* receiver status register */
183 #define IT87_BDLR	0x05	/* baud rate divisor low byte register */
184 #define IT87_BDHR	0x06	/* baud rate divisor high byte register */
185 #define IT87_IIR	0x07	/* interrupt identification register */
186 
187 #define IT87_IOREG_LENGTH 0x08	/* length of register file */
188 
189 /* IER bits */
190 #define IT87_TLDLIE	0x01	/* transmitter low data interrupt enable */
191 #define IT87_RDAIE	0x02	/* receiver data available interrupt enable */
192 #define IT87_RFOIE	0x04	/* receiver FIFO overrun interrupt enable */
193 #define IT87_IEC	0x08	/* interrupt enable control */
194 #define IT87_BR		0x10	/* baud rate register enable */
195 #define IT87_RESET	0x20	/* reset */
196 
197 /* RCR bits */
198 #define IT87_RXDCR	0x07	/* receiver demodulation carrier range mask */
199 #define IT87_RXACT	0x08	/* receiver active */
200 #define IT87_RXEND	0x10	/* receiver demodulation enable */
201 #define IT87_RXEN	0x20	/* receiver enable */
202 #define IT87_HCFS	0x40	/* high-speed carrier frequency select */
203 #define IT87_RDWOS	0x80	/* receiver data without sync */
204 
205 /* TCR1 bits */
206 #define IT87_TXMPM	0x03	/* transmitter modulation pulse mode mask */
207 #define IT87_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
208 #define IT87_TXENDF	0x04	/* transmitter deferral */
209 #define IT87_TXRLE	0x08	/* transmitter run length enable */
210 #define IT87_FIFOTL	0x30	/* FIFO level threshold mask */
211 #define IT87_FIFOTL_DEFAULT 0x20	/* FIFO level threshold default
212 					 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
213 					 * 0x30 -> 25 */
214 #define IT87_ILE	0x40	/* internal loopback enable */
215 #define IT87_FIFOCLR	0x80	/* FIFO clear bit */
216 
217 /* TCR2 bits */
218 #define IT87_TXMPW	0x07	/* transmitter modulation pulse width mask */
219 #define IT87_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
220 #define IT87_CFQ	0xf8	/* carrier frequency mask */
221 #define IT87_CFQ_SHIFT	3	/* carrier frequency bit shift */
222 
223 /* TSR bits */
224 #define IT87_TXFBC	0x3f	/* transmitter FIFO byte count mask */
225 
226 /* RSR bits */
227 #define IT87_RXFBC	0x3f	/* receiver FIFO byte count mask */
228 #define IT87_RXFTO	0x80	/* receiver FIFO time-out */
229 
230 /* IIR bits */
231 #define IT87_IP		0x01	/* interrupt pending */
232 #define IT87_II		0x06	/* interrupt identification mask */
233 #define IT87_II_NOINT	0x00	/* no interrupt */
234 #define IT87_II_TXLDL	0x02	/* transmitter low data level */
235 #define IT87_II_RXDS	0x04	/* receiver data stored */
236 #define IT87_II_RXFO	0x06	/* receiver FIFO overrun */
237 
238 /*
239  * IT8512E/F
240  *
241  * Hardware data obtained from:
242  *
243  * IT8512E/F
244  * Embedded Controller
245  * Preliminary Specification V0.4.1
246  *
247  * Note that the CIR registers are not directly available to the host, because
248  * they only are accessible to the integrated microcontroller. Thus, in order
249  * use it, some kind of bridging is required. As the bridging may depend on
250  * the controller firmware in use, we are going to use the PNP ID in order to
251  * determine the strategy and ports available. See after these generic
252  * IT8512E/F register definitions for register definitions for those
253  * strategies.
254  */
255 
256 /* register offsets */
257 #define IT85_C0DR	0x00	/* data register */
258 #define IT85_C0MSTCR	0x01	/* master control register */
259 #define IT85_C0IER	0x02	/* interrupt enable register */
260 #define IT85_C0IIR	0x03	/* interrupt identification register */
261 #define IT85_C0CFR	0x04	/* carrier frequency register */
262 #define IT85_C0RCR	0x05	/* receiver control register */
263 #define IT85_C0TCR	0x06	/* transmitter control register */
264 #define IT85_C0SCK	0x07	/* slow clock control register */
265 #define IT85_C0BDLR	0x08	/* baud rate divisor low byte register */
266 #define IT85_C0BDHR	0x09	/* baud rate divisor high byte register */
267 #define IT85_C0TFSR	0x0a	/* transmitter FIFO status register */
268 #define IT85_C0RFSR	0x0b	/* receiver FIFO status register */
269 #define IT85_C0WCL	0x0d	/* wakeup code length register */
270 #define IT85_C0WCR	0x0e	/* wakeup code read/write register */
271 #define IT85_C0WPS	0x0f	/* wakeup power control/status register */
272 
273 #define IT85_IOREG_LENGTH 0x10	/* length of register file */
274 
275 /* C0MSTCR bits */
276 #define IT85_RESET	0x01	/* reset */
277 #define IT85_FIFOCLR	0x02	/* FIFO clear bit */
278 #define IT85_FIFOTL	0x0c	/* FIFO level threshold mask */
279 #define IT85_FIFOTL_DEFAULT 0x08	/* FIFO level threshold default
280 					 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
281 					 * 0x0c -> 25 */
282 #define IT85_ILE	0x10	/* internal loopback enable */
283 #define IT85_ILSEL	0x20	/* internal loopback select */
284 
285 /* C0IER bits */
286 #define IT85_TLDLIE	0x01	/* TX low data level interrupt enable */
287 #define IT85_RDAIE	0x02	/* RX data available interrupt enable */
288 #define IT85_RFOIE	0x04	/* RX FIFO overrun interrupt enable */
289 #define IT85_IEC	0x80	/* interrupt enable function control */
290 
291 /* C0IIR bits */
292 #define IT85_TLDLI	0x01	/* transmitter low data level interrupt */
293 #define IT85_RDAI	0x02	/* receiver data available interrupt */
294 #define IT85_RFOI	0x04	/* receiver FIFO overrun interrupt */
295 #define IT85_NIP	0x80	/* no interrupt pending */
296 
297 /* C0CFR bits */
298 #define IT85_CFQ	0x1f	/* carrier frequency mask */
299 #define IT85_HCFS	0x20	/* high speed carrier frequency select */
300 
301 /* C0RCR bits */
302 #define IT85_RXDCR	0x07	/* receiver demodulation carrier range mask */
303 #define IT85_RXACT	0x08	/* receiver active */
304 #define IT85_RXEND	0x10	/* receiver demodulation enable */
305 #define IT85_RDWOS	0x20	/* receiver data without sync */
306 #define IT85_RXEN	0x80	/* receiver enable */
307 
308 /* C0TCR bits */
309 #define IT85_TXMPW	0x07	/* transmitter modulation pulse width mask */
310 #define IT85_TXMPW_DEFAULT 0x04	/* default modulation pulse width */
311 #define IT85_TXMPM	0x18	/* transmitter modulation pulse mode mask */
312 #define IT85_TXMPM_DEFAULT 0x00	/* modulation pulse mode default */
313 #define IT85_TXENDF	0x20	/* transmitter deferral */
314 #define IT85_TXRLE	0x40	/* transmitter run length enable */
315 
316 /* C0SCK bits */
317 #define IT85_SCKS	0x01	/* slow clock select */
318 #define IT85_TXDCKG	0x02	/* TXD clock gating */
319 #define IT85_DLL1P8E	0x04	/* DLL 1.8432M enable */
320 #define IT85_DLLTE	0x08	/* DLL test enable */
321 #define IT85_BRCM	0x70	/* baud rate count mode */
322 #define IT85_DLLOCK	0x80	/* DLL lock */
323 
324 /* C0TFSR bits */
325 #define IT85_TXFBC	0x3f	/* transmitter FIFO count mask */
326 
327 /* C0RFSR bits */
328 #define IT85_RXFBC	0x3f	/* receiver FIFO count mask */
329 #define IT85_RXFTO	0x80	/* receiver FIFO time-out */
330 
331 /* C0WCL bits */
332 #define IT85_WCL	0x3f	/* wakeup code length mask */
333 
334 /* C0WPS bits */
335 #define IT85_CIRPOSIE	0x01	/* power on/off status interrupt enable */
336 #define IT85_CIRPOIS	0x02	/* power on/off interrupt status */
337 #define IT85_CIRPOII	0x04	/* power on/off interrupt identification */
338 #define IT85_RCRST	0x10	/* wakeup code reading counter reset bit */
339 #define IT85_WCRST	0x20	/* wakeup code writing counter reset bit */
340 
341 /*
342  * ITE8708
343  *
344  * Hardware data obtained from hacked driver for IT8512 in this forum post:
345  *
346  *  http://ubuntuforums.org/showthread.php?t=1028640
347  *
348  * Although there's no official documentation for that driver, analysis would
349  * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
350  * selectable by a single bank-select bit that's mapped onto both banks. The
351  * IT8512 registers are mapped in a different order, so that the first bank
352  * maps the ones that are used more often, and two registers that share a
353  * reserved high-order bit are placed at the same offset in both banks in
354  * order to reuse the reserved bit as the bank select bit.
355  */
356 
357 /* register offsets */
358 
359 /* mapped onto both banks */
360 #define IT8708_BANKSEL	0x07	/* bank select register */
361 #define IT8708_HRAE	0x80	/* high registers access enable */
362 
363 /* mapped onto the low bank */
364 #define IT8708_C0DR	0x00	/* data register */
365 #define IT8708_C0MSTCR	0x01	/* master control register */
366 #define IT8708_C0IER	0x02	/* interrupt enable register */
367 #define IT8708_C0IIR	0x03	/* interrupt identification register */
368 #define IT8708_C0RFSR	0x04	/* receiver FIFO status register */
369 #define IT8708_C0RCR	0x05	/* receiver control register */
370 #define IT8708_C0TFSR	0x06	/* transmitter FIFO status register */
371 #define IT8708_C0TCR	0x07	/* transmitter control register */
372 
373 /* mapped onto the high bank */
374 #define IT8708_C0BDLR	0x01	/* baud rate divisor low byte register */
375 #define IT8708_C0BDHR	0x02	/* baud rate divisor high byte register */
376 #define IT8708_C0CFR	0x04	/* carrier frequency register */
377 
378 /* registers whose bank mapping we don't know, since they weren't being used
379  * in the hacked driver... most probably they belong to the high bank too,
380  * since they fit in the holes the other registers leave */
381 #define IT8708_C0SCK	0x03	/* slow clock control register */
382 #define IT8708_C0WCL	0x05	/* wakeup code length register */
383 #define IT8708_C0WCR	0x06	/* wakeup code read/write register */
384 #define IT8708_C0WPS	0x07	/* wakeup power control/status register */
385 
386 #define IT8708_IOREG_LENGTH 0x08	/* length of register file */
387 
388 /* two more registers that are defined in the hacked driver, but can't be
389  * found in the data sheets; no idea what they are or how they are accessed,
390  * since the hacked driver doesn't seem to use them */
391 #define IT8708_CSCRR	0x00
392 #define IT8708_CGPINTR	0x01
393 
394 /* CSCRR bits */
395 #define IT8708_CSCRR_SCRB 0x3f
396 #define IT8708_CSCRR_PM	0x80
397 
398 /* CGPINTR bits */
399 #define IT8708_CGPINT	0x01
400 
401 /*
402  * ITE8709
403  *
404  * Hardware interfacing data obtained from the original lirc_ite8709 driver.
405  * Verbatim from its sources:
406  *
407  * The ITE8709 device seems to be the combination of IT8512 superIO chip and
408  * a specific firmware running on the IT8512's embedded micro-controller.
409  * In addition of the embedded micro-controller, the IT8512 chip contains a
410  * CIR module and several other modules. A few modules are directly accessible
411  * by the host CPU, but most of them are only accessible by the
412  * micro-controller. The CIR module is only accessible by the
413  * micro-controller.
414  *
415  * The battery-backed SRAM module is accessible by the host CPU and the
416  * micro-controller. So one of the MC's firmware role is to act as a bridge
417  * between the host CPU and the CIR module. The firmware implements a kind of
418  * communication protocol using the SRAM module as a shared memory. The IT8512
419  * specification is publicly available on ITE's web site, but the
420  * communication protocol is not, so it was reverse-engineered.
421  */
422 
423 /* register offsets */
424 #define IT8709_RAM_IDX	0x00	/* index into the SRAM module bytes */
425 #define IT8709_RAM_VAL	0x01	/* read/write data to the indexed byte */
426 
427 #define IT8709_IOREG_LENGTH 0x02	/* length of register file */
428 
429 /* register offsets inside the SRAM module */
430 #define IT8709_MODE	0x1a	/* request/ack byte */
431 #define IT8709_REG_IDX	0x1b	/* index of the CIR register to access */
432 #define IT8709_REG_VAL	0x1c	/* value read/to be written */
433 #define IT8709_IIR	0x1e	/* interrupt identification register */
434 #define IT8709_RFSR	0x1f	/* receiver FIFO status register */
435 #define IT8709_FIFO	0x20	/* start of in RAM RX FIFO copy */
436 
437 /* MODE values */
438 #define IT8709_IDLE	0x00
439 #define IT8709_WRITE	0x01
440 #define IT8709_READ	0x02
441