xref: /linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c (revision e0c0ab04f6785abaa71b9b8dc252cb1a2072c225) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6  *	Jeffy Chen <jeffy.chen@rock-chips.com>
7  */
8 
9 #include <linux/clk.h>
10 
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16 #include "rockchip_vpu981_regs.h"
17 
18 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
19 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
20 #define RK3588_ACLK_MAX_FREQ (300 * 1000 * 1000)
21 
22 #define ROCKCHIP_VPU981_MIN_SIZE 64
23 
24 /*
25  * Supported formats.
26  */
27 
28 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
29 	{
30 		.fourcc = V4L2_PIX_FMT_YUV420M,
31 		.codec_mode = HANTRO_MODE_NONE,
32 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
33 	},
34 	{
35 		.fourcc = V4L2_PIX_FMT_NV12M,
36 		.codec_mode = HANTRO_MODE_NONE,
37 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
38 	},
39 	{
40 		.fourcc = V4L2_PIX_FMT_YUYV,
41 		.codec_mode = HANTRO_MODE_NONE,
42 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
43 	},
44 	{
45 		.fourcc = V4L2_PIX_FMT_UYVY,
46 		.codec_mode = HANTRO_MODE_NONE,
47 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
48 	},
49 	{
50 		.fourcc = V4L2_PIX_FMT_JPEG,
51 		.codec_mode = HANTRO_MODE_JPEG_ENC,
52 		.max_depth = 2,
53 		.header_size = JPEG_HEADER_SIZE,
54 		.frmsize = {
55 			.min_width = 96,
56 			.max_width = 8192,
57 			.step_width = MB_DIM,
58 			.min_height = 32,
59 			.max_height = 8192,
60 			.step_height = MB_DIM,
61 		},
62 	},
63 };
64 
65 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
66 	{
67 		.fourcc = V4L2_PIX_FMT_YUYV,
68 		.codec_mode = HANTRO_MODE_NONE,
69 		.postprocessed = true,
70 		.frmsize = {
71 			.min_width = FMT_MIN_WIDTH,
72 			.max_width = FMT_FHD_WIDTH,
73 			.step_width = MB_DIM,
74 			.min_height = FMT_MIN_HEIGHT,
75 			.max_height = FMT_FHD_HEIGHT,
76 			.step_height = MB_DIM,
77 		},
78 	},
79 };
80 
81 static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
82 	{
83 		.fourcc = V4L2_PIX_FMT_NV12,
84 		.codec_mode = HANTRO_MODE_NONE,
85 		.postprocessed = true,
86 		.frmsize = {
87 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
88 			.max_width = FMT_4K_WIDTH,
89 			.step_width = MB_DIM,
90 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
91 			.max_height = FMT_4K_HEIGHT,
92 			.step_height = MB_DIM,
93 		},
94 	},
95 	{
96 		.fourcc = V4L2_PIX_FMT_NV15,
97 		.codec_mode = HANTRO_MODE_NONE,
98 		.match_depth = true,
99 		.postprocessed = true,
100 		.frmsize = {
101 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
102 			.max_width = FMT_4K_WIDTH,
103 			.step_width = MB_DIM,
104 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
105 			.max_height = FMT_4K_HEIGHT,
106 			.step_height = MB_DIM,
107 		},
108 	},
109 	{
110 		.fourcc = V4L2_PIX_FMT_P010,
111 		.codec_mode = HANTRO_MODE_NONE,
112 		.match_depth = true,
113 		.postprocessed = true,
114 		.frmsize = {
115 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
116 			.max_width = FMT_4K_WIDTH,
117 			.step_width = MB_DIM,
118 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
119 			.max_height = FMT_4K_HEIGHT,
120 			.step_height = MB_DIM,
121 		},
122 	},
123 };
124 
125 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
126 	{
127 		.fourcc = V4L2_PIX_FMT_NV12,
128 		.codec_mode = HANTRO_MODE_NONE,
129 		.frmsize = {
130 			.min_width = FMT_MIN_WIDTH,
131 			.max_width = FMT_FHD_WIDTH,
132 			.step_width = MB_DIM,
133 			.min_height = FMT_MIN_HEIGHT,
134 			.max_height = FMT_FHD_HEIGHT,
135 			.step_height = MB_DIM,
136 		},
137 	},
138 	{
139 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
140 		.codec_mode = HANTRO_MODE_H264_DEC,
141 		.max_depth = 2,
142 		.frmsize = {
143 			.min_width = FMT_MIN_WIDTH,
144 			.max_width = FMT_FHD_WIDTH,
145 			.step_width = MB_DIM,
146 			.min_height = FMT_MIN_HEIGHT,
147 			.max_height = FMT_FHD_HEIGHT,
148 			.step_height = MB_DIM,
149 		},
150 	},
151 	{
152 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
153 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
154 		.max_depth = 2,
155 		.frmsize = {
156 			.min_width = FMT_MIN_WIDTH,
157 			.max_width = FMT_FHD_WIDTH,
158 			.step_width = MB_DIM,
159 			.min_height = FMT_MIN_HEIGHT,
160 			.max_height = FMT_FHD_HEIGHT,
161 			.step_height = MB_DIM,
162 		},
163 	},
164 	{
165 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
166 		.codec_mode = HANTRO_MODE_VP8_DEC,
167 		.max_depth = 2,
168 		.frmsize = {
169 			.min_width = FMT_MIN_WIDTH,
170 			.max_width = FMT_FHD_WIDTH,
171 			.step_width = MB_DIM,
172 			.min_height = FMT_MIN_HEIGHT,
173 			.max_height = FMT_FHD_HEIGHT,
174 			.step_height = MB_DIM,
175 		},
176 	},
177 };
178 
179 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
180 	{
181 		.fourcc = V4L2_PIX_FMT_NV12,
182 		.codec_mode = HANTRO_MODE_NONE,
183 		.frmsize = {
184 			.min_width = FMT_MIN_WIDTH,
185 			.max_width = FMT_4K_WIDTH,
186 			.step_width = MB_DIM,
187 			.min_height = FMT_MIN_HEIGHT,
188 			.max_height = FMT_4K_HEIGHT,
189 			.step_height = MB_DIM,
190 		},
191 	},
192 	{
193 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
194 		.codec_mode = HANTRO_MODE_H264_DEC,
195 		.max_depth = 2,
196 		.frmsize = {
197 			.min_width = FMT_MIN_WIDTH,
198 			.max_width = FMT_4K_WIDTH,
199 			.step_width = MB_DIM,
200 			.min_height = FMT_MIN_HEIGHT,
201 			.max_height = FMT_4K_HEIGHT,
202 			.step_height = MB_DIM,
203 		},
204 	},
205 	{
206 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
207 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
208 		.max_depth = 2,
209 		.frmsize = {
210 			.min_width = FMT_MIN_WIDTH,
211 			.max_width = FMT_FHD_WIDTH,
212 			.step_width = MB_DIM,
213 			.min_height = FMT_MIN_HEIGHT,
214 			.max_height = FMT_FHD_HEIGHT,
215 			.step_height = MB_DIM,
216 		},
217 	},
218 	{
219 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
220 		.codec_mode = HANTRO_MODE_VP8_DEC,
221 		.max_depth = 2,
222 		.frmsize = {
223 			.min_width = FMT_MIN_WIDTH,
224 			.max_width = FMT_UHD_WIDTH,
225 			.step_width = MB_DIM,
226 			.min_height = FMT_MIN_HEIGHT,
227 			.max_height = FMT_UHD_HEIGHT,
228 			.step_height = MB_DIM,
229 		},
230 	},
231 };
232 
233 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
234 	{
235 		.fourcc = V4L2_PIX_FMT_NV12,
236 		.codec_mode = HANTRO_MODE_NONE,
237 		.frmsize = {
238 			.min_width = FMT_MIN_WIDTH,
239 			.max_width = FMT_FHD_WIDTH,
240 			.step_width = MB_DIM,
241 			.min_height = FMT_MIN_HEIGHT,
242 			.max_height = FMT_FHD_HEIGHT,
243 			.step_height = MB_DIM,
244 		},
245 	},
246 	{
247 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
248 		.codec_mode = HANTRO_MODE_H264_DEC,
249 		.max_depth = 2,
250 		.frmsize = {
251 			.min_width = FMT_MIN_WIDTH,
252 			.max_width = FMT_FHD_WIDTH,
253 			.step_width = MB_DIM,
254 			.min_height = FMT_MIN_HEIGHT,
255 			.max_height = FMT_FHD_HEIGHT,
256 			.step_height = MB_DIM,
257 		},
258 	},
259 	{
260 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
261 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
262 		.max_depth = 2,
263 		.frmsize = {
264 			.min_width = FMT_MIN_WIDTH,
265 			.max_width = FMT_FHD_WIDTH,
266 			.step_width = MB_DIM,
267 			.min_height = FMT_MIN_HEIGHT,
268 			.max_height = FMT_FHD_HEIGHT,
269 			.step_height = MB_DIM,
270 		},
271 	},
272 	{
273 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
274 		.codec_mode = HANTRO_MODE_VP8_DEC,
275 		.max_depth = 2,
276 		.frmsize = {
277 			.min_width = FMT_MIN_WIDTH,
278 			.max_width = FMT_UHD_WIDTH,
279 			.step_width = MB_DIM,
280 			.min_height = FMT_MIN_HEIGHT,
281 			.max_height = FMT_UHD_HEIGHT,
282 			.step_height = MB_DIM,
283 		},
284 	},
285 };
286 
287 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
288 	{
289 		.fourcc = V4L2_PIX_FMT_NV12,
290 		.codec_mode = HANTRO_MODE_NONE,
291 		.frmsize = {
292 			.min_width = FMT_MIN_WIDTH,
293 			.max_width = FMT_FHD_WIDTH,
294 			.step_width = MB_DIM,
295 			.min_height = FMT_MIN_HEIGHT,
296 			.max_height = FMT_FHD_HEIGHT,
297 			.step_height = MB_DIM,
298 		},
299 	},
300 	{
301 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
302 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
303 		.max_depth = 2,
304 		.frmsize = {
305 			.min_width = FMT_MIN_WIDTH,
306 			.max_width = FMT_FHD_WIDTH,
307 			.step_width = MB_DIM,
308 			.min_height = FMT_MIN_HEIGHT,
309 			.max_height = FMT_FHD_HEIGHT,
310 			.step_height = MB_DIM,
311 		},
312 	},
313 	{
314 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
315 		.codec_mode = HANTRO_MODE_VP8_DEC,
316 		.max_depth = 2,
317 		.frmsize = {
318 			.min_width = FMT_MIN_WIDTH,
319 			.max_width = FMT_UHD_WIDTH,
320 			.step_width = MB_DIM,
321 			.min_height = FMT_MIN_HEIGHT,
322 			.max_height = FMT_UHD_HEIGHT,
323 			.step_height = MB_DIM,
324 		},
325 	},
326 };
327 
328 static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
329 	{
330 		.fourcc = V4L2_PIX_FMT_NV12_4L4,
331 		.codec_mode = HANTRO_MODE_NONE,
332 		.match_depth = true,
333 		.frmsize = {
334 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
335 			.max_width = FMT_4K_WIDTH,
336 			.step_width = MB_DIM,
337 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
338 			.max_height = FMT_4K_HEIGHT,
339 			.step_height = MB_DIM,
340 		},
341 	},
342 	{
343 		.fourcc = V4L2_PIX_FMT_NV15_4L4,
344 		.codec_mode = HANTRO_MODE_NONE,
345 		.match_depth = true,
346 		.frmsize = {
347 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
348 			.max_width = FMT_4K_WIDTH,
349 			.step_width = MB_DIM,
350 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
351 			.max_height = FMT_4K_HEIGHT,
352 			.step_height = MB_DIM,
353 		},
354 	},
355 	{
356 		.fourcc = V4L2_PIX_FMT_AV1_FRAME,
357 		.codec_mode = HANTRO_MODE_AV1_DEC,
358 		.max_depth = 2,
359 		.frmsize = {
360 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
361 			.max_width = FMT_4K_WIDTH,
362 			.step_width = MB_DIM,
363 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
364 			.max_height = FMT_4K_HEIGHT,
365 			.step_height = MB_DIM,
366 		},
367 	},
368 };
369 
370 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
371 {
372 	struct hantro_dev *vpu = dev_id;
373 	enum vb2_buffer_state state;
374 	u32 status;
375 
376 	status = vepu_read(vpu, H1_REG_INTERRUPT);
377 	state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
378 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
379 
380 	vepu_write(vpu, 0, H1_REG_INTERRUPT);
381 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
382 
383 	hantro_irq_done(vpu, state);
384 
385 	return IRQ_HANDLED;
386 }
387 
388 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
389 {
390 	struct hantro_dev *vpu = dev_id;
391 	enum vb2_buffer_state state;
392 	u32 status;
393 
394 	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
395 	state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
396 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
397 
398 	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
399 	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
400 
401 	hantro_irq_done(vpu, state);
402 
403 	return IRQ_HANDLED;
404 }
405 
406 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
407 {
408 	struct hantro_dev *vpu = dev_id;
409 	enum vb2_buffer_state state;
410 	u32 status;
411 
412 	status = vepu_read(vpu, VEPU_REG_INTERRUPT);
413 	state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
414 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
415 
416 	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
417 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
418 
419 	hantro_irq_done(vpu, state);
420 
421 	return IRQ_HANDLED;
422 }
423 
424 static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
425 {
426 	struct hantro_dev *vpu = dev_id;
427 	enum vb2_buffer_state state;
428 	u32 status;
429 
430 	status = vdpu_read(vpu, AV1_REG_INTERRUPT);
431 	state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
432 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
433 
434 	vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
435 	vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
436 
437 	hantro_irq_done(vpu, state);
438 
439 	return IRQ_HANDLED;
440 }
441 
442 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
443 {
444 	/* Bump ACLK to max. possible freq. to improve performance. */
445 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
446 	return 0;
447 }
448 
449 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
450 {
451 	/* Bump ACLKs to max. possible freq. to improve performance. */
452 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
453 	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
454 	return 0;
455 }
456 
457 static int rk3588_vpu981_hw_init(struct hantro_dev *vpu)
458 {
459 	/* Bump ACLKs to max. possible freq. to improve performance. */
460 	clk_set_rate(vpu->clocks[0].clk, RK3588_ACLK_MAX_FREQ);
461 	return 0;
462 }
463 
464 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
465 {
466 	/* Bump ACLK to max. possible freq. to improve performance. */
467 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
468 	return 0;
469 }
470 
471 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
472 {
473 	struct hantro_dev *vpu = ctx->dev;
474 
475 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
476 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
477 }
478 
479 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
480 {
481 	struct hantro_dev *vpu = ctx->dev;
482 
483 	vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
484 	vepu_write(vpu, 0, H1_REG_ENC_CTRL);
485 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
486 }
487 
488 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
489 {
490 	struct hantro_dev *vpu = ctx->dev;
491 
492 	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
493 	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
494 	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
495 }
496 
497 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
498 {
499 	struct hantro_dev *vpu = ctx->dev;
500 
501 	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
502 	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
503 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
504 }
505 
506 /*
507  * Supported codec ops.
508  */
509 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
510 	[HANTRO_MODE_H264_DEC] = {
511 		.run = hantro_g1_h264_dec_run,
512 		.reset = hantro_g1_reset,
513 		.init = hantro_h264_dec_init,
514 		.exit = hantro_h264_dec_exit,
515 	},
516 	[HANTRO_MODE_MPEG2_DEC] = {
517 		.run = hantro_g1_mpeg2_dec_run,
518 		.reset = hantro_g1_reset,
519 		.init = hantro_mpeg2_dec_init,
520 		.exit = hantro_mpeg2_dec_exit,
521 	},
522 	[HANTRO_MODE_VP8_DEC] = {
523 		.run = hantro_g1_vp8_dec_run,
524 		.reset = hantro_g1_reset,
525 		.init = hantro_vp8_dec_init,
526 		.exit = hantro_vp8_dec_exit,
527 	},
528 };
529 
530 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
531 	[HANTRO_MODE_JPEG_ENC] = {
532 		.run = hantro_h1_jpeg_enc_run,
533 		.reset = rockchip_vpu1_enc_reset,
534 		.done = hantro_h1_jpeg_enc_done,
535 	},
536 	[HANTRO_MODE_H264_DEC] = {
537 		.run = hantro_g1_h264_dec_run,
538 		.reset = rk3066_vpu_dec_reset,
539 		.init = hantro_h264_dec_init,
540 		.exit = hantro_h264_dec_exit,
541 	},
542 	[HANTRO_MODE_MPEG2_DEC] = {
543 		.run = hantro_g1_mpeg2_dec_run,
544 		.reset = rk3066_vpu_dec_reset,
545 		.init = hantro_mpeg2_dec_init,
546 		.exit = hantro_mpeg2_dec_exit,
547 	},
548 	[HANTRO_MODE_VP8_DEC] = {
549 		.run = hantro_g1_vp8_dec_run,
550 		.reset = rk3066_vpu_dec_reset,
551 		.init = hantro_vp8_dec_init,
552 		.exit = hantro_vp8_dec_exit,
553 	},
554 };
555 
556 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
557 	[HANTRO_MODE_JPEG_ENC] = {
558 		.run = hantro_h1_jpeg_enc_run,
559 		.reset = rockchip_vpu1_enc_reset,
560 		.done = hantro_h1_jpeg_enc_done,
561 	},
562 	[HANTRO_MODE_H264_DEC] = {
563 		.run = hantro_g1_h264_dec_run,
564 		.reset = hantro_g1_reset,
565 		.init = hantro_h264_dec_init,
566 		.exit = hantro_h264_dec_exit,
567 	},
568 	[HANTRO_MODE_MPEG2_DEC] = {
569 		.run = hantro_g1_mpeg2_dec_run,
570 		.reset = hantro_g1_reset,
571 		.init = hantro_mpeg2_dec_init,
572 		.exit = hantro_mpeg2_dec_exit,
573 	},
574 	[HANTRO_MODE_VP8_DEC] = {
575 		.run = hantro_g1_vp8_dec_run,
576 		.reset = hantro_g1_reset,
577 		.init = hantro_vp8_dec_init,
578 		.exit = hantro_vp8_dec_exit,
579 	},
580 };
581 
582 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
583 	[HANTRO_MODE_JPEG_ENC] = {
584 		.run = rockchip_vpu2_jpeg_enc_run,
585 		.reset = rockchip_vpu2_enc_reset,
586 		.done = rockchip_vpu2_jpeg_enc_done,
587 	},
588 	[HANTRO_MODE_H264_DEC] = {
589 		.run = rockchip_vpu2_h264_dec_run,
590 		.reset = rockchip_vpu2_dec_reset,
591 		.init = hantro_h264_dec_init,
592 		.exit = hantro_h264_dec_exit,
593 	},
594 	[HANTRO_MODE_MPEG2_DEC] = {
595 		.run = rockchip_vpu2_mpeg2_dec_run,
596 		.reset = rockchip_vpu2_dec_reset,
597 		.init = hantro_mpeg2_dec_init,
598 		.exit = hantro_mpeg2_dec_exit,
599 	},
600 	[HANTRO_MODE_VP8_DEC] = {
601 		.run = rockchip_vpu2_vp8_dec_run,
602 		.reset = rockchip_vpu2_dec_reset,
603 		.init = hantro_vp8_dec_init,
604 		.exit = hantro_vp8_dec_exit,
605 	},
606 };
607 
608 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
609 	[HANTRO_MODE_JPEG_ENC] = {
610 		.run = rockchip_vpu2_jpeg_enc_run,
611 		.reset = rockchip_vpu2_enc_reset,
612 		.done = rockchip_vpu2_jpeg_enc_done,
613 	},
614 };
615 
616 static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
617 	[HANTRO_MODE_AV1_DEC] = {
618 		.run = rockchip_vpu981_av1_dec_run,
619 		.init = rockchip_vpu981_av1_dec_init,
620 		.exit = rockchip_vpu981_av1_dec_exit,
621 		.done = rockchip_vpu981_av1_dec_done,
622 	},
623 };
624 /*
625  * VPU variant.
626  */
627 
628 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
629 	{ "vdpu", hantro_g1_irq },
630 };
631 
632 static const struct hantro_irq rockchip_vpu1_irqs[] = {
633 	{ "vepu", rockchip_vpu1_vepu_irq },
634 	{ "vdpu", hantro_g1_irq },
635 };
636 
637 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
638 	{ "vdpu", rockchip_vpu2_vdpu_irq },
639 };
640 
641 static const struct hantro_irq rockchip_vpu2_irqs[] = {
642 	{ "vepu", rockchip_vpu2_vepu_irq },
643 	{ "vdpu", rockchip_vpu2_vdpu_irq },
644 };
645 
646 static const struct hantro_irq rk3568_vepu_irqs[] = {
647 	{ "vepu", rockchip_vpu2_vepu_irq },
648 };
649 
650 static const char * const rk3066_vpu_clk_names[] = {
651 	"aclk_vdpu", "hclk_vdpu",
652 	"aclk_vepu", "hclk_vepu"
653 };
654 
655 static const struct hantro_irq rk3588_vpu981_irqs[] = {
656 	{ "vdpu", rk3588_vpu981_irq },
657 };
658 
659 static const char * const rockchip_vpu_clk_names[] = {
660 	"aclk", "hclk"
661 };
662 
663 static const char * const rk3588_vpu981_vpu_clk_names[] = {
664 	"aclk", "hclk",
665 };
666 
667 /* VDPU1/VEPU1 */
668 
669 const struct hantro_variant rk3036_vpu_variant = {
670 	.dec_offset = 0x400,
671 	.dec_fmts = rk3066_vpu_dec_fmts,
672 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
673 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
674 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
675 	.postproc_ops = &hantro_g1_postproc_ops,
676 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
677 		 HANTRO_H264_DECODER,
678 	.codec_ops = rk3036_vpu_codec_ops,
679 	.irqs = rockchip_vdpu1_irqs,
680 	.num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
681 	.init = rk3036_vpu_hw_init,
682 	.clk_names = rockchip_vpu_clk_names,
683 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
684 };
685 
686 /*
687  * Despite this variant has separate clocks for decoder and encoder,
688  * it's still required to enable all four of them for either decoding
689  * or encoding and we can't split it in separate g1/h1 variants.
690  */
691 const struct hantro_variant rk3066_vpu_variant = {
692 	.enc_offset = 0x0,
693 	.enc_fmts = rockchip_vpu_enc_fmts,
694 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
695 	.dec_offset = 0x400,
696 	.dec_fmts = rk3066_vpu_dec_fmts,
697 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
698 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
699 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
700 	.postproc_ops = &hantro_g1_postproc_ops,
701 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
702 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
703 	.codec_ops = rk3066_vpu_codec_ops,
704 	.irqs = rockchip_vpu1_irqs,
705 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
706 	.init = rk3066_vpu_hw_init,
707 	.clk_names = rk3066_vpu_clk_names,
708 	.num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
709 };
710 
711 const struct hantro_variant rk3288_vpu_variant = {
712 	.enc_offset = 0x0,
713 	.enc_fmts = rockchip_vpu_enc_fmts,
714 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
715 	.dec_offset = 0x400,
716 	.dec_fmts = rk3288_vpu_dec_fmts,
717 	.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
718 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
719 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
720 	.postproc_ops = &hantro_g1_postproc_ops,
721 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
722 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
723 	.codec_ops = rk3288_vpu_codec_ops,
724 	.irqs = rockchip_vpu1_irqs,
725 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
726 	.init = rockchip_vpu_hw_init,
727 	.clk_names = rockchip_vpu_clk_names,
728 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
729 };
730 
731 /* VDPU2/VEPU2 */
732 
733 const struct hantro_variant rk3328_vpu_variant = {
734 	.dec_offset = 0x400,
735 	.dec_fmts = rockchip_vdpu2_dec_fmts,
736 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
737 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
738 		 HANTRO_H264_DECODER,
739 	.codec_ops = rk3399_vpu_codec_ops,
740 	.irqs = rockchip_vdpu2_irqs,
741 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
742 	.init = rockchip_vpu_hw_init,
743 	.clk_names = rockchip_vpu_clk_names,
744 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
745 };
746 
747 /*
748  * H.264 decoding explicitly disabled in RK3399.
749  * This ensures userspace applications use the Rockchip VDEC core,
750  * which has better performance.
751  */
752 const struct hantro_variant rk3399_vpu_variant = {
753 	.enc_offset = 0x0,
754 	.enc_fmts = rockchip_vpu_enc_fmts,
755 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
756 	.dec_offset = 0x400,
757 	.dec_fmts = rk3399_vpu_dec_fmts,
758 	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
759 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
760 		 HANTRO_VP8_DECODER,
761 	.codec_ops = rk3399_vpu_codec_ops,
762 	.irqs = rockchip_vpu2_irqs,
763 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
764 	.init = rockchip_vpu_hw_init,
765 	.clk_names = rockchip_vpu_clk_names,
766 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
767 };
768 
769 const struct hantro_variant rk3568_vepu_variant = {
770 	.enc_offset = 0x0,
771 	.enc_fmts = rockchip_vpu_enc_fmts,
772 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
773 	.codec = HANTRO_JPEG_ENCODER,
774 	.codec_ops = rk3568_vepu_codec_ops,
775 	.irqs = rk3568_vepu_irqs,
776 	.num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
777 	.init = rockchip_vpu_hw_init,
778 	.clk_names = rockchip_vpu_clk_names,
779 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
780 };
781 
782 const struct hantro_variant rk3568_vpu_variant = {
783 	.dec_offset = 0x400,
784 	.dec_fmts = rockchip_vdpu2_dec_fmts,
785 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
786 	.codec = HANTRO_MPEG2_DECODER |
787 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
788 	.codec_ops = rk3399_vpu_codec_ops,
789 	.irqs = rockchip_vdpu2_irqs,
790 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
791 	.init = rockchip_vpu_hw_init,
792 	.clk_names = rockchip_vpu_clk_names,
793 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
794 };
795 
796 const struct hantro_variant px30_vpu_variant = {
797 	.enc_offset = 0x0,
798 	.enc_fmts = rockchip_vpu_enc_fmts,
799 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
800 	.dec_offset = 0x400,
801 	.dec_fmts = rockchip_vdpu2_dec_fmts,
802 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
803 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
804 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
805 	.codec_ops = rk3399_vpu_codec_ops,
806 	.irqs = rockchip_vpu2_irqs,
807 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
808 	.init = rk3036_vpu_hw_init,
809 	.clk_names = rockchip_vpu_clk_names,
810 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
811 };
812 
813 const struct hantro_variant rk3588_vpu981_variant = {
814 	.dec_offset = 0x0,
815 	.dec_fmts = rockchip_vpu981_dec_fmts,
816 	.num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
817 	.postproc_fmts = rockchip_vpu981_postproc_fmts,
818 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
819 	.postproc_ops = &rockchip_vpu981_postproc_ops,
820 	.codec = HANTRO_AV1_DECODER,
821 	.codec_ops = rk3588_vpu981_codec_ops,
822 	.irqs = rk3588_vpu981_irqs,
823 	.num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
824 	.init = rk3588_vpu981_hw_init,
825 	.clk_names = rk3588_vpu981_vpu_clk_names,
826 	.num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
827 };
828