xref: /linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c (revision 9f2c9170934eace462499ba0bfe042cc72900173) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6  *	Jeffy Chen <jeffy.chen@rock-chips.com>
7  */
8 
9 #include <linux/clk.h>
10 
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16 
17 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
18 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
19 
20 /*
21  * Supported formats.
22  */
23 
24 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
25 	{
26 		.fourcc = V4L2_PIX_FMT_YUV420M,
27 		.codec_mode = HANTRO_MODE_NONE,
28 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
29 	},
30 	{
31 		.fourcc = V4L2_PIX_FMT_NV12M,
32 		.codec_mode = HANTRO_MODE_NONE,
33 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
34 	},
35 	{
36 		.fourcc = V4L2_PIX_FMT_YUYV,
37 		.codec_mode = HANTRO_MODE_NONE,
38 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
39 	},
40 	{
41 		.fourcc = V4L2_PIX_FMT_UYVY,
42 		.codec_mode = HANTRO_MODE_NONE,
43 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
44 	},
45 	{
46 		.fourcc = V4L2_PIX_FMT_JPEG,
47 		.codec_mode = HANTRO_MODE_JPEG_ENC,
48 		.max_depth = 2,
49 		.header_size = JPEG_HEADER_SIZE,
50 		.frmsize = {
51 			.min_width = 96,
52 			.max_width = 8192,
53 			.step_width = MB_DIM,
54 			.min_height = 32,
55 			.max_height = 8192,
56 			.step_height = MB_DIM,
57 		},
58 	},
59 };
60 
61 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
62 	{
63 		.fourcc = V4L2_PIX_FMT_YUYV,
64 		.codec_mode = HANTRO_MODE_NONE,
65 		.postprocessed = true,
66 		.frmsize = {
67 			.min_width = FMT_MIN_WIDTH,
68 			.max_width = FMT_FHD_WIDTH,
69 			.step_width = MB_DIM,
70 			.min_height = FMT_MIN_HEIGHT,
71 			.max_height = FMT_FHD_HEIGHT,
72 			.step_height = MB_DIM,
73 		},
74 	},
75 };
76 
77 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
78 	{
79 		.fourcc = V4L2_PIX_FMT_NV12,
80 		.codec_mode = HANTRO_MODE_NONE,
81 		.frmsize = {
82 			.min_width = FMT_MIN_WIDTH,
83 			.max_width = FMT_FHD_WIDTH,
84 			.step_width = MB_DIM,
85 			.min_height = FMT_MIN_HEIGHT,
86 			.max_height = FMT_FHD_HEIGHT,
87 			.step_height = MB_DIM,
88 		},
89 	},
90 	{
91 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
92 		.codec_mode = HANTRO_MODE_H264_DEC,
93 		.max_depth = 2,
94 		.frmsize = {
95 			.min_width = FMT_MIN_WIDTH,
96 			.max_width = FMT_FHD_WIDTH,
97 			.step_width = MB_DIM,
98 			.min_height = FMT_MIN_HEIGHT,
99 			.max_height = FMT_FHD_HEIGHT,
100 			.step_height = MB_DIM,
101 		},
102 	},
103 	{
104 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
105 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
106 		.max_depth = 2,
107 		.frmsize = {
108 			.min_width = FMT_MIN_WIDTH,
109 			.max_width = FMT_FHD_WIDTH,
110 			.step_width = MB_DIM,
111 			.min_height = FMT_MIN_HEIGHT,
112 			.max_height = FMT_FHD_HEIGHT,
113 			.step_height = MB_DIM,
114 		},
115 	},
116 	{
117 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
118 		.codec_mode = HANTRO_MODE_VP8_DEC,
119 		.max_depth = 2,
120 		.frmsize = {
121 			.min_width = FMT_MIN_WIDTH,
122 			.max_width = FMT_FHD_WIDTH,
123 			.step_width = MB_DIM,
124 			.min_height = FMT_MIN_HEIGHT,
125 			.max_height = FMT_FHD_HEIGHT,
126 			.step_height = MB_DIM,
127 		},
128 	},
129 };
130 
131 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
132 	{
133 		.fourcc = V4L2_PIX_FMT_NV12,
134 		.codec_mode = HANTRO_MODE_NONE,
135 		.frmsize = {
136 			.min_width = FMT_MIN_WIDTH,
137 			.max_width = FMT_4K_WIDTH,
138 			.step_width = MB_DIM,
139 			.min_height = FMT_MIN_HEIGHT,
140 			.max_height = FMT_4K_HEIGHT,
141 			.step_height = MB_DIM,
142 		},
143 	},
144 	{
145 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
146 		.codec_mode = HANTRO_MODE_H264_DEC,
147 		.max_depth = 2,
148 		.frmsize = {
149 			.min_width = FMT_MIN_WIDTH,
150 			.max_width = FMT_4K_WIDTH,
151 			.step_width = MB_DIM,
152 			.min_height = FMT_MIN_HEIGHT,
153 			.max_height = FMT_4K_HEIGHT,
154 			.step_height = MB_DIM,
155 		},
156 	},
157 	{
158 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
159 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
160 		.max_depth = 2,
161 		.frmsize = {
162 			.min_width = FMT_MIN_WIDTH,
163 			.max_width = FMT_FHD_WIDTH,
164 			.step_width = MB_DIM,
165 			.min_height = FMT_MIN_HEIGHT,
166 			.max_height = FMT_FHD_HEIGHT,
167 			.step_height = MB_DIM,
168 		},
169 	},
170 	{
171 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
172 		.codec_mode = HANTRO_MODE_VP8_DEC,
173 		.max_depth = 2,
174 		.frmsize = {
175 			.min_width = FMT_MIN_WIDTH,
176 			.max_width = FMT_UHD_WIDTH,
177 			.step_width = MB_DIM,
178 			.min_height = FMT_MIN_HEIGHT,
179 			.max_height = FMT_UHD_HEIGHT,
180 			.step_height = MB_DIM,
181 		},
182 	},
183 };
184 
185 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
186 	{
187 		.fourcc = V4L2_PIX_FMT_NV12,
188 		.codec_mode = HANTRO_MODE_NONE,
189 		.frmsize = {
190 			.min_width = FMT_MIN_WIDTH,
191 			.max_width = FMT_FHD_WIDTH,
192 			.step_width = MB_DIM,
193 			.min_height = FMT_MIN_HEIGHT,
194 			.max_height = FMT_FHD_HEIGHT,
195 			.step_height = MB_DIM,
196 		},
197 	},
198 	{
199 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
200 		.codec_mode = HANTRO_MODE_H264_DEC,
201 		.max_depth = 2,
202 		.frmsize = {
203 			.min_width = FMT_MIN_WIDTH,
204 			.max_width = FMT_FHD_WIDTH,
205 			.step_width = MB_DIM,
206 			.min_height = FMT_MIN_HEIGHT,
207 			.max_height = FMT_FHD_HEIGHT,
208 			.step_height = MB_DIM,
209 		},
210 	},
211 	{
212 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
213 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
214 		.max_depth = 2,
215 		.frmsize = {
216 			.min_width = FMT_MIN_WIDTH,
217 			.max_width = FMT_FHD_WIDTH,
218 			.step_width = MB_DIM,
219 			.min_height = FMT_MIN_HEIGHT,
220 			.max_height = FMT_FHD_HEIGHT,
221 			.step_height = MB_DIM,
222 		},
223 	},
224 	{
225 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
226 		.codec_mode = HANTRO_MODE_VP8_DEC,
227 		.max_depth = 2,
228 		.frmsize = {
229 			.min_width = FMT_MIN_WIDTH,
230 			.max_width = FMT_UHD_WIDTH,
231 			.step_width = MB_DIM,
232 			.min_height = FMT_MIN_HEIGHT,
233 			.max_height = FMT_UHD_HEIGHT,
234 			.step_height = MB_DIM,
235 		},
236 	},
237 };
238 
239 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
240 	{
241 		.fourcc = V4L2_PIX_FMT_NV12,
242 		.codec_mode = HANTRO_MODE_NONE,
243 		.frmsize = {
244 			.min_width = FMT_MIN_WIDTH,
245 			.max_width = FMT_FHD_WIDTH,
246 			.step_width = MB_DIM,
247 			.min_height = FMT_MIN_HEIGHT,
248 			.max_height = FMT_FHD_HEIGHT,
249 			.step_height = MB_DIM,
250 		},
251 	},
252 	{
253 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
254 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
255 		.max_depth = 2,
256 		.frmsize = {
257 			.min_width = FMT_MIN_WIDTH,
258 			.max_width = FMT_FHD_WIDTH,
259 			.step_width = MB_DIM,
260 			.min_height = FMT_MIN_HEIGHT,
261 			.max_height = FMT_FHD_HEIGHT,
262 			.step_height = MB_DIM,
263 		},
264 	},
265 	{
266 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
267 		.codec_mode = HANTRO_MODE_VP8_DEC,
268 		.max_depth = 2,
269 		.frmsize = {
270 			.min_width = FMT_MIN_WIDTH,
271 			.max_width = FMT_UHD_WIDTH,
272 			.step_width = MB_DIM,
273 			.min_height = FMT_MIN_HEIGHT,
274 			.max_height = FMT_UHD_HEIGHT,
275 			.step_height = MB_DIM,
276 		},
277 	},
278 };
279 
280 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
281 {
282 	struct hantro_dev *vpu = dev_id;
283 	enum vb2_buffer_state state;
284 	u32 status;
285 
286 	status = vepu_read(vpu, H1_REG_INTERRUPT);
287 	state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
288 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
289 
290 	vepu_write(vpu, 0, H1_REG_INTERRUPT);
291 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
292 
293 	hantro_irq_done(vpu, state);
294 
295 	return IRQ_HANDLED;
296 }
297 
298 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
299 {
300 	struct hantro_dev *vpu = dev_id;
301 	enum vb2_buffer_state state;
302 	u32 status;
303 
304 	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
305 	state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
306 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
307 
308 	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
309 	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
310 
311 	hantro_irq_done(vpu, state);
312 
313 	return IRQ_HANDLED;
314 }
315 
316 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
317 {
318 	struct hantro_dev *vpu = dev_id;
319 	enum vb2_buffer_state state;
320 	u32 status;
321 
322 	status = vepu_read(vpu, VEPU_REG_INTERRUPT);
323 	state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
324 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
325 
326 	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
327 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
328 
329 	hantro_irq_done(vpu, state);
330 
331 	return IRQ_HANDLED;
332 }
333 
334 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
335 {
336 	/* Bump ACLK to max. possible freq. to improve performance. */
337 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
338 	return 0;
339 }
340 
341 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
342 {
343 	/* Bump ACLKs to max. possible freq. to improve performance. */
344 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
345 	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
346 	return 0;
347 }
348 
349 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
350 {
351 	/* Bump ACLK to max. possible freq. to improve performance. */
352 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
353 	return 0;
354 }
355 
356 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
357 {
358 	struct hantro_dev *vpu = ctx->dev;
359 
360 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
361 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
362 }
363 
364 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
365 {
366 	struct hantro_dev *vpu = ctx->dev;
367 
368 	vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
369 	vepu_write(vpu, 0, H1_REG_ENC_CTRL);
370 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
371 }
372 
373 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
374 {
375 	struct hantro_dev *vpu = ctx->dev;
376 
377 	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
378 	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
379 	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
380 }
381 
382 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
383 {
384 	struct hantro_dev *vpu = ctx->dev;
385 
386 	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
387 	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
388 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
389 }
390 
391 /*
392  * Supported codec ops.
393  */
394 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
395 	[HANTRO_MODE_H264_DEC] = {
396 		.run = hantro_g1_h264_dec_run,
397 		.reset = hantro_g1_reset,
398 		.init = hantro_h264_dec_init,
399 		.exit = hantro_h264_dec_exit,
400 	},
401 	[HANTRO_MODE_MPEG2_DEC] = {
402 		.run = hantro_g1_mpeg2_dec_run,
403 		.reset = hantro_g1_reset,
404 		.init = hantro_mpeg2_dec_init,
405 		.exit = hantro_mpeg2_dec_exit,
406 	},
407 	[HANTRO_MODE_VP8_DEC] = {
408 		.run = hantro_g1_vp8_dec_run,
409 		.reset = hantro_g1_reset,
410 		.init = hantro_vp8_dec_init,
411 		.exit = hantro_vp8_dec_exit,
412 	},
413 };
414 
415 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
416 	[HANTRO_MODE_JPEG_ENC] = {
417 		.run = hantro_h1_jpeg_enc_run,
418 		.reset = rockchip_vpu1_enc_reset,
419 		.done = hantro_h1_jpeg_enc_done,
420 	},
421 	[HANTRO_MODE_H264_DEC] = {
422 		.run = hantro_g1_h264_dec_run,
423 		.reset = rk3066_vpu_dec_reset,
424 		.init = hantro_h264_dec_init,
425 		.exit = hantro_h264_dec_exit,
426 	},
427 	[HANTRO_MODE_MPEG2_DEC] = {
428 		.run = hantro_g1_mpeg2_dec_run,
429 		.reset = rk3066_vpu_dec_reset,
430 		.init = hantro_mpeg2_dec_init,
431 		.exit = hantro_mpeg2_dec_exit,
432 	},
433 	[HANTRO_MODE_VP8_DEC] = {
434 		.run = hantro_g1_vp8_dec_run,
435 		.reset = rk3066_vpu_dec_reset,
436 		.init = hantro_vp8_dec_init,
437 		.exit = hantro_vp8_dec_exit,
438 	},
439 };
440 
441 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
442 	[HANTRO_MODE_JPEG_ENC] = {
443 		.run = hantro_h1_jpeg_enc_run,
444 		.reset = rockchip_vpu1_enc_reset,
445 		.done = hantro_h1_jpeg_enc_done,
446 	},
447 	[HANTRO_MODE_H264_DEC] = {
448 		.run = hantro_g1_h264_dec_run,
449 		.reset = hantro_g1_reset,
450 		.init = hantro_h264_dec_init,
451 		.exit = hantro_h264_dec_exit,
452 	},
453 	[HANTRO_MODE_MPEG2_DEC] = {
454 		.run = hantro_g1_mpeg2_dec_run,
455 		.reset = hantro_g1_reset,
456 		.init = hantro_mpeg2_dec_init,
457 		.exit = hantro_mpeg2_dec_exit,
458 	},
459 	[HANTRO_MODE_VP8_DEC] = {
460 		.run = hantro_g1_vp8_dec_run,
461 		.reset = hantro_g1_reset,
462 		.init = hantro_vp8_dec_init,
463 		.exit = hantro_vp8_dec_exit,
464 	},
465 };
466 
467 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
468 	[HANTRO_MODE_JPEG_ENC] = {
469 		.run = rockchip_vpu2_jpeg_enc_run,
470 		.reset = rockchip_vpu2_enc_reset,
471 		.done = rockchip_vpu2_jpeg_enc_done,
472 	},
473 	[HANTRO_MODE_H264_DEC] = {
474 		.run = rockchip_vpu2_h264_dec_run,
475 		.reset = rockchip_vpu2_dec_reset,
476 		.init = hantro_h264_dec_init,
477 		.exit = hantro_h264_dec_exit,
478 	},
479 	[HANTRO_MODE_MPEG2_DEC] = {
480 		.run = rockchip_vpu2_mpeg2_dec_run,
481 		.reset = rockchip_vpu2_dec_reset,
482 		.init = hantro_mpeg2_dec_init,
483 		.exit = hantro_mpeg2_dec_exit,
484 	},
485 	[HANTRO_MODE_VP8_DEC] = {
486 		.run = rockchip_vpu2_vp8_dec_run,
487 		.reset = rockchip_vpu2_dec_reset,
488 		.init = hantro_vp8_dec_init,
489 		.exit = hantro_vp8_dec_exit,
490 	},
491 };
492 
493 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
494 	[HANTRO_MODE_JPEG_ENC] = {
495 		.run = rockchip_vpu2_jpeg_enc_run,
496 		.reset = rockchip_vpu2_enc_reset,
497 		.done = rockchip_vpu2_jpeg_enc_done,
498 	},
499 };
500 
501 /*
502  * VPU variant.
503  */
504 
505 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
506 	{ "vdpu", hantro_g1_irq },
507 };
508 
509 static const struct hantro_irq rockchip_vpu1_irqs[] = {
510 	{ "vepu", rockchip_vpu1_vepu_irq },
511 	{ "vdpu", hantro_g1_irq },
512 };
513 
514 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
515 	{ "vdpu", rockchip_vpu2_vdpu_irq },
516 };
517 
518 static const struct hantro_irq rockchip_vpu2_irqs[] = {
519 	{ "vepu", rockchip_vpu2_vepu_irq },
520 	{ "vdpu", rockchip_vpu2_vdpu_irq },
521 };
522 
523 static const struct hantro_irq rk3568_vepu_irqs[] = {
524 	{ "vepu", rockchip_vpu2_vepu_irq },
525 };
526 
527 static const char * const rk3066_vpu_clk_names[] = {
528 	"aclk_vdpu", "hclk_vdpu",
529 	"aclk_vepu", "hclk_vepu"
530 };
531 
532 static const char * const rockchip_vpu_clk_names[] = {
533 	"aclk", "hclk"
534 };
535 
536 /* VDPU1/VEPU1 */
537 
538 const struct hantro_variant rk3036_vpu_variant = {
539 	.dec_offset = 0x400,
540 	.dec_fmts = rk3066_vpu_dec_fmts,
541 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
542 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
543 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
544 	.postproc_ops = &hantro_g1_postproc_ops,
545 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
546 		 HANTRO_H264_DECODER,
547 	.codec_ops = rk3036_vpu_codec_ops,
548 	.irqs = rockchip_vdpu1_irqs,
549 	.num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
550 	.init = rk3036_vpu_hw_init,
551 	.clk_names = rockchip_vpu_clk_names,
552 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
553 };
554 
555 /*
556  * Despite this variant has separate clocks for decoder and encoder,
557  * it's still required to enable all four of them for either decoding
558  * or encoding and we can't split it in separate g1/h1 variants.
559  */
560 const struct hantro_variant rk3066_vpu_variant = {
561 	.enc_offset = 0x0,
562 	.enc_fmts = rockchip_vpu_enc_fmts,
563 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
564 	.dec_offset = 0x400,
565 	.dec_fmts = rk3066_vpu_dec_fmts,
566 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
567 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
568 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
569 	.postproc_ops = &hantro_g1_postproc_ops,
570 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
571 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
572 	.codec_ops = rk3066_vpu_codec_ops,
573 	.irqs = rockchip_vpu1_irqs,
574 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
575 	.init = rk3066_vpu_hw_init,
576 	.clk_names = rk3066_vpu_clk_names,
577 	.num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
578 };
579 
580 const struct hantro_variant rk3288_vpu_variant = {
581 	.enc_offset = 0x0,
582 	.enc_fmts = rockchip_vpu_enc_fmts,
583 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
584 	.dec_offset = 0x400,
585 	.dec_fmts = rk3288_vpu_dec_fmts,
586 	.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
587 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
588 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
589 	.postproc_ops = &hantro_g1_postproc_ops,
590 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
591 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
592 	.codec_ops = rk3288_vpu_codec_ops,
593 	.irqs = rockchip_vpu1_irqs,
594 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
595 	.init = rockchip_vpu_hw_init,
596 	.clk_names = rockchip_vpu_clk_names,
597 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
598 };
599 
600 /* VDPU2/VEPU2 */
601 
602 const struct hantro_variant rk3328_vpu_variant = {
603 	.dec_offset = 0x400,
604 	.dec_fmts = rockchip_vdpu2_dec_fmts,
605 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
606 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
607 		 HANTRO_H264_DECODER,
608 	.codec_ops = rk3399_vpu_codec_ops,
609 	.irqs = rockchip_vdpu2_irqs,
610 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
611 	.init = rockchip_vpu_hw_init,
612 	.clk_names = rockchip_vpu_clk_names,
613 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
614 };
615 
616 /*
617  * H.264 decoding explicitly disabled in RK3399.
618  * This ensures userspace applications use the Rockchip VDEC core,
619  * which has better performance.
620  */
621 const struct hantro_variant rk3399_vpu_variant = {
622 	.enc_offset = 0x0,
623 	.enc_fmts = rockchip_vpu_enc_fmts,
624 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
625 	.dec_offset = 0x400,
626 	.dec_fmts = rk3399_vpu_dec_fmts,
627 	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
628 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
629 		 HANTRO_VP8_DECODER,
630 	.codec_ops = rk3399_vpu_codec_ops,
631 	.irqs = rockchip_vpu2_irqs,
632 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
633 	.init = rockchip_vpu_hw_init,
634 	.clk_names = rockchip_vpu_clk_names,
635 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
636 };
637 
638 const struct hantro_variant rk3568_vepu_variant = {
639 	.enc_offset = 0x0,
640 	.enc_fmts = rockchip_vpu_enc_fmts,
641 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
642 	.codec = HANTRO_JPEG_ENCODER,
643 	.codec_ops = rk3568_vepu_codec_ops,
644 	.irqs = rk3568_vepu_irqs,
645 	.num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
646 	.init = rockchip_vpu_hw_init,
647 	.clk_names = rockchip_vpu_clk_names,
648 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
649 };
650 
651 const struct hantro_variant rk3568_vpu_variant = {
652 	.dec_offset = 0x400,
653 	.dec_fmts = rockchip_vdpu2_dec_fmts,
654 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
655 	.codec = HANTRO_MPEG2_DECODER |
656 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
657 	.codec_ops = rk3399_vpu_codec_ops,
658 	.irqs = rockchip_vdpu2_irqs,
659 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
660 	.init = rockchip_vpu_hw_init,
661 	.clk_names = rockchip_vpu_clk_names,
662 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
663 };
664 
665 const struct hantro_variant px30_vpu_variant = {
666 	.enc_offset = 0x0,
667 	.enc_fmts = rockchip_vpu_enc_fmts,
668 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
669 	.dec_offset = 0x400,
670 	.dec_fmts = rockchip_vdpu2_dec_fmts,
671 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
672 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
673 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
674 	.codec_ops = rk3399_vpu_codec_ops,
675 	.irqs = rockchip_vpu2_irqs,
676 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
677 	.init = rk3036_vpu_hw_init,
678 	.clk_names = rockchip_vpu_clk_names,
679 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
680 };
681