xref: /linux/drivers/media/platform/verisilicon/rockchip_vpu_hw.c (revision 6e9a12f85a7567bb9a41d5230468886bd6a27b20) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Hantro VPU codec driver
4  *
5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
6  *	Jeffy Chen <jeffy.chen@rock-chips.com>
7  */
8 
9 #include <linux/clk.h>
10 
11 #include "hantro.h"
12 #include "hantro_jpeg.h"
13 #include "hantro_g1_regs.h"
14 #include "hantro_h1_regs.h"
15 #include "rockchip_vpu2_regs.h"
16 #include "rockchip_vpu981_regs.h"
17 
18 #define RK3066_ACLK_MAX_FREQ (300 * 1000 * 1000)
19 #define RK3288_ACLK_MAX_FREQ (400 * 1000 * 1000)
20 
21 #define ROCKCHIP_VPU981_MIN_SIZE 64
22 
23 /*
24  * Supported formats.
25  */
26 
27 static const struct hantro_fmt rockchip_vpu_enc_fmts[] = {
28 	{
29 		.fourcc = V4L2_PIX_FMT_YUV420M,
30 		.codec_mode = HANTRO_MODE_NONE,
31 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P,
32 	},
33 	{
34 		.fourcc = V4L2_PIX_FMT_NV12M,
35 		.codec_mode = HANTRO_MODE_NONE,
36 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP,
37 	},
38 	{
39 		.fourcc = V4L2_PIX_FMT_YUYV,
40 		.codec_mode = HANTRO_MODE_NONE,
41 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422,
42 	},
43 	{
44 		.fourcc = V4L2_PIX_FMT_UYVY,
45 		.codec_mode = HANTRO_MODE_NONE,
46 		.enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422,
47 	},
48 	{
49 		.fourcc = V4L2_PIX_FMT_JPEG,
50 		.codec_mode = HANTRO_MODE_JPEG_ENC,
51 		.max_depth = 2,
52 		.header_size = JPEG_HEADER_SIZE,
53 		.frmsize = {
54 			.min_width = 96,
55 			.max_width = 8192,
56 			.step_width = MB_DIM,
57 			.min_height = 32,
58 			.max_height = 8192,
59 			.step_height = MB_DIM,
60 		},
61 	},
62 };
63 
64 static const struct hantro_fmt rockchip_vpu1_postproc_fmts[] = {
65 	{
66 		.fourcc = V4L2_PIX_FMT_YUYV,
67 		.codec_mode = HANTRO_MODE_NONE,
68 		.postprocessed = true,
69 		.frmsize = {
70 			.min_width = FMT_MIN_WIDTH,
71 			.max_width = FMT_FHD_WIDTH,
72 			.step_width = MB_DIM,
73 			.min_height = FMT_MIN_HEIGHT,
74 			.max_height = FMT_FHD_HEIGHT,
75 			.step_height = MB_DIM,
76 		},
77 	},
78 };
79 
80 static const struct hantro_fmt rockchip_vpu981_postproc_fmts[] = {
81 	{
82 		.fourcc = V4L2_PIX_FMT_NV12,
83 		.codec_mode = HANTRO_MODE_NONE,
84 		.postprocessed = true,
85 		.frmsize = {
86 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
87 			.max_width = FMT_4K_WIDTH,
88 			.step_width = MB_DIM,
89 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
90 			.max_height = FMT_4K_HEIGHT,
91 			.step_height = MB_DIM,
92 		},
93 	},
94 	{
95 		.fourcc = V4L2_PIX_FMT_NV15,
96 		.codec_mode = HANTRO_MODE_NONE,
97 		.match_depth = true,
98 		.postprocessed = true,
99 		.frmsize = {
100 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
101 			.max_width = FMT_4K_WIDTH,
102 			.step_width = MB_DIM,
103 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
104 			.max_height = FMT_4K_HEIGHT,
105 			.step_height = MB_DIM,
106 		},
107 	},
108 	{
109 		.fourcc = V4L2_PIX_FMT_P010,
110 		.codec_mode = HANTRO_MODE_NONE,
111 		.match_depth = true,
112 		.postprocessed = true,
113 		.frmsize = {
114 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
115 			.max_width = FMT_4K_WIDTH,
116 			.step_width = MB_DIM,
117 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
118 			.max_height = FMT_4K_HEIGHT,
119 			.step_height = MB_DIM,
120 		},
121 	},
122 };
123 
124 static const struct hantro_fmt rk3066_vpu_dec_fmts[] = {
125 	{
126 		.fourcc = V4L2_PIX_FMT_NV12,
127 		.codec_mode = HANTRO_MODE_NONE,
128 		.frmsize = {
129 			.min_width = FMT_MIN_WIDTH,
130 			.max_width = FMT_FHD_WIDTH,
131 			.step_width = MB_DIM,
132 			.min_height = FMT_MIN_HEIGHT,
133 			.max_height = FMT_FHD_HEIGHT,
134 			.step_height = MB_DIM,
135 		},
136 	},
137 	{
138 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
139 		.codec_mode = HANTRO_MODE_H264_DEC,
140 		.max_depth = 2,
141 		.frmsize = {
142 			.min_width = FMT_MIN_WIDTH,
143 			.max_width = FMT_FHD_WIDTH,
144 			.step_width = MB_DIM,
145 			.min_height = FMT_MIN_HEIGHT,
146 			.max_height = FMT_FHD_HEIGHT,
147 			.step_height = MB_DIM,
148 		},
149 	},
150 	{
151 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
152 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
153 		.max_depth = 2,
154 		.frmsize = {
155 			.min_width = FMT_MIN_WIDTH,
156 			.max_width = FMT_FHD_WIDTH,
157 			.step_width = MB_DIM,
158 			.min_height = FMT_MIN_HEIGHT,
159 			.max_height = FMT_FHD_HEIGHT,
160 			.step_height = MB_DIM,
161 		},
162 	},
163 	{
164 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
165 		.codec_mode = HANTRO_MODE_VP8_DEC,
166 		.max_depth = 2,
167 		.frmsize = {
168 			.min_width = FMT_MIN_WIDTH,
169 			.max_width = FMT_FHD_WIDTH,
170 			.step_width = MB_DIM,
171 			.min_height = FMT_MIN_HEIGHT,
172 			.max_height = FMT_FHD_HEIGHT,
173 			.step_height = MB_DIM,
174 		},
175 	},
176 };
177 
178 static const struct hantro_fmt rk3288_vpu_dec_fmts[] = {
179 	{
180 		.fourcc = V4L2_PIX_FMT_NV12,
181 		.codec_mode = HANTRO_MODE_NONE,
182 		.frmsize = {
183 			.min_width = FMT_MIN_WIDTH,
184 			.max_width = FMT_4K_WIDTH,
185 			.step_width = MB_DIM,
186 			.min_height = FMT_MIN_HEIGHT,
187 			.max_height = FMT_4K_HEIGHT,
188 			.step_height = MB_DIM,
189 		},
190 	},
191 	{
192 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
193 		.codec_mode = HANTRO_MODE_H264_DEC,
194 		.max_depth = 2,
195 		.frmsize = {
196 			.min_width = FMT_MIN_WIDTH,
197 			.max_width = FMT_4K_WIDTH,
198 			.step_width = MB_DIM,
199 			.min_height = FMT_MIN_HEIGHT,
200 			.max_height = FMT_4K_HEIGHT,
201 			.step_height = MB_DIM,
202 		},
203 	},
204 	{
205 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
206 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
207 		.max_depth = 2,
208 		.frmsize = {
209 			.min_width = FMT_MIN_WIDTH,
210 			.max_width = FMT_FHD_WIDTH,
211 			.step_width = MB_DIM,
212 			.min_height = FMT_MIN_HEIGHT,
213 			.max_height = FMT_FHD_HEIGHT,
214 			.step_height = MB_DIM,
215 		},
216 	},
217 	{
218 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
219 		.codec_mode = HANTRO_MODE_VP8_DEC,
220 		.max_depth = 2,
221 		.frmsize = {
222 			.min_width = FMT_MIN_WIDTH,
223 			.max_width = FMT_UHD_WIDTH,
224 			.step_width = MB_DIM,
225 			.min_height = FMT_MIN_HEIGHT,
226 			.max_height = FMT_UHD_HEIGHT,
227 			.step_height = MB_DIM,
228 		},
229 	},
230 };
231 
232 static const struct hantro_fmt rockchip_vdpu2_dec_fmts[] = {
233 	{
234 		.fourcc = V4L2_PIX_FMT_NV12,
235 		.codec_mode = HANTRO_MODE_NONE,
236 		.frmsize = {
237 			.min_width = FMT_MIN_WIDTH,
238 			.max_width = FMT_FHD_WIDTH,
239 			.step_width = MB_DIM,
240 			.min_height = FMT_MIN_HEIGHT,
241 			.max_height = FMT_FHD_HEIGHT,
242 			.step_height = MB_DIM,
243 		},
244 	},
245 	{
246 		.fourcc = V4L2_PIX_FMT_H264_SLICE,
247 		.codec_mode = HANTRO_MODE_H264_DEC,
248 		.max_depth = 2,
249 		.frmsize = {
250 			.min_width = FMT_MIN_WIDTH,
251 			.max_width = FMT_FHD_WIDTH,
252 			.step_width = MB_DIM,
253 			.min_height = FMT_MIN_HEIGHT,
254 			.max_height = FMT_FHD_HEIGHT,
255 			.step_height = MB_DIM,
256 		},
257 	},
258 	{
259 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
260 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
261 		.max_depth = 2,
262 		.frmsize = {
263 			.min_width = FMT_MIN_WIDTH,
264 			.max_width = FMT_FHD_WIDTH,
265 			.step_width = MB_DIM,
266 			.min_height = FMT_MIN_HEIGHT,
267 			.max_height = FMT_FHD_HEIGHT,
268 			.step_height = MB_DIM,
269 		},
270 	},
271 	{
272 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
273 		.codec_mode = HANTRO_MODE_VP8_DEC,
274 		.max_depth = 2,
275 		.frmsize = {
276 			.min_width = FMT_MIN_WIDTH,
277 			.max_width = FMT_UHD_WIDTH,
278 			.step_width = MB_DIM,
279 			.min_height = FMT_MIN_HEIGHT,
280 			.max_height = FMT_UHD_HEIGHT,
281 			.step_height = MB_DIM,
282 		},
283 	},
284 };
285 
286 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
287 	{
288 		.fourcc = V4L2_PIX_FMT_NV12,
289 		.codec_mode = HANTRO_MODE_NONE,
290 		.frmsize = {
291 			.min_width = FMT_MIN_WIDTH,
292 			.max_width = FMT_FHD_WIDTH,
293 			.step_width = MB_DIM,
294 			.min_height = FMT_MIN_HEIGHT,
295 			.max_height = FMT_FHD_HEIGHT,
296 			.step_height = MB_DIM,
297 		},
298 	},
299 	{
300 		.fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
301 		.codec_mode = HANTRO_MODE_MPEG2_DEC,
302 		.max_depth = 2,
303 		.frmsize = {
304 			.min_width = FMT_MIN_WIDTH,
305 			.max_width = FMT_FHD_WIDTH,
306 			.step_width = MB_DIM,
307 			.min_height = FMT_MIN_HEIGHT,
308 			.max_height = FMT_FHD_HEIGHT,
309 			.step_height = MB_DIM,
310 		},
311 	},
312 	{
313 		.fourcc = V4L2_PIX_FMT_VP8_FRAME,
314 		.codec_mode = HANTRO_MODE_VP8_DEC,
315 		.max_depth = 2,
316 		.frmsize = {
317 			.min_width = FMT_MIN_WIDTH,
318 			.max_width = FMT_UHD_WIDTH,
319 			.step_width = MB_DIM,
320 			.min_height = FMT_MIN_HEIGHT,
321 			.max_height = FMT_UHD_HEIGHT,
322 			.step_height = MB_DIM,
323 		},
324 	},
325 };
326 
327 static const struct hantro_fmt rockchip_vpu981_dec_fmts[] = {
328 	{
329 		.fourcc = V4L2_PIX_FMT_NV12_4L4,
330 		.codec_mode = HANTRO_MODE_NONE,
331 		.match_depth = true,
332 		.frmsize = {
333 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
334 			.max_width = FMT_4K_WIDTH,
335 			.step_width = MB_DIM,
336 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
337 			.max_height = FMT_4K_HEIGHT,
338 			.step_height = MB_DIM,
339 		},
340 	},
341 	{
342 		.fourcc = V4L2_PIX_FMT_NV15_4L4,
343 		.codec_mode = HANTRO_MODE_NONE,
344 		.match_depth = true,
345 		.frmsize = {
346 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
347 			.max_width = FMT_4K_WIDTH,
348 			.step_width = MB_DIM,
349 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
350 			.max_height = FMT_4K_HEIGHT,
351 			.step_height = MB_DIM,
352 		},
353 	},
354 	{
355 		.fourcc = V4L2_PIX_FMT_AV1_FRAME,
356 		.codec_mode = HANTRO_MODE_AV1_DEC,
357 		.max_depth = 2,
358 		.frmsize = {
359 			.min_width = ROCKCHIP_VPU981_MIN_SIZE,
360 			.max_width = FMT_4K_WIDTH,
361 			.step_width = MB_DIM,
362 			.min_height = ROCKCHIP_VPU981_MIN_SIZE,
363 			.max_height = FMT_4K_HEIGHT,
364 			.step_height = MB_DIM,
365 		},
366 	},
367 };
368 
369 static irqreturn_t rockchip_vpu1_vepu_irq(int irq, void *dev_id)
370 {
371 	struct hantro_dev *vpu = dev_id;
372 	enum vb2_buffer_state state;
373 	u32 status;
374 
375 	status = vepu_read(vpu, H1_REG_INTERRUPT);
376 	state = (status & H1_REG_INTERRUPT_FRAME_RDY) ?
377 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
378 
379 	vepu_write(vpu, 0, H1_REG_INTERRUPT);
380 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
381 
382 	hantro_irq_done(vpu, state);
383 
384 	return IRQ_HANDLED;
385 }
386 
387 static irqreturn_t rockchip_vpu2_vdpu_irq(int irq, void *dev_id)
388 {
389 	struct hantro_dev *vpu = dev_id;
390 	enum vb2_buffer_state state;
391 	u32 status;
392 
393 	status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
394 	state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
395 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
396 
397 	vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
398 	vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
399 
400 	hantro_irq_done(vpu, state);
401 
402 	return IRQ_HANDLED;
403 }
404 
405 static irqreturn_t rockchip_vpu2_vepu_irq(int irq, void *dev_id)
406 {
407 	struct hantro_dev *vpu = dev_id;
408 	enum vb2_buffer_state state;
409 	u32 status;
410 
411 	status = vepu_read(vpu, VEPU_REG_INTERRUPT);
412 	state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
413 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
414 
415 	vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
416 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
417 
418 	hantro_irq_done(vpu, state);
419 
420 	return IRQ_HANDLED;
421 }
422 
423 static irqreturn_t rk3588_vpu981_irq(int irq, void *dev_id)
424 {
425 	struct hantro_dev *vpu = dev_id;
426 	enum vb2_buffer_state state;
427 	u32 status;
428 
429 	status = vdpu_read(vpu, AV1_REG_INTERRUPT);
430 	state = (status & AV1_REG_INTERRUPT_DEC_RDY_INT) ?
431 		VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
432 
433 	vdpu_write(vpu, 0, AV1_REG_INTERRUPT);
434 	vdpu_write(vpu, AV1_REG_CONFIG_DEC_CLK_GATE_E, AV1_REG_CONFIG);
435 
436 	hantro_irq_done(vpu, state);
437 
438 	return IRQ_HANDLED;
439 }
440 
441 static int rk3036_vpu_hw_init(struct hantro_dev *vpu)
442 {
443 	/* Bump ACLK to max. possible freq. to improve performance. */
444 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
445 	return 0;
446 }
447 
448 static int rk3066_vpu_hw_init(struct hantro_dev *vpu)
449 {
450 	/* Bump ACLKs to max. possible freq. to improve performance. */
451 	clk_set_rate(vpu->clocks[0].clk, RK3066_ACLK_MAX_FREQ);
452 	clk_set_rate(vpu->clocks[2].clk, RK3066_ACLK_MAX_FREQ);
453 	return 0;
454 }
455 
456 static int rockchip_vpu_hw_init(struct hantro_dev *vpu)
457 {
458 	/* Bump ACLK to max. possible freq. to improve performance. */
459 	clk_set_rate(vpu->clocks[0].clk, RK3288_ACLK_MAX_FREQ);
460 	return 0;
461 }
462 
463 static void rk3066_vpu_dec_reset(struct hantro_ctx *ctx)
464 {
465 	struct hantro_dev *vpu = ctx->dev;
466 
467 	vdpu_write(vpu, G1_REG_INTERRUPT_DEC_IRQ_DIS, G1_REG_INTERRUPT);
468 	vdpu_write(vpu, G1_REG_CONFIG_DEC_CLK_GATE_E, G1_REG_CONFIG);
469 }
470 
471 static void rockchip_vpu1_enc_reset(struct hantro_ctx *ctx)
472 {
473 	struct hantro_dev *vpu = ctx->dev;
474 
475 	vepu_write(vpu, H1_REG_INTERRUPT_DIS_BIT, H1_REG_INTERRUPT);
476 	vepu_write(vpu, 0, H1_REG_ENC_CTRL);
477 	vepu_write(vpu, 0, H1_REG_AXI_CTRL);
478 }
479 
480 static void rockchip_vpu2_dec_reset(struct hantro_ctx *ctx)
481 {
482 	struct hantro_dev *vpu = ctx->dev;
483 
484 	vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
485 	vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
486 	vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
487 }
488 
489 static void rockchip_vpu2_enc_reset(struct hantro_ctx *ctx)
490 {
491 	struct hantro_dev *vpu = ctx->dev;
492 
493 	vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
494 	vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
495 	vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
496 }
497 
498 /*
499  * Supported codec ops.
500  */
501 static const struct hantro_codec_ops rk3036_vpu_codec_ops[] = {
502 	[HANTRO_MODE_H264_DEC] = {
503 		.run = hantro_g1_h264_dec_run,
504 		.reset = hantro_g1_reset,
505 		.init = hantro_h264_dec_init,
506 		.exit = hantro_h264_dec_exit,
507 	},
508 	[HANTRO_MODE_MPEG2_DEC] = {
509 		.run = hantro_g1_mpeg2_dec_run,
510 		.reset = hantro_g1_reset,
511 		.init = hantro_mpeg2_dec_init,
512 		.exit = hantro_mpeg2_dec_exit,
513 	},
514 	[HANTRO_MODE_VP8_DEC] = {
515 		.run = hantro_g1_vp8_dec_run,
516 		.reset = hantro_g1_reset,
517 		.init = hantro_vp8_dec_init,
518 		.exit = hantro_vp8_dec_exit,
519 	},
520 };
521 
522 static const struct hantro_codec_ops rk3066_vpu_codec_ops[] = {
523 	[HANTRO_MODE_JPEG_ENC] = {
524 		.run = hantro_h1_jpeg_enc_run,
525 		.reset = rockchip_vpu1_enc_reset,
526 		.done = hantro_h1_jpeg_enc_done,
527 	},
528 	[HANTRO_MODE_H264_DEC] = {
529 		.run = hantro_g1_h264_dec_run,
530 		.reset = rk3066_vpu_dec_reset,
531 		.init = hantro_h264_dec_init,
532 		.exit = hantro_h264_dec_exit,
533 	},
534 	[HANTRO_MODE_MPEG2_DEC] = {
535 		.run = hantro_g1_mpeg2_dec_run,
536 		.reset = rk3066_vpu_dec_reset,
537 		.init = hantro_mpeg2_dec_init,
538 		.exit = hantro_mpeg2_dec_exit,
539 	},
540 	[HANTRO_MODE_VP8_DEC] = {
541 		.run = hantro_g1_vp8_dec_run,
542 		.reset = rk3066_vpu_dec_reset,
543 		.init = hantro_vp8_dec_init,
544 		.exit = hantro_vp8_dec_exit,
545 	},
546 };
547 
548 static const struct hantro_codec_ops rk3288_vpu_codec_ops[] = {
549 	[HANTRO_MODE_JPEG_ENC] = {
550 		.run = hantro_h1_jpeg_enc_run,
551 		.reset = rockchip_vpu1_enc_reset,
552 		.done = hantro_h1_jpeg_enc_done,
553 	},
554 	[HANTRO_MODE_H264_DEC] = {
555 		.run = hantro_g1_h264_dec_run,
556 		.reset = hantro_g1_reset,
557 		.init = hantro_h264_dec_init,
558 		.exit = hantro_h264_dec_exit,
559 	},
560 	[HANTRO_MODE_MPEG2_DEC] = {
561 		.run = hantro_g1_mpeg2_dec_run,
562 		.reset = hantro_g1_reset,
563 		.init = hantro_mpeg2_dec_init,
564 		.exit = hantro_mpeg2_dec_exit,
565 	},
566 	[HANTRO_MODE_VP8_DEC] = {
567 		.run = hantro_g1_vp8_dec_run,
568 		.reset = hantro_g1_reset,
569 		.init = hantro_vp8_dec_init,
570 		.exit = hantro_vp8_dec_exit,
571 	},
572 };
573 
574 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
575 	[HANTRO_MODE_JPEG_ENC] = {
576 		.run = rockchip_vpu2_jpeg_enc_run,
577 		.reset = rockchip_vpu2_enc_reset,
578 		.done = rockchip_vpu2_jpeg_enc_done,
579 	},
580 	[HANTRO_MODE_H264_DEC] = {
581 		.run = rockchip_vpu2_h264_dec_run,
582 		.reset = rockchip_vpu2_dec_reset,
583 		.init = hantro_h264_dec_init,
584 		.exit = hantro_h264_dec_exit,
585 	},
586 	[HANTRO_MODE_MPEG2_DEC] = {
587 		.run = rockchip_vpu2_mpeg2_dec_run,
588 		.reset = rockchip_vpu2_dec_reset,
589 		.init = hantro_mpeg2_dec_init,
590 		.exit = hantro_mpeg2_dec_exit,
591 	},
592 	[HANTRO_MODE_VP8_DEC] = {
593 		.run = rockchip_vpu2_vp8_dec_run,
594 		.reset = rockchip_vpu2_dec_reset,
595 		.init = hantro_vp8_dec_init,
596 		.exit = hantro_vp8_dec_exit,
597 	},
598 };
599 
600 static const struct hantro_codec_ops rk3568_vepu_codec_ops[] = {
601 	[HANTRO_MODE_JPEG_ENC] = {
602 		.run = rockchip_vpu2_jpeg_enc_run,
603 		.reset = rockchip_vpu2_enc_reset,
604 		.done = rockchip_vpu2_jpeg_enc_done,
605 	},
606 };
607 
608 static const struct hantro_codec_ops rk3588_vpu981_codec_ops[] = {
609 	[HANTRO_MODE_AV1_DEC] = {
610 		.run = rockchip_vpu981_av1_dec_run,
611 		.init = rockchip_vpu981_av1_dec_init,
612 		.exit = rockchip_vpu981_av1_dec_exit,
613 		.done = rockchip_vpu981_av1_dec_done,
614 	},
615 };
616 /*
617  * VPU variant.
618  */
619 
620 static const struct hantro_irq rockchip_vdpu1_irqs[] = {
621 	{ "vdpu", hantro_g1_irq },
622 };
623 
624 static const struct hantro_irq rockchip_vpu1_irqs[] = {
625 	{ "vepu", rockchip_vpu1_vepu_irq },
626 	{ "vdpu", hantro_g1_irq },
627 };
628 
629 static const struct hantro_irq rockchip_vdpu2_irqs[] = {
630 	{ "vdpu", rockchip_vpu2_vdpu_irq },
631 };
632 
633 static const struct hantro_irq rockchip_vpu2_irqs[] = {
634 	{ "vepu", rockchip_vpu2_vepu_irq },
635 	{ "vdpu", rockchip_vpu2_vdpu_irq },
636 };
637 
638 static const struct hantro_irq rk3568_vepu_irqs[] = {
639 	{ "vepu", rockchip_vpu2_vepu_irq },
640 };
641 
642 static const char * const rk3066_vpu_clk_names[] = {
643 	"aclk_vdpu", "hclk_vdpu",
644 	"aclk_vepu", "hclk_vepu"
645 };
646 
647 static const struct hantro_irq rk3588_vpu981_irqs[] = {
648 	{ "vdpu", rk3588_vpu981_irq },
649 };
650 
651 static const char * const rockchip_vpu_clk_names[] = {
652 	"aclk", "hclk"
653 };
654 
655 static const char * const rk3588_vpu981_vpu_clk_names[] = {
656 	"aclk", "hclk",
657 };
658 
659 /* VDPU1/VEPU1 */
660 
661 const struct hantro_variant rk3036_vpu_variant = {
662 	.dec_offset = 0x400,
663 	.dec_fmts = rk3066_vpu_dec_fmts,
664 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
665 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
666 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
667 	.postproc_ops = &hantro_g1_postproc_ops,
668 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
669 		 HANTRO_H264_DECODER,
670 	.codec_ops = rk3036_vpu_codec_ops,
671 	.irqs = rockchip_vdpu1_irqs,
672 	.num_irqs = ARRAY_SIZE(rockchip_vdpu1_irqs),
673 	.init = rk3036_vpu_hw_init,
674 	.clk_names = rockchip_vpu_clk_names,
675 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
676 };
677 
678 /*
679  * Despite this variant has separate clocks for decoder and encoder,
680  * it's still required to enable all four of them for either decoding
681  * or encoding and we can't split it in separate g1/h1 variants.
682  */
683 const struct hantro_variant rk3066_vpu_variant = {
684 	.enc_offset = 0x0,
685 	.enc_fmts = rockchip_vpu_enc_fmts,
686 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
687 	.dec_offset = 0x400,
688 	.dec_fmts = rk3066_vpu_dec_fmts,
689 	.num_dec_fmts = ARRAY_SIZE(rk3066_vpu_dec_fmts),
690 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
691 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
692 	.postproc_ops = &hantro_g1_postproc_ops,
693 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
694 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
695 	.codec_ops = rk3066_vpu_codec_ops,
696 	.irqs = rockchip_vpu1_irqs,
697 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
698 	.init = rk3066_vpu_hw_init,
699 	.clk_names = rk3066_vpu_clk_names,
700 	.num_clocks = ARRAY_SIZE(rk3066_vpu_clk_names)
701 };
702 
703 const struct hantro_variant rk3288_vpu_variant = {
704 	.enc_offset = 0x0,
705 	.enc_fmts = rockchip_vpu_enc_fmts,
706 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
707 	.dec_offset = 0x400,
708 	.dec_fmts = rk3288_vpu_dec_fmts,
709 	.num_dec_fmts = ARRAY_SIZE(rk3288_vpu_dec_fmts),
710 	.postproc_fmts = rockchip_vpu1_postproc_fmts,
711 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu1_postproc_fmts),
712 	.postproc_ops = &hantro_g1_postproc_ops,
713 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
714 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
715 	.codec_ops = rk3288_vpu_codec_ops,
716 	.irqs = rockchip_vpu1_irqs,
717 	.num_irqs = ARRAY_SIZE(rockchip_vpu1_irqs),
718 	.init = rockchip_vpu_hw_init,
719 	.clk_names = rockchip_vpu_clk_names,
720 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
721 };
722 
723 /* VDPU2/VEPU2 */
724 
725 const struct hantro_variant rk3328_vpu_variant = {
726 	.dec_offset = 0x400,
727 	.dec_fmts = rockchip_vdpu2_dec_fmts,
728 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
729 	.codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER |
730 		 HANTRO_H264_DECODER,
731 	.codec_ops = rk3399_vpu_codec_ops,
732 	.irqs = rockchip_vdpu2_irqs,
733 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
734 	.init = rockchip_vpu_hw_init,
735 	.clk_names = rockchip_vpu_clk_names,
736 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names),
737 };
738 
739 /*
740  * H.264 decoding explicitly disabled in RK3399.
741  * This ensures userspace applications use the Rockchip VDEC core,
742  * which has better performance.
743  */
744 const struct hantro_variant rk3399_vpu_variant = {
745 	.enc_offset = 0x0,
746 	.enc_fmts = rockchip_vpu_enc_fmts,
747 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
748 	.dec_offset = 0x400,
749 	.dec_fmts = rk3399_vpu_dec_fmts,
750 	.num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
751 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
752 		 HANTRO_VP8_DECODER,
753 	.codec_ops = rk3399_vpu_codec_ops,
754 	.irqs = rockchip_vpu2_irqs,
755 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
756 	.init = rockchip_vpu_hw_init,
757 	.clk_names = rockchip_vpu_clk_names,
758 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
759 };
760 
761 const struct hantro_variant rk3568_vepu_variant = {
762 	.enc_offset = 0x0,
763 	.enc_fmts = rockchip_vpu_enc_fmts,
764 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
765 	.codec = HANTRO_JPEG_ENCODER,
766 	.codec_ops = rk3568_vepu_codec_ops,
767 	.irqs = rk3568_vepu_irqs,
768 	.num_irqs = ARRAY_SIZE(rk3568_vepu_irqs),
769 	.init = rockchip_vpu_hw_init,
770 	.clk_names = rockchip_vpu_clk_names,
771 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
772 };
773 
774 const struct hantro_variant rk3568_vpu_variant = {
775 	.dec_offset = 0x400,
776 	.dec_fmts = rockchip_vdpu2_dec_fmts,
777 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
778 	.codec = HANTRO_MPEG2_DECODER |
779 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
780 	.codec_ops = rk3399_vpu_codec_ops,
781 	.irqs = rockchip_vdpu2_irqs,
782 	.num_irqs = ARRAY_SIZE(rockchip_vdpu2_irqs),
783 	.init = rockchip_vpu_hw_init,
784 	.clk_names = rockchip_vpu_clk_names,
785 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
786 };
787 
788 const struct hantro_variant px30_vpu_variant = {
789 	.enc_offset = 0x0,
790 	.enc_fmts = rockchip_vpu_enc_fmts,
791 	.num_enc_fmts = ARRAY_SIZE(rockchip_vpu_enc_fmts),
792 	.dec_offset = 0x400,
793 	.dec_fmts = rockchip_vdpu2_dec_fmts,
794 	.num_dec_fmts = ARRAY_SIZE(rockchip_vdpu2_dec_fmts),
795 	.codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER |
796 		 HANTRO_VP8_DECODER | HANTRO_H264_DECODER,
797 	.codec_ops = rk3399_vpu_codec_ops,
798 	.irqs = rockchip_vpu2_irqs,
799 	.num_irqs = ARRAY_SIZE(rockchip_vpu2_irqs),
800 	.init = rk3036_vpu_hw_init,
801 	.clk_names = rockchip_vpu_clk_names,
802 	.num_clocks = ARRAY_SIZE(rockchip_vpu_clk_names)
803 };
804 
805 const struct hantro_variant rk3588_vpu981_variant = {
806 	.dec_offset = 0x0,
807 	.dec_fmts = rockchip_vpu981_dec_fmts,
808 	.num_dec_fmts = ARRAY_SIZE(rockchip_vpu981_dec_fmts),
809 	.postproc_fmts = rockchip_vpu981_postproc_fmts,
810 	.num_postproc_fmts = ARRAY_SIZE(rockchip_vpu981_postproc_fmts),
811 	.postproc_ops = &rockchip_vpu981_postproc_ops,
812 	.codec = HANTRO_AV1_DECODER,
813 	.codec_ops = rk3588_vpu981_codec_ops,
814 	.irqs = rk3588_vpu981_irqs,
815 	.num_irqs = ARRAY_SIZE(rk3588_vpu981_irqs),
816 	.clk_names = rk3588_vpu981_vpu_clk_names,
817 	.num_clocks = ARRAY_SIZE(rk3588_vpu981_vpu_clk_names)
818 };
819