1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Hantro G1 post-processor support 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 */ 7 8 #include <linux/dma-mapping.h> 9 #include <linux/types.h> 10 11 #include "hantro.h" 12 #include "hantro_hw.h" 13 #include "hantro_g1_regs.h" 14 #include "hantro_g2_regs.h" 15 #include "hantro_v4l2.h" 16 17 #define HANTRO_PP_REG_WRITE(vpu, reg_name, val) \ 18 { \ 19 hantro_reg_write(vpu, \ 20 &hantro_g1_postproc_regs.reg_name, \ 21 val); \ 22 } 23 24 #define HANTRO_PP_REG_WRITE_S(vpu, reg_name, val) \ 25 { \ 26 hantro_reg_write_s(vpu, \ 27 &hantro_g1_postproc_regs.reg_name, \ 28 val); \ 29 } 30 31 #define VPU_PP_IN_YUYV 0x0 32 #define VPU_PP_IN_NV12 0x1 33 #define VPU_PP_IN_YUV420 0x2 34 #define VPU_PP_IN_YUV240_TILED 0x5 35 #define VPU_PP_OUT_RGB 0x0 36 #define VPU_PP_OUT_YUYV 0x3 37 38 static const struct hantro_postproc_regs hantro_g1_postproc_regs = { 39 .pipeline_en = {G1_REG_PP_INTERRUPT, 1, 0x1}, 40 .max_burst = {G1_REG_PP_DEV_CONFIG, 0, 0x1f}, 41 .clk_gate = {G1_REG_PP_DEV_CONFIG, 1, 0x1}, 42 .out_swap32 = {G1_REG_PP_DEV_CONFIG, 5, 0x1}, 43 .out_endian = {G1_REG_PP_DEV_CONFIG, 6, 0x1}, 44 .out_luma_base = {G1_REG_PP_OUT_LUMA_BASE, 0, 0xffffffff}, 45 .input_width = {G1_REG_PP_INPUT_SIZE, 0, 0x1ff}, 46 .input_height = {G1_REG_PP_INPUT_SIZE, 9, 0x1ff}, 47 .output_width = {G1_REG_PP_CONTROL, 4, 0x7ff}, 48 .output_height = {G1_REG_PP_CONTROL, 15, 0x7ff}, 49 .input_fmt = {G1_REG_PP_CONTROL, 29, 0x7}, 50 .output_fmt = {G1_REG_PP_CONTROL, 26, 0x7}, 51 .orig_width = {G1_REG_PP_MASK1_ORIG_WIDTH, 23, 0x1ff}, 52 .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff}, 53 }; 54 55 bool hantro_needs_postproc(const struct hantro_ctx *ctx, 56 const struct hantro_fmt *fmt) 57 { 58 if (ctx->is_encoder) 59 return false; 60 return fmt->postprocessed; 61 } 62 63 static void hantro_postproc_g1_enable(struct hantro_ctx *ctx) 64 { 65 struct hantro_dev *vpu = ctx->dev; 66 struct vb2_v4l2_buffer *dst_buf; 67 u32 src_pp_fmt, dst_pp_fmt; 68 dma_addr_t dst_dma; 69 70 /* Turn on pipeline mode. Must be done first. */ 71 HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x1); 72 73 src_pp_fmt = VPU_PP_IN_NV12; 74 75 switch (ctx->vpu_dst_fmt->fourcc) { 76 case V4L2_PIX_FMT_YUYV: 77 dst_pp_fmt = VPU_PP_OUT_YUYV; 78 break; 79 default: 80 WARN(1, "output format %d not supported by the post-processor, this wasn't expected.", 81 ctx->vpu_dst_fmt->fourcc); 82 dst_pp_fmt = 0; 83 break; 84 } 85 86 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 87 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 88 89 HANTRO_PP_REG_WRITE(vpu, clk_gate, 0x1); 90 HANTRO_PP_REG_WRITE(vpu, out_endian, 0x1); 91 HANTRO_PP_REG_WRITE(vpu, out_swap32, 0x1); 92 HANTRO_PP_REG_WRITE(vpu, max_burst, 16); 93 HANTRO_PP_REG_WRITE(vpu, out_luma_base, dst_dma); 94 HANTRO_PP_REG_WRITE(vpu, input_width, MB_WIDTH(ctx->dst_fmt.width)); 95 HANTRO_PP_REG_WRITE(vpu, input_height, MB_HEIGHT(ctx->dst_fmt.height)); 96 HANTRO_PP_REG_WRITE(vpu, input_fmt, src_pp_fmt); 97 HANTRO_PP_REG_WRITE(vpu, output_fmt, dst_pp_fmt); 98 HANTRO_PP_REG_WRITE(vpu, output_width, ctx->dst_fmt.width); 99 HANTRO_PP_REG_WRITE(vpu, output_height, ctx->dst_fmt.height); 100 HANTRO_PP_REG_WRITE(vpu, orig_width, MB_WIDTH(ctx->dst_fmt.width)); 101 HANTRO_PP_REG_WRITE(vpu, display_width, ctx->dst_fmt.width); 102 } 103 104 static int down_scale_factor(struct hantro_ctx *ctx) 105 { 106 if (ctx->src_fmt.width == ctx->dst_fmt.width) 107 return 0; 108 109 return DIV_ROUND_CLOSEST(ctx->src_fmt.width, ctx->dst_fmt.width); 110 } 111 112 static void hantro_postproc_g2_enable(struct hantro_ctx *ctx) 113 { 114 struct hantro_dev *vpu = ctx->dev; 115 struct vb2_v4l2_buffer *dst_buf; 116 int down_scale = down_scale_factor(ctx); 117 int out_depth; 118 size_t chroma_offset; 119 dma_addr_t dst_dma; 120 121 dst_buf = hantro_get_dst_buf(ctx); 122 dst_dma = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 123 chroma_offset = ctx->dst_fmt.plane_fmt[0].bytesperline * 124 ctx->dst_fmt.height; 125 126 if (down_scale) { 127 hantro_reg_write(vpu, &g2_down_scale_e, 1); 128 hantro_reg_write(vpu, &g2_down_scale_y, down_scale >> 2); 129 hantro_reg_write(vpu, &g2_down_scale_x, down_scale >> 2); 130 hantro_write_addr(vpu, G2_DS_DST, dst_dma); 131 hantro_write_addr(vpu, G2_DS_DST_CHR, dst_dma + (chroma_offset >> down_scale)); 132 } else { 133 hantro_write_addr(vpu, G2_RS_OUT_LUMA_ADDR, dst_dma); 134 hantro_write_addr(vpu, G2_RS_OUT_CHROMA_ADDR, dst_dma + chroma_offset); 135 } 136 137 out_depth = hantro_get_format_depth(ctx->dst_fmt.pixelformat); 138 if (ctx->dev->variant->legacy_regs) { 139 u8 pp_shift = 0; 140 141 if (out_depth > 8) 142 pp_shift = 16 - out_depth; 143 144 hantro_reg_write(ctx->dev, &g2_rs_out_bit_depth, out_depth); 145 hantro_reg_write(ctx->dev, &g2_pp_pix_shift, pp_shift); 146 } else { 147 hantro_reg_write(vpu, &g2_output_8_bits, out_depth > 8 ? 0 : 1); 148 hantro_reg_write(vpu, &g2_output_format, out_depth > 8 ? 1 : 0); 149 } 150 hantro_reg_write(vpu, &g2_out_rs_e, 1); 151 } 152 153 static int hantro_postproc_g2_enum_framesizes(struct hantro_ctx *ctx, 154 struct v4l2_frmsizeenum *fsize) 155 { 156 /** 157 * G2 scaler can scale down by 0, 2, 4 or 8 158 * use fsize->index has power of 2 diviser 159 **/ 160 if (fsize->index > 3) 161 return -EINVAL; 162 163 if (!ctx->src_fmt.width || !ctx->src_fmt.height) 164 return -EINVAL; 165 166 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 167 fsize->discrete.width = ctx->src_fmt.width >> fsize->index; 168 fsize->discrete.height = ctx->src_fmt.height >> fsize->index; 169 170 return 0; 171 } 172 173 void hantro_postproc_free(struct hantro_ctx *ctx) 174 { 175 struct hantro_dev *vpu = ctx->dev; 176 unsigned int i; 177 178 for (i = 0; i < VB2_MAX_FRAME; ++i) { 179 struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; 180 181 if (priv->cpu) { 182 dma_free_attrs(vpu->dev, priv->size, priv->cpu, 183 priv->dma, priv->attrs); 184 priv->cpu = NULL; 185 } 186 } 187 } 188 189 int hantro_postproc_alloc(struct hantro_ctx *ctx) 190 { 191 struct hantro_dev *vpu = ctx->dev; 192 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 193 struct vb2_queue *cap_queue = &m2m_ctx->cap_q_ctx.q; 194 unsigned int num_buffers = cap_queue->num_buffers; 195 struct v4l2_pix_format_mplane pix_mp; 196 const struct hantro_fmt *fmt; 197 unsigned int i, buf_size; 198 199 /* this should always pick native format */ 200 fmt = hantro_get_default_fmt(ctx, false, ctx->bit_depth); 201 if (!fmt) 202 return -EINVAL; 203 v4l2_fill_pixfmt_mp(&pix_mp, fmt->fourcc, ctx->src_fmt.width, 204 ctx->src_fmt.height); 205 206 buf_size = pix_mp.plane_fmt[0].sizeimage; 207 if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE) 208 buf_size += hantro_h264_mv_size(pix_mp.width, 209 pix_mp.height); 210 else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME) 211 buf_size += hantro_vp9_mv_size(pix_mp.width, 212 pix_mp.height); 213 else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) 214 buf_size += hantro_hevc_mv_size(pix_mp.width, 215 pix_mp.height); 216 217 for (i = 0; i < num_buffers; ++i) { 218 struct hantro_aux_buf *priv = &ctx->postproc.dec_q[i]; 219 220 /* 221 * The buffers on this queue are meant as intermediate 222 * buffers for the decoder, so no mapping is needed. 223 */ 224 priv->attrs = DMA_ATTR_NO_KERNEL_MAPPING; 225 priv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &priv->dma, 226 GFP_KERNEL, priv->attrs); 227 if (!priv->cpu) 228 return -ENOMEM; 229 priv->size = buf_size; 230 } 231 return 0; 232 } 233 234 static void hantro_postproc_g1_disable(struct hantro_ctx *ctx) 235 { 236 struct hantro_dev *vpu = ctx->dev; 237 238 HANTRO_PP_REG_WRITE_S(vpu, pipeline_en, 0x0); 239 } 240 241 static void hantro_postproc_g2_disable(struct hantro_ctx *ctx) 242 { 243 struct hantro_dev *vpu = ctx->dev; 244 245 hantro_reg_write(vpu, &g2_out_rs_e, 0); 246 } 247 248 void hantro_postproc_disable(struct hantro_ctx *ctx) 249 { 250 struct hantro_dev *vpu = ctx->dev; 251 252 if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->disable) 253 vpu->variant->postproc_ops->disable(ctx); 254 } 255 256 void hantro_postproc_enable(struct hantro_ctx *ctx) 257 { 258 struct hantro_dev *vpu = ctx->dev; 259 260 if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enable) 261 vpu->variant->postproc_ops->enable(ctx); 262 } 263 264 int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx, 265 struct v4l2_frmsizeenum *fsize) 266 { 267 struct hantro_dev *vpu = ctx->dev; 268 269 if (vpu->variant->postproc_ops && vpu->variant->postproc_ops->enum_framesizes) 270 return vpu->variant->postproc_ops->enum_framesizes(ctx, fsize); 271 272 return -EINVAL; 273 } 274 275 const struct hantro_postproc_ops hantro_g1_postproc_ops = { 276 .enable = hantro_postproc_g1_enable, 277 .disable = hantro_postproc_g1_disable, 278 }; 279 280 const struct hantro_postproc_ops hantro_g2_postproc_ops = { 281 .enable = hantro_postproc_g2_enable, 282 .disable = hantro_postproc_g2_disable, 283 .enum_framesizes = hantro_postproc_g2_enum_framesizes, 284 }; 285