1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Hantro VPU codec driver 4 * 5 * Copyright 2018 Google LLC. 6 * Tomasz Figa <tfiga@chromium.org> 7 */ 8 9 #ifndef HANTRO_H1_REGS_H_ 10 #define HANTRO_H1_REGS_H_ 11 12 /* Encoder registers. */ 13 #define H1_REG_INTERRUPT 0x004 14 #define H1_REG_INTERRUPT_FRAME_RDY BIT(2) 15 #define H1_REG_INTERRUPT_DIS_BIT BIT(1) 16 #define H1_REG_INTERRUPT_BIT BIT(0) 17 #define H1_REG_AXI_CTRL 0x008 18 #define H1_REG_AXI_CTRL_OUTPUT_SWAP16 BIT(15) 19 #define H1_REG_AXI_CTRL_INPUT_SWAP16 BIT(14) 20 #define H1_REG_AXI_CTRL_BURST_LEN(x) ((x) << 8) 21 #define H1_REG_AXI_CTRL_GATE_BIT BIT(4) 22 #define H1_REG_AXI_CTRL_OUTPUT_SWAP32 BIT(3) 23 #define H1_REG_AXI_CTRL_INPUT_SWAP32 BIT(2) 24 #define H1_REG_AXI_CTRL_OUTPUT_SWAP8 BIT(1) 25 #define H1_REG_AXI_CTRL_INPUT_SWAP8 BIT(0) 26 #define H1_REG_ADDR_OUTPUT_STREAM 0x014 27 #define H1_REG_ADDR_OUTPUT_CTRL 0x018 28 #define H1_REG_ADDR_REF_LUMA 0x01c 29 #define H1_REG_ADDR_REF_CHROMA 0x020 30 #define H1_REG_ADDR_REC_LUMA 0x024 31 #define H1_REG_ADDR_REC_CHROMA 0x028 32 #define H1_REG_ADDR_IN_PLANE_0 0x02c 33 #define H1_REG_ADDR_IN_PLANE_1 0x030 34 #define H1_REG_ADDR_IN_PLANE_2 0x034 35 #define H1_REG_ENC_CTRL 0x038 36 #define H1_REG_ENC_CTRL_TIMEOUT_EN BIT(31) 37 #define H1_REG_ENC_CTRL_NAL_MODE_BIT BIT(29) 38 #define H1_REG_ENC_CTRL_WIDTH(w) ((w) << 19) 39 #define H1_REG_ENC_CTRL_HEIGHT(h) ((h) << 10) 40 #define H1_REG_ENC_PIC_INTER (0x0 << 3) 41 #define H1_REG_ENC_PIC_INTRA (0x1 << 3) 42 #define H1_REG_ENC_PIC_MVCINTER (0x2 << 3) 43 #define H1_REG_ENC_CTRL_ENC_MODE_H264 (0x3 << 1) 44 #define H1_REG_ENC_CTRL_ENC_MODE_JPEG (0x2 << 1) 45 #define H1_REG_ENC_CTRL_ENC_MODE_VP8 (0x1 << 1) 46 #define H1_REG_ENC_CTRL_EN_BIT BIT(0) 47 #define H1_REG_IN_IMG_CTRL 0x03c 48 #define H1_REG_IN_IMG_CTRL_ROW_LEN(x) ((x) << 12) 49 #define H1_REG_IN_IMG_CTRL_OVRFLR_D4(x) ((x) << 10) 50 #define H1_REG_IN_IMG_CTRL_OVRFLB(x) ((x) << 6) 51 #define H1_REG_IN_IMG_CTRL_FMT(x) ((x) << 2) 52 #define H1_REG_ENC_CTRL0 0x040 53 #define H1_REG_ENC_CTRL0_INIT_QP(x) ((x) << 26) 54 #define H1_REG_ENC_CTRL0_SLICE_ALPHA(x) ((x) << 22) 55 #define H1_REG_ENC_CTRL0_SLICE_BETA(x) ((x) << 18) 56 #define H1_REG_ENC_CTRL0_CHROMA_QP_OFFSET(x) ((x) << 13) 57 #define H1_REG_ENC_CTRL0_FILTER_DIS(x) ((x) << 5) 58 #define H1_REG_ENC_CTRL0_IDR_PICID(x) ((x) << 1) 59 #define H1_REG_ENC_CTRL0_CONSTR_INTRA_PRED BIT(0) 60 #define H1_REG_ENC_CTRL1 0x044 61 #define H1_REG_ENC_CTRL1_PPS_ID(x) ((x) << 24) 62 #define H1_REG_ENC_CTRL1_INTRA_PRED_MODE(x) ((x) << 16) 63 #define H1_REG_ENC_CTRL1_FRAME_NUM(x) ((x)) 64 #define H1_REG_ENC_CTRL2 0x048 65 #define H1_REG_ENC_CTRL2_DEBLOCKING_FILTER_MODE(x) ((x) << 30) 66 #define H1_REG_ENC_CTRL2_H264_SLICE_SIZE(x) ((x) << 23) 67 #define H1_REG_ENC_CTRL2_DISABLE_QUARTER_PIXMV BIT(22) 68 #define H1_REG_ENC_CTRL2_TRANS8X8_MODE_EN BIT(21) 69 #define H1_REG_ENC_CTRL2_CABAC_INIT_IDC(x) ((x) << 19) 70 #define H1_REG_ENC_CTRL2_ENTROPY_CODING_MODE BIT(18) 71 #define H1_REG_ENC_CTRL2_H264_INTER4X4_MODE BIT(17) 72 #define H1_REG_ENC_CTRL2_H264_STREAM_MODE BIT(16) 73 #define H1_REG_ENC_CTRL2_INTRA16X16_MODE(x) ((x)) 74 #define H1_REG_ENC_CTRL3 0x04c 75 #define H1_REG_ENC_CTRL3_MUTIMV_EN BIT(30) 76 #define H1_REG_ENC_CTRL3_MV_PENALTY_1_4P(x) ((x) << 20) 77 #define H1_REG_ENC_CTRL3_MV_PENALTY_4P(x) ((x) << 10) 78 #define H1_REG_ENC_CTRL3_MV_PENALTY_1P(x) ((x)) 79 #define H1_REG_ENC_CTRL4 0x050 80 #define H1_REG_ENC_CTRL4_MV_PENALTY_16X8_8X16(x) ((x) << 20) 81 #define H1_REG_ENC_CTRL4_MV_PENALTY_8X8(x) ((x) << 10) 82 #define H1_REG_ENC_CTRL4_8X4_4X8(x) ((x)) 83 #define H1_REG_ENC_CTRL5 0x054 84 #define H1_REG_ENC_CTRL5_MACROBLOCK_PENALTY(x) ((x) << 24) 85 #define H1_REG_ENC_CTRL5_COMPLETE_SLICES(x) ((x) << 16) 86 #define H1_REG_ENC_CTRL5_INTER_MODE(x) ((x)) 87 #define H1_REG_STR_HDR_REM_MSB 0x058 88 #define H1_REG_STR_HDR_REM_LSB 0x05c 89 #define H1_REG_STR_BUF_LIMIT 0x060 90 #define H1_REG_MAD_CTRL 0x064 91 #define H1_REG_MAD_CTRL_QP_ADJUST(x) ((x) << 28) 92 #define H1_REG_MAD_CTRL_MAD_THRESHOLD(x) ((x) << 22) 93 #define H1_REG_MAD_CTRL_QP_SUM_DIV2(x) ((x)) 94 #define H1_REG_ADDR_VP8_PROB_CNT 0x068 95 #define H1_REG_QP_VAL 0x06c 96 #define H1_REG_QP_VAL_LUM(x) ((x) << 26) 97 #define H1_REG_QP_VAL_MAX(x) ((x) << 20) 98 #define H1_REG_QP_VAL_MIN(x) ((x) << 14) 99 #define H1_REG_QP_VAL_CHECKPOINT_DISTAN(x) ((x)) 100 #define H1_REG_VP8_QP_VAL(i) (0x06c + ((i) * 0x4)) 101 #define H1_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4)) 102 #define H1_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff)) 103 #define H1_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16) 104 #define H1_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \ 105 * (i & 1))) & 0xffff) \ 106 * 32) 107 #define H1_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4)) 108 #define H1_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff)) 109 #define H1_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16) 110 #define H1_REG_VP8_BOOL_ENC 0x08c 111 #define H1_REG_CHKPT_DELTA_QP 0x090 112 #define H1_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0) 113 #define H1_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4) 114 #define H1_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8) 115 #define H1_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12) 116 #define H1_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16) 117 #define H1_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20) 118 #define H1_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24) 119 #define H1_REG_VP8_CTRL0 0x090 120 #define H1_REG_RLC_CTRL 0x094 121 #define H1_REG_RLC_CTRL_STR_OFFS_SHIFT 23 122 #define H1_REG_RLC_CTRL_STR_OFFS_MASK (0x3f << 23) 123 #define H1_REG_RLC_CTRL_RLC_SUM(x) ((x)) 124 #define H1_REG_MB_CTRL 0x098 125 #define H1_REG_MB_CNT_OUT(x) (((x) & 0xffff)) 126 #define H1_REG_MB_CNT_SET(x) (((x) & 0xffff) << 16) 127 #define H1_REG_ADDR_NEXT_PIC 0x09c 128 #define H1_REG_JPEG_LUMA_QUAT(i) (0x100 + ((i) * 0x4)) 129 #define H1_REG_JPEG_CHROMA_QUAT(i) (0x140 + ((i) * 0x4)) 130 #define H1_REG_STABILIZATION_OUTPUT 0x0A0 131 #define H1_REG_ADDR_CABAC_TBL 0x0cc 132 #define H1_REG_ADDR_MV_OUT 0x0d0 133 #define H1_REG_RGB_YUV_COEFF(i) (0x0d4 + ((i) * 0x4)) 134 #define H1_REG_RGB_MASK_MSB 0x0dc 135 #define H1_REG_INTRA_AREA_CTRL 0x0e0 136 #define H1_REG_CIR_INTRA_CTRL 0x0e4 137 #define H1_REG_INTRA_SLICE_BITMAP(i) (0x0e8 + ((i) * 0x4)) 138 #define H1_REG_ADDR_VP8_DCT_PART(i) (0x0e8 + ((i) * 0x4)) 139 #define H1_REG_FIRST_ROI_AREA 0x0f0 140 #define H1_REG_SECOND_ROI_AREA 0x0f4 141 #define H1_REG_MVC_CTRL 0x0f8 142 #define H1_REG_MVC_CTRL_MV16X16_FAVOR(x) ((x) << 28) 143 #define H1_REG_VP8_INTRA_PENALTY(i) (0x100 + ((i) * 0x4)) 144 #define H1_REG_ADDR_VP8_SEG_MAP 0x11c 145 #define H1_REG_VP8_SEG_QP(i) (0x120 + ((i) * 0x4)) 146 #define H1_REG_DMV_4P_1P_PENALTY(i) (0x180 + ((i) * 0x4)) 147 #define H1_REG_DMV_4P_1P_PENALTY_BIT(x, i) ((x) << (i) * 8) 148 #define H1_REG_DMV_QPEL_PENALTY(i) (0x200 + ((i) * 0x4)) 149 #define H1_REG_DMV_QPEL_PENALTY_BIT(x, i) ((x) << (i) * 8) 150 #define H1_REG_VP8_CTRL1 0x280 151 #define H1_REG_VP8_BIT_COST_GOLDEN 0x284 152 #define H1_REG_VP8_LOOP_FLT_DELTA(i) (0x288 + ((i) * 0x4)) 153 154 #endif /* HANTRO_H1_REGS_H_ */ 155