1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI CSI2RX Shim Wrapper Driver 4 * 5 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 * Author: Pratyush Yadav <p.yadav@ti.com> 8 * Author: Jai Luthra <j-luthra@ti.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/dmaengine.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 17 #include <media/mipi-csi2.h> 18 #include <media/v4l2-device.h> 19 #include <media/v4l2-ioctl.h> 20 #include <media/v4l2-mc.h> 21 #include <media/videobuf2-dma-contig.h> 22 23 #define TI_CSI2RX_MODULE_NAME "j721e-csi2rx" 24 25 #define SHIM_CNTL 0x10 26 #define SHIM_CNTL_PIX_RST BIT(0) 27 28 #define SHIM_DMACNTX 0x20 29 #define SHIM_DMACNTX_EN BIT(31) 30 #define SHIM_DMACNTX_YUV422 GENMASK(27, 26) 31 #define SHIM_DMACNTX_SIZE GENMASK(21, 20) 32 #define SHIM_DMACNTX_FMT GENMASK(5, 0) 33 #define SHIM_DMACNTX_YUV422_MODE_11 3 34 #define SHIM_DMACNTX_SIZE_8 0 35 #define SHIM_DMACNTX_SIZE_16 1 36 #define SHIM_DMACNTX_SIZE_32 2 37 38 #define SHIM_PSI_CFG0 0x24 39 #define SHIM_PSI_CFG0_SRC_TAG GENMASK(15, 0) 40 #define SHIM_PSI_CFG0_DST_TAG GENMASK(31, 16) 41 42 #define PSIL_WORD_SIZE_BYTES 16 43 /* 44 * There are no hard limits on the width or height. The DMA engine can handle 45 * all sizes. The max width and height are arbitrary numbers for this driver. 46 * Use 16K * 16K as the arbitrary limit. It is large enough that it is unlikely 47 * the limit will be hit in practice. 48 */ 49 #define MAX_WIDTH_BYTES SZ_16K 50 #define MAX_HEIGHT_LINES SZ_16K 51 52 #define DRAIN_TIMEOUT_MS 50 53 #define DRAIN_BUFFER_SIZE SZ_32K 54 55 struct ti_csi2rx_fmt { 56 u32 fourcc; /* Four character code. */ 57 u32 code; /* Mbus code. */ 58 u32 csi_dt; /* CSI Data type. */ 59 u8 bpp; /* Bits per pixel. */ 60 u8 size; /* Data size shift when unpacking. */ 61 }; 62 63 struct ti_csi2rx_buffer { 64 /* Common v4l2 buffer. Must be first. */ 65 struct vb2_v4l2_buffer vb; 66 struct list_head list; 67 struct ti_csi2rx_dev *csi; 68 }; 69 70 enum ti_csi2rx_dma_state { 71 TI_CSI2RX_DMA_STOPPED, /* Streaming not started yet. */ 72 TI_CSI2RX_DMA_IDLE, /* Streaming but no pending DMA operation. */ 73 TI_CSI2RX_DMA_ACTIVE, /* Streaming and pending DMA operation. */ 74 }; 75 76 struct ti_csi2rx_dma { 77 /* Protects all fields in this struct. */ 78 spinlock_t lock; 79 struct dma_chan *chan; 80 /* Buffers queued to the driver, waiting to be processed by DMA. */ 81 struct list_head queue; 82 enum ti_csi2rx_dma_state state; 83 /* 84 * Queue of buffers submitted to DMA engine. 85 */ 86 struct list_head submitted; 87 /* Buffer to drain stale data from PSI-L endpoint */ 88 struct { 89 void *vaddr; 90 dma_addr_t paddr; 91 size_t len; 92 } drain; 93 }; 94 95 struct ti_csi2rx_dev { 96 struct device *dev; 97 void __iomem *shim; 98 struct v4l2_device v4l2_dev; 99 struct video_device vdev; 100 struct media_device mdev; 101 struct media_pipeline pipe; 102 struct media_pad pad; 103 struct v4l2_async_notifier notifier; 104 struct v4l2_subdev *source; 105 struct vb2_queue vidq; 106 struct mutex mutex; /* To serialize ioctls. */ 107 struct v4l2_format v_fmt; 108 struct ti_csi2rx_dma dma; 109 u32 sequence; 110 }; 111 112 static const struct ti_csi2rx_fmt ti_csi2rx_formats[] = { 113 { 114 .fourcc = V4L2_PIX_FMT_YUYV, 115 .code = MEDIA_BUS_FMT_YUYV8_1X16, 116 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 117 .bpp = 16, 118 .size = SHIM_DMACNTX_SIZE_8, 119 }, { 120 .fourcc = V4L2_PIX_FMT_UYVY, 121 .code = MEDIA_BUS_FMT_UYVY8_1X16, 122 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 123 .bpp = 16, 124 .size = SHIM_DMACNTX_SIZE_8, 125 }, { 126 .fourcc = V4L2_PIX_FMT_YVYU, 127 .code = MEDIA_BUS_FMT_YVYU8_1X16, 128 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 129 .bpp = 16, 130 .size = SHIM_DMACNTX_SIZE_8, 131 }, { 132 .fourcc = V4L2_PIX_FMT_VYUY, 133 .code = MEDIA_BUS_FMT_VYUY8_1X16, 134 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 135 .bpp = 16, 136 .size = SHIM_DMACNTX_SIZE_8, 137 }, { 138 .fourcc = V4L2_PIX_FMT_SBGGR8, 139 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 140 .csi_dt = MIPI_CSI2_DT_RAW8, 141 .bpp = 8, 142 .size = SHIM_DMACNTX_SIZE_8, 143 }, { 144 .fourcc = V4L2_PIX_FMT_SGBRG8, 145 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 146 .csi_dt = MIPI_CSI2_DT_RAW8, 147 .bpp = 8, 148 .size = SHIM_DMACNTX_SIZE_8, 149 }, { 150 .fourcc = V4L2_PIX_FMT_SGRBG8, 151 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 152 .csi_dt = MIPI_CSI2_DT_RAW8, 153 .bpp = 8, 154 .size = SHIM_DMACNTX_SIZE_8, 155 }, { 156 .fourcc = V4L2_PIX_FMT_SRGGB8, 157 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 158 .csi_dt = MIPI_CSI2_DT_RAW8, 159 .bpp = 8, 160 .size = SHIM_DMACNTX_SIZE_8, 161 }, { 162 .fourcc = V4L2_PIX_FMT_SBGGR10, 163 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 164 .csi_dt = MIPI_CSI2_DT_RAW10, 165 .bpp = 16, 166 .size = SHIM_DMACNTX_SIZE_16, 167 }, { 168 .fourcc = V4L2_PIX_FMT_SGBRG10, 169 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 170 .csi_dt = MIPI_CSI2_DT_RAW10, 171 .bpp = 16, 172 .size = SHIM_DMACNTX_SIZE_16, 173 }, { 174 .fourcc = V4L2_PIX_FMT_SGRBG10, 175 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 176 .csi_dt = MIPI_CSI2_DT_RAW10, 177 .bpp = 16, 178 .size = SHIM_DMACNTX_SIZE_16, 179 }, { 180 .fourcc = V4L2_PIX_FMT_SRGGB10, 181 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 182 .csi_dt = MIPI_CSI2_DT_RAW10, 183 .bpp = 16, 184 .size = SHIM_DMACNTX_SIZE_16, 185 }, 186 187 /* More formats can be supported but they are not listed for now. */ 188 }; 189 190 /* Forward declaration needed by ti_csi2rx_dma_callback. */ 191 static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, 192 struct ti_csi2rx_buffer *buf); 193 194 static const struct ti_csi2rx_fmt *find_format_by_fourcc(u32 pixelformat) 195 { 196 unsigned int i; 197 198 for (i = 0; i < ARRAY_SIZE(ti_csi2rx_formats); i++) { 199 if (ti_csi2rx_formats[i].fourcc == pixelformat) 200 return &ti_csi2rx_formats[i]; 201 } 202 203 return NULL; 204 } 205 206 static const struct ti_csi2rx_fmt *find_format_by_code(u32 code) 207 { 208 unsigned int i; 209 210 for (i = 0; i < ARRAY_SIZE(ti_csi2rx_formats); i++) { 211 if (ti_csi2rx_formats[i].code == code) 212 return &ti_csi2rx_formats[i]; 213 } 214 215 return NULL; 216 } 217 218 static void ti_csi2rx_fill_fmt(const struct ti_csi2rx_fmt *csi_fmt, 219 struct v4l2_format *v4l2_fmt) 220 { 221 struct v4l2_pix_format *pix = &v4l2_fmt->fmt.pix; 222 unsigned int pixels_in_word; 223 224 pixels_in_word = PSIL_WORD_SIZE_BYTES * 8 / csi_fmt->bpp; 225 226 /* Clamp width and height to sensible maximums (16K x 16K) */ 227 pix->width = clamp_t(unsigned int, pix->width, 228 pixels_in_word, 229 MAX_WIDTH_BYTES * 8 / csi_fmt->bpp); 230 pix->height = clamp_t(unsigned int, pix->height, 1, MAX_HEIGHT_LINES); 231 232 /* Width should be a multiple of transfer word-size */ 233 pix->width = rounddown(pix->width, pixels_in_word); 234 235 v4l2_fmt->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 236 pix->pixelformat = csi_fmt->fourcc; 237 pix->bytesperline = pix->width * (csi_fmt->bpp / 8); 238 pix->sizeimage = pix->bytesperline * pix->height; 239 } 240 241 static int ti_csi2rx_querycap(struct file *file, void *priv, 242 struct v4l2_capability *cap) 243 { 244 strscpy(cap->driver, TI_CSI2RX_MODULE_NAME, sizeof(cap->driver)); 245 strscpy(cap->card, TI_CSI2RX_MODULE_NAME, sizeof(cap->card)); 246 247 return 0; 248 } 249 250 static int ti_csi2rx_enum_fmt_vid_cap(struct file *file, void *priv, 251 struct v4l2_fmtdesc *f) 252 { 253 const struct ti_csi2rx_fmt *fmt = NULL; 254 255 if (f->mbus_code) { 256 /* 1-to-1 mapping between bus formats and pixel formats */ 257 if (f->index > 0) 258 return -EINVAL; 259 260 fmt = find_format_by_code(f->mbus_code); 261 } else { 262 if (f->index >= ARRAY_SIZE(ti_csi2rx_formats)) 263 return -EINVAL; 264 265 fmt = &ti_csi2rx_formats[f->index]; 266 } 267 268 if (!fmt) 269 return -EINVAL; 270 271 f->pixelformat = fmt->fourcc; 272 memset(f->reserved, 0, sizeof(f->reserved)); 273 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 274 275 return 0; 276 } 277 278 static int ti_csi2rx_g_fmt_vid_cap(struct file *file, void *prov, 279 struct v4l2_format *f) 280 { 281 struct ti_csi2rx_dev *csi = video_drvdata(file); 282 283 *f = csi->v_fmt; 284 285 return 0; 286 } 287 288 static int ti_csi2rx_try_fmt_vid_cap(struct file *file, void *priv, 289 struct v4l2_format *f) 290 { 291 const struct ti_csi2rx_fmt *fmt; 292 293 /* 294 * Default to the first format if the requested pixel format code isn't 295 * supported. 296 */ 297 fmt = find_format_by_fourcc(f->fmt.pix.pixelformat); 298 if (!fmt) 299 fmt = &ti_csi2rx_formats[0]; 300 301 /* Interlaced formats are not supported. */ 302 f->fmt.pix.field = V4L2_FIELD_NONE; 303 304 ti_csi2rx_fill_fmt(fmt, f); 305 306 return 0; 307 } 308 309 static int ti_csi2rx_s_fmt_vid_cap(struct file *file, void *priv, 310 struct v4l2_format *f) 311 { 312 struct ti_csi2rx_dev *csi = video_drvdata(file); 313 struct vb2_queue *q = &csi->vidq; 314 int ret; 315 316 if (vb2_is_busy(q)) 317 return -EBUSY; 318 319 ret = ti_csi2rx_try_fmt_vid_cap(file, priv, f); 320 if (ret < 0) 321 return ret; 322 323 csi->v_fmt = *f; 324 325 return 0; 326 } 327 328 static int ti_csi2rx_enum_framesizes(struct file *file, void *fh, 329 struct v4l2_frmsizeenum *fsize) 330 { 331 const struct ti_csi2rx_fmt *fmt; 332 unsigned int pixels_in_word; 333 334 fmt = find_format_by_fourcc(fsize->pixel_format); 335 if (!fmt || fsize->index != 0) 336 return -EINVAL; 337 338 /* 339 * Number of pixels in one PSI-L word. The transfer happens in multiples 340 * of PSI-L word sizes. 341 */ 342 pixels_in_word = PSIL_WORD_SIZE_BYTES * 8 / fmt->bpp; 343 344 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 345 fsize->stepwise.min_width = pixels_in_word; 346 fsize->stepwise.max_width = rounddown(MAX_WIDTH_BYTES * 8 / fmt->bpp, 347 pixels_in_word); 348 fsize->stepwise.step_width = pixels_in_word; 349 fsize->stepwise.min_height = 1; 350 fsize->stepwise.max_height = MAX_HEIGHT_LINES; 351 fsize->stepwise.step_height = 1; 352 353 return 0; 354 } 355 356 static const struct v4l2_ioctl_ops csi_ioctl_ops = { 357 .vidioc_querycap = ti_csi2rx_querycap, 358 .vidioc_enum_fmt_vid_cap = ti_csi2rx_enum_fmt_vid_cap, 359 .vidioc_try_fmt_vid_cap = ti_csi2rx_try_fmt_vid_cap, 360 .vidioc_g_fmt_vid_cap = ti_csi2rx_g_fmt_vid_cap, 361 .vidioc_s_fmt_vid_cap = ti_csi2rx_s_fmt_vid_cap, 362 .vidioc_enum_framesizes = ti_csi2rx_enum_framesizes, 363 .vidioc_reqbufs = vb2_ioctl_reqbufs, 364 .vidioc_create_bufs = vb2_ioctl_create_bufs, 365 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 366 .vidioc_querybuf = vb2_ioctl_querybuf, 367 .vidioc_qbuf = vb2_ioctl_qbuf, 368 .vidioc_dqbuf = vb2_ioctl_dqbuf, 369 .vidioc_expbuf = vb2_ioctl_expbuf, 370 .vidioc_streamon = vb2_ioctl_streamon, 371 .vidioc_streamoff = vb2_ioctl_streamoff, 372 }; 373 374 static const struct v4l2_file_operations csi_fops = { 375 .owner = THIS_MODULE, 376 .open = v4l2_fh_open, 377 .release = vb2_fop_release, 378 .read = vb2_fop_read, 379 .poll = vb2_fop_poll, 380 .unlocked_ioctl = video_ioctl2, 381 .mmap = vb2_fop_mmap, 382 }; 383 384 static int csi_async_notifier_bound(struct v4l2_async_notifier *notifier, 385 struct v4l2_subdev *subdev, 386 struct v4l2_async_connection *asc) 387 { 388 struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); 389 390 csi->source = subdev; 391 392 return 0; 393 } 394 395 static int csi_async_notifier_complete(struct v4l2_async_notifier *notifier) 396 { 397 struct ti_csi2rx_dev *csi = dev_get_drvdata(notifier->v4l2_dev->dev); 398 struct video_device *vdev = &csi->vdev; 399 int ret; 400 401 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 402 if (ret) 403 return ret; 404 405 ret = v4l2_create_fwnode_links_to_pad(csi->source, &csi->pad, 406 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 407 408 if (ret) { 409 video_unregister_device(vdev); 410 return ret; 411 } 412 413 ret = v4l2_device_register_subdev_nodes(&csi->v4l2_dev); 414 if (ret) 415 video_unregister_device(vdev); 416 417 return ret; 418 } 419 420 static const struct v4l2_async_notifier_operations csi_async_notifier_ops = { 421 .bound = csi_async_notifier_bound, 422 .complete = csi_async_notifier_complete, 423 }; 424 425 static int ti_csi2rx_notifier_register(struct ti_csi2rx_dev *csi) 426 { 427 struct fwnode_handle *fwnode; 428 struct v4l2_async_connection *asc; 429 struct device_node *node; 430 int ret; 431 432 node = of_get_child_by_name(csi->dev->of_node, "csi-bridge"); 433 if (!node) 434 return -EINVAL; 435 436 fwnode = of_fwnode_handle(node); 437 if (!fwnode) { 438 of_node_put(node); 439 return -EINVAL; 440 } 441 442 v4l2_async_nf_init(&csi->notifier, &csi->v4l2_dev); 443 csi->notifier.ops = &csi_async_notifier_ops; 444 445 asc = v4l2_async_nf_add_fwnode(&csi->notifier, fwnode, 446 struct v4l2_async_connection); 447 of_node_put(node); 448 if (IS_ERR(asc)) { 449 v4l2_async_nf_cleanup(&csi->notifier); 450 return PTR_ERR(asc); 451 } 452 453 ret = v4l2_async_nf_register(&csi->notifier); 454 if (ret) { 455 v4l2_async_nf_cleanup(&csi->notifier); 456 return ret; 457 } 458 459 return 0; 460 } 461 462 static void ti_csi2rx_setup_shim(struct ti_csi2rx_dev *csi) 463 { 464 const struct ti_csi2rx_fmt *fmt; 465 unsigned int reg; 466 467 fmt = find_format_by_fourcc(csi->v_fmt.fmt.pix.pixelformat); 468 469 /* De-assert the pixel interface reset. */ 470 reg = SHIM_CNTL_PIX_RST; 471 writel(reg, csi->shim + SHIM_CNTL); 472 473 reg = SHIM_DMACNTX_EN; 474 reg |= FIELD_PREP(SHIM_DMACNTX_FMT, fmt->csi_dt); 475 476 /* 477 * The hardware assumes incoming YUV422 8-bit data on MIPI CSI2 bus 478 * follows the spec and is packed in the order U0 -> Y0 -> V0 -> Y1 -> 479 * ... 480 * 481 * There is an option to swap the bytes around before storing in 482 * memory, to achieve different pixel formats: 483 * 484 * Byte3 <----------- Byte0 485 * [ Y1 ][ V0 ][ Y0 ][ U0 ] MODE 11 486 * [ Y1 ][ U0 ][ Y0 ][ V0 ] MODE 10 487 * [ V0 ][ Y1 ][ U0 ][ Y0 ] MODE 01 488 * [ U0 ][ Y1 ][ V0 ][ Y0 ] MODE 00 489 * 490 * We don't have any requirement to change pixelformat from what is 491 * coming from the source, so we keep it in MODE 11, which does not 492 * swap any bytes when storing in memory. 493 */ 494 switch (fmt->fourcc) { 495 case V4L2_PIX_FMT_UYVY: 496 case V4L2_PIX_FMT_VYUY: 497 case V4L2_PIX_FMT_YUYV: 498 case V4L2_PIX_FMT_YVYU: 499 reg |= FIELD_PREP(SHIM_DMACNTX_YUV422, 500 SHIM_DMACNTX_YUV422_MODE_11); 501 break; 502 default: 503 /* Ignore if not YUV 4:2:2 */ 504 break; 505 } 506 507 reg |= FIELD_PREP(SHIM_DMACNTX_SIZE, fmt->size); 508 509 writel(reg, csi->shim + SHIM_DMACNTX); 510 511 reg = FIELD_PREP(SHIM_PSI_CFG0_SRC_TAG, 0) | 512 FIELD_PREP(SHIM_PSI_CFG0_DST_TAG, 0); 513 writel(reg, csi->shim + SHIM_PSI_CFG0); 514 } 515 516 static void ti_csi2rx_drain_callback(void *param) 517 { 518 struct completion *drain_complete = param; 519 520 complete(drain_complete); 521 } 522 523 /* 524 * Drain the stale data left at the PSI-L endpoint. 525 * 526 * This might happen if no buffers are queued in time but source is still 527 * streaming. In multi-stream scenarios this can happen when one stream is 528 * stopped but other is still streaming, and thus module-level pixel reset is 529 * not asserted. 530 * 531 * To prevent that stale data corrupting the subsequent transactions, it is 532 * required to issue DMA requests to drain it out. 533 */ 534 static int ti_csi2rx_drain_dma(struct ti_csi2rx_dev *csi) 535 { 536 struct dma_async_tx_descriptor *desc; 537 struct completion drain_complete; 538 dma_cookie_t cookie; 539 int ret; 540 541 init_completion(&drain_complete); 542 543 desc = dmaengine_prep_slave_single(csi->dma.chan, csi->dma.drain.paddr, 544 csi->dma.drain.len, DMA_DEV_TO_MEM, 545 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 546 if (!desc) { 547 ret = -EIO; 548 goto out; 549 } 550 551 desc->callback = ti_csi2rx_drain_callback; 552 desc->callback_param = &drain_complete; 553 554 cookie = dmaengine_submit(desc); 555 ret = dma_submit_error(cookie); 556 if (ret) 557 goto out; 558 559 dma_async_issue_pending(csi->dma.chan); 560 561 if (!wait_for_completion_timeout(&drain_complete, 562 msecs_to_jiffies(DRAIN_TIMEOUT_MS))) { 563 dmaengine_terminate_sync(csi->dma.chan); 564 dev_dbg(csi->dev, "DMA transfer timed out for drain buffer\n"); 565 ret = -ETIMEDOUT; 566 goto out; 567 } 568 out: 569 return ret; 570 } 571 572 static void ti_csi2rx_dma_callback(void *param) 573 { 574 struct ti_csi2rx_buffer *buf = param; 575 struct ti_csi2rx_dev *csi = buf->csi; 576 struct ti_csi2rx_dma *dma = &csi->dma; 577 unsigned long flags; 578 579 /* 580 * TODO: Derive the sequence number from the CSI2RX frame number 581 * hardware monitor registers. 582 */ 583 buf->vb.vb2_buf.timestamp = ktime_get_ns(); 584 buf->vb.sequence = csi->sequence++; 585 586 spin_lock_irqsave(&dma->lock, flags); 587 588 WARN_ON(!list_is_first(&buf->list, &dma->submitted)); 589 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 590 list_del(&buf->list); 591 592 /* If there are more buffers to process then start their transfer. */ 593 while (!list_empty(&dma->queue)) { 594 buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); 595 596 if (ti_csi2rx_start_dma(csi, buf)) { 597 dev_err(csi->dev, "Failed to queue the next buffer for DMA\n"); 598 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 599 } else { 600 list_move_tail(&buf->list, &dma->submitted); 601 } 602 } 603 604 if (list_empty(&dma->submitted)) 605 dma->state = TI_CSI2RX_DMA_IDLE; 606 607 spin_unlock_irqrestore(&dma->lock, flags); 608 } 609 610 static int ti_csi2rx_start_dma(struct ti_csi2rx_dev *csi, 611 struct ti_csi2rx_buffer *buf) 612 { 613 unsigned long addr; 614 struct dma_async_tx_descriptor *desc; 615 size_t len = csi->v_fmt.fmt.pix.sizeimage; 616 dma_cookie_t cookie; 617 int ret = 0; 618 619 addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 620 desc = dmaengine_prep_slave_single(csi->dma.chan, addr, len, 621 DMA_DEV_TO_MEM, 622 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 623 if (!desc) 624 return -EIO; 625 626 desc->callback = ti_csi2rx_dma_callback; 627 desc->callback_param = buf; 628 629 cookie = dmaengine_submit(desc); 630 ret = dma_submit_error(cookie); 631 if (ret) 632 return ret; 633 634 dma_async_issue_pending(csi->dma.chan); 635 636 return 0; 637 } 638 639 static void ti_csi2rx_stop_dma(struct ti_csi2rx_dev *csi) 640 { 641 struct ti_csi2rx_dma *dma = &csi->dma; 642 enum ti_csi2rx_dma_state state; 643 unsigned long flags; 644 int ret; 645 646 spin_lock_irqsave(&dma->lock, flags); 647 state = csi->dma.state; 648 dma->state = TI_CSI2RX_DMA_STOPPED; 649 spin_unlock_irqrestore(&dma->lock, flags); 650 651 if (state != TI_CSI2RX_DMA_STOPPED) { 652 /* 653 * Normal DMA termination does not clean up pending data on 654 * the endpoint if multiple streams are running and only one 655 * is stopped, as the module-level pixel reset cannot be 656 * enforced before terminating DMA. 657 */ 658 ret = ti_csi2rx_drain_dma(csi); 659 if (ret && ret != -ETIMEDOUT) 660 dev_warn(csi->dev, 661 "Failed to drain DMA. Next frame might be bogus\n"); 662 } 663 664 ret = dmaengine_terminate_sync(csi->dma.chan); 665 if (ret) 666 dev_err(csi->dev, "Failed to stop DMA: %d\n", ret); 667 } 668 669 static void ti_csi2rx_cleanup_buffers(struct ti_csi2rx_dev *csi, 670 enum vb2_buffer_state state) 671 { 672 struct ti_csi2rx_dma *dma = &csi->dma; 673 struct ti_csi2rx_buffer *buf, *tmp; 674 unsigned long flags; 675 676 spin_lock_irqsave(&dma->lock, flags); 677 list_for_each_entry_safe(buf, tmp, &csi->dma.queue, list) { 678 list_del(&buf->list); 679 vb2_buffer_done(&buf->vb.vb2_buf, state); 680 } 681 list_for_each_entry_safe(buf, tmp, &csi->dma.submitted, list) { 682 list_del(&buf->list); 683 vb2_buffer_done(&buf->vb.vb2_buf, state); 684 } 685 spin_unlock_irqrestore(&dma->lock, flags); 686 } 687 688 static int ti_csi2rx_queue_setup(struct vb2_queue *q, unsigned int *nbuffers, 689 unsigned int *nplanes, unsigned int sizes[], 690 struct device *alloc_devs[]) 691 { 692 struct ti_csi2rx_dev *csi = vb2_get_drv_priv(q); 693 unsigned int size = csi->v_fmt.fmt.pix.sizeimage; 694 695 if (*nplanes) { 696 if (sizes[0] < size) 697 return -EINVAL; 698 size = sizes[0]; 699 } 700 701 *nplanes = 1; 702 sizes[0] = size; 703 704 return 0; 705 } 706 707 static int ti_csi2rx_buffer_prepare(struct vb2_buffer *vb) 708 { 709 struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); 710 unsigned long size = csi->v_fmt.fmt.pix.sizeimage; 711 712 if (vb2_plane_size(vb, 0) < size) { 713 dev_err(csi->dev, "Data will not fit into plane\n"); 714 return -EINVAL; 715 } 716 717 vb2_set_plane_payload(vb, 0, size); 718 return 0; 719 } 720 721 static void ti_csi2rx_buffer_queue(struct vb2_buffer *vb) 722 { 723 struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vb->vb2_queue); 724 struct ti_csi2rx_buffer *buf; 725 struct ti_csi2rx_dma *dma = &csi->dma; 726 bool restart_dma = false; 727 unsigned long flags = 0; 728 int ret; 729 730 buf = container_of(vb, struct ti_csi2rx_buffer, vb.vb2_buf); 731 buf->csi = csi; 732 733 spin_lock_irqsave(&dma->lock, flags); 734 /* 735 * Usually the DMA callback takes care of queueing the pending buffers. 736 * But if DMA has stalled due to lack of buffers, restart it now. 737 */ 738 if (dma->state == TI_CSI2RX_DMA_IDLE) { 739 /* 740 * Do not restart DMA with the lock held because 741 * ti_csi2rx_drain_dma() might block for completion. 742 * There won't be a race on queueing DMA anyway since the 743 * callback is not being fired. 744 */ 745 restart_dma = true; 746 dma->state = TI_CSI2RX_DMA_ACTIVE; 747 } else { 748 list_add_tail(&buf->list, &dma->queue); 749 } 750 spin_unlock_irqrestore(&dma->lock, flags); 751 752 if (restart_dma) { 753 /* 754 * Once frames start dropping, some data gets stuck in the DMA 755 * pipeline somewhere. So the first DMA transfer after frame 756 * drops gives a partial frame. This is obviously not useful to 757 * the application and will only confuse it. Issue a DMA 758 * transaction to drain that up. 759 */ 760 ret = ti_csi2rx_drain_dma(csi); 761 if (ret && ret != -ETIMEDOUT) 762 dev_warn(csi->dev, 763 "Failed to drain DMA. Next frame might be bogus\n"); 764 765 ret = ti_csi2rx_start_dma(csi, buf); 766 if (ret) { 767 dev_err(csi->dev, "Failed to start DMA: %d\n", ret); 768 spin_lock_irqsave(&dma->lock, flags); 769 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 770 dma->state = TI_CSI2RX_DMA_IDLE; 771 spin_unlock_irqrestore(&dma->lock, flags); 772 } else { 773 spin_lock_irqsave(&dma->lock, flags); 774 list_add_tail(&buf->list, &dma->submitted); 775 spin_unlock_irqrestore(&dma->lock, flags); 776 } 777 } 778 } 779 780 static int ti_csi2rx_start_streaming(struct vb2_queue *vq, unsigned int count) 781 { 782 struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); 783 struct ti_csi2rx_dma *dma = &csi->dma; 784 struct ti_csi2rx_buffer *buf; 785 unsigned long flags; 786 int ret = 0; 787 788 spin_lock_irqsave(&dma->lock, flags); 789 if (list_empty(&dma->queue)) 790 ret = -EIO; 791 spin_unlock_irqrestore(&dma->lock, flags); 792 if (ret) 793 return ret; 794 795 ret = video_device_pipeline_start(&csi->vdev, &csi->pipe); 796 if (ret) 797 goto err; 798 799 ti_csi2rx_setup_shim(csi); 800 801 csi->sequence = 0; 802 803 spin_lock_irqsave(&dma->lock, flags); 804 buf = list_entry(dma->queue.next, struct ti_csi2rx_buffer, list); 805 806 ret = ti_csi2rx_start_dma(csi, buf); 807 if (ret) { 808 dev_err(csi->dev, "Failed to start DMA: %d\n", ret); 809 spin_unlock_irqrestore(&dma->lock, flags); 810 goto err_pipeline; 811 } 812 813 list_move_tail(&buf->list, &dma->submitted); 814 dma->state = TI_CSI2RX_DMA_ACTIVE; 815 spin_unlock_irqrestore(&dma->lock, flags); 816 817 ret = v4l2_subdev_call(csi->source, video, s_stream, 1); 818 if (ret) 819 goto err_dma; 820 821 return 0; 822 823 err_dma: 824 ti_csi2rx_stop_dma(csi); 825 err_pipeline: 826 video_device_pipeline_stop(&csi->vdev); 827 writel(0, csi->shim + SHIM_CNTL); 828 writel(0, csi->shim + SHIM_DMACNTX); 829 err: 830 ti_csi2rx_cleanup_buffers(csi, VB2_BUF_STATE_QUEUED); 831 return ret; 832 } 833 834 static void ti_csi2rx_stop_streaming(struct vb2_queue *vq) 835 { 836 struct ti_csi2rx_dev *csi = vb2_get_drv_priv(vq); 837 int ret; 838 839 video_device_pipeline_stop(&csi->vdev); 840 841 writel(0, csi->shim + SHIM_CNTL); 842 writel(0, csi->shim + SHIM_DMACNTX); 843 844 ret = v4l2_subdev_call(csi->source, video, s_stream, 0); 845 if (ret) 846 dev_err(csi->dev, "Failed to stop subdev stream\n"); 847 848 ti_csi2rx_stop_dma(csi); 849 ti_csi2rx_cleanup_buffers(csi, VB2_BUF_STATE_ERROR); 850 } 851 852 static const struct vb2_ops csi_vb2_qops = { 853 .queue_setup = ti_csi2rx_queue_setup, 854 .buf_prepare = ti_csi2rx_buffer_prepare, 855 .buf_queue = ti_csi2rx_buffer_queue, 856 .start_streaming = ti_csi2rx_start_streaming, 857 .stop_streaming = ti_csi2rx_stop_streaming, 858 .wait_prepare = vb2_ops_wait_prepare, 859 .wait_finish = vb2_ops_wait_finish, 860 }; 861 862 static int ti_csi2rx_init_vb2q(struct ti_csi2rx_dev *csi) 863 { 864 struct vb2_queue *q = &csi->vidq; 865 int ret; 866 867 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 868 q->io_modes = VB2_MMAP | VB2_DMABUF; 869 q->drv_priv = csi; 870 q->buf_struct_size = sizeof(struct ti_csi2rx_buffer); 871 q->ops = &csi_vb2_qops; 872 q->mem_ops = &vb2_dma_contig_memops; 873 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 874 q->dev = dmaengine_get_dma_device(csi->dma.chan); 875 q->lock = &csi->mutex; 876 q->min_queued_buffers = 1; 877 878 ret = vb2_queue_init(q); 879 if (ret) 880 return ret; 881 882 csi->vdev.queue = q; 883 884 return 0; 885 } 886 887 static int ti_csi2rx_link_validate(struct media_link *link) 888 { 889 struct media_entity *entity = link->sink->entity; 890 struct video_device *vdev = media_entity_to_video_device(entity); 891 struct ti_csi2rx_dev *csi = container_of(vdev, struct ti_csi2rx_dev, vdev); 892 struct v4l2_pix_format *csi_fmt = &csi->v_fmt.fmt.pix; 893 struct v4l2_subdev_format source_fmt = { 894 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 895 .pad = link->source->index, 896 }; 897 const struct ti_csi2rx_fmt *ti_fmt; 898 int ret; 899 900 ret = v4l2_subdev_call_state_active(csi->source, pad, 901 get_fmt, &source_fmt); 902 if (ret) 903 return ret; 904 905 if (source_fmt.format.width != csi_fmt->width) { 906 dev_dbg(csi->dev, "Width does not match (source %u, sink %u)\n", 907 source_fmt.format.width, csi_fmt->width); 908 return -EPIPE; 909 } 910 911 if (source_fmt.format.height != csi_fmt->height) { 912 dev_dbg(csi->dev, "Height does not match (source %u, sink %u)\n", 913 source_fmt.format.height, csi_fmt->height); 914 return -EPIPE; 915 } 916 917 if (source_fmt.format.field != csi_fmt->field && 918 csi_fmt->field != V4L2_FIELD_NONE) { 919 dev_dbg(csi->dev, "Field does not match (source %u, sink %u)\n", 920 source_fmt.format.field, csi_fmt->field); 921 return -EPIPE; 922 } 923 924 ti_fmt = find_format_by_code(source_fmt.format.code); 925 if (!ti_fmt) { 926 dev_dbg(csi->dev, "Media bus format 0x%x not supported\n", 927 source_fmt.format.code); 928 return -EPIPE; 929 } 930 931 if (ti_fmt->fourcc != csi_fmt->pixelformat) { 932 dev_dbg(csi->dev, 933 "Cannot transform source fmt 0x%x to sink fmt 0x%x\n", 934 ti_fmt->fourcc, csi_fmt->pixelformat); 935 return -EPIPE; 936 } 937 938 return 0; 939 } 940 941 static const struct media_entity_operations ti_csi2rx_video_entity_ops = { 942 .link_validate = ti_csi2rx_link_validate, 943 }; 944 945 static int ti_csi2rx_init_dma(struct ti_csi2rx_dev *csi) 946 { 947 struct dma_slave_config cfg = { 948 .src_addr_width = DMA_SLAVE_BUSWIDTH_16_BYTES, 949 }; 950 int ret; 951 952 INIT_LIST_HEAD(&csi->dma.queue); 953 INIT_LIST_HEAD(&csi->dma.submitted); 954 spin_lock_init(&csi->dma.lock); 955 956 csi->dma.state = TI_CSI2RX_DMA_STOPPED; 957 958 csi->dma.chan = dma_request_chan(csi->dev, "rx0"); 959 if (IS_ERR(csi->dma.chan)) 960 return PTR_ERR(csi->dma.chan); 961 962 ret = dmaengine_slave_config(csi->dma.chan, &cfg); 963 if (ret) { 964 dma_release_channel(csi->dma.chan); 965 return ret; 966 } 967 968 csi->dma.drain.len = DRAIN_BUFFER_SIZE; 969 csi->dma.drain.vaddr = dma_alloc_coherent(csi->dev, csi->dma.drain.len, 970 &csi->dma.drain.paddr, 971 GFP_KERNEL); 972 if (!csi->dma.drain.vaddr) 973 return -ENOMEM; 974 975 return 0; 976 } 977 978 static int ti_csi2rx_v4l2_init(struct ti_csi2rx_dev *csi) 979 { 980 struct media_device *mdev = &csi->mdev; 981 struct video_device *vdev = &csi->vdev; 982 const struct ti_csi2rx_fmt *fmt; 983 struct v4l2_pix_format *pix_fmt = &csi->v_fmt.fmt.pix; 984 int ret; 985 986 fmt = find_format_by_fourcc(V4L2_PIX_FMT_UYVY); 987 if (!fmt) 988 return -EINVAL; 989 990 pix_fmt->width = 640; 991 pix_fmt->height = 480; 992 pix_fmt->field = V4L2_FIELD_NONE; 993 pix_fmt->colorspace = V4L2_COLORSPACE_SRGB; 994 pix_fmt->ycbcr_enc = V4L2_YCBCR_ENC_601, 995 pix_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE, 996 pix_fmt->xfer_func = V4L2_XFER_FUNC_SRGB, 997 998 ti_csi2rx_fill_fmt(fmt, &csi->v_fmt); 999 1000 mdev->dev = csi->dev; 1001 mdev->hw_revision = 1; 1002 strscpy(mdev->model, "TI-CSI2RX", sizeof(mdev->model)); 1003 1004 media_device_init(mdev); 1005 1006 strscpy(vdev->name, TI_CSI2RX_MODULE_NAME, sizeof(vdev->name)); 1007 vdev->v4l2_dev = &csi->v4l2_dev; 1008 vdev->vfl_dir = VFL_DIR_RX; 1009 vdev->fops = &csi_fops; 1010 vdev->ioctl_ops = &csi_ioctl_ops; 1011 vdev->release = video_device_release_empty; 1012 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | 1013 V4L2_CAP_IO_MC; 1014 vdev->lock = &csi->mutex; 1015 video_set_drvdata(vdev, csi); 1016 1017 csi->pad.flags = MEDIA_PAD_FL_SINK; 1018 vdev->entity.ops = &ti_csi2rx_video_entity_ops; 1019 ret = media_entity_pads_init(&csi->vdev.entity, 1, &csi->pad); 1020 if (ret) 1021 return ret; 1022 1023 csi->v4l2_dev.mdev = mdev; 1024 1025 ret = v4l2_device_register(csi->dev, &csi->v4l2_dev); 1026 if (ret) 1027 return ret; 1028 1029 ret = media_device_register(mdev); 1030 if (ret) { 1031 v4l2_device_unregister(&csi->v4l2_dev); 1032 media_device_cleanup(mdev); 1033 return ret; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static void ti_csi2rx_cleanup_dma(struct ti_csi2rx_dev *csi) 1040 { 1041 dma_free_coherent(csi->dev, csi->dma.drain.len, 1042 csi->dma.drain.vaddr, csi->dma.drain.paddr); 1043 csi->dma.drain.vaddr = NULL; 1044 dma_release_channel(csi->dma.chan); 1045 } 1046 1047 static void ti_csi2rx_cleanup_v4l2(struct ti_csi2rx_dev *csi) 1048 { 1049 media_device_unregister(&csi->mdev); 1050 v4l2_device_unregister(&csi->v4l2_dev); 1051 media_device_cleanup(&csi->mdev); 1052 } 1053 1054 static void ti_csi2rx_cleanup_subdev(struct ti_csi2rx_dev *csi) 1055 { 1056 v4l2_async_nf_unregister(&csi->notifier); 1057 v4l2_async_nf_cleanup(&csi->notifier); 1058 } 1059 1060 static void ti_csi2rx_cleanup_vb2q(struct ti_csi2rx_dev *csi) 1061 { 1062 vb2_queue_release(&csi->vidq); 1063 } 1064 1065 static int ti_csi2rx_probe(struct platform_device *pdev) 1066 { 1067 struct ti_csi2rx_dev *csi; 1068 struct resource *res; 1069 int ret; 1070 1071 csi = devm_kzalloc(&pdev->dev, sizeof(*csi), GFP_KERNEL); 1072 if (!csi) 1073 return -ENOMEM; 1074 1075 csi->dev = &pdev->dev; 1076 platform_set_drvdata(pdev, csi); 1077 1078 mutex_init(&csi->mutex); 1079 1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1081 csi->shim = devm_ioremap_resource(&pdev->dev, res); 1082 if (IS_ERR(csi->shim)) { 1083 ret = PTR_ERR(csi->shim); 1084 goto err_mutex; 1085 } 1086 1087 ret = ti_csi2rx_init_dma(csi); 1088 if (ret) 1089 goto err_mutex; 1090 1091 ret = ti_csi2rx_v4l2_init(csi); 1092 if (ret) 1093 goto err_dma; 1094 1095 ret = ti_csi2rx_init_vb2q(csi); 1096 if (ret) 1097 goto err_v4l2; 1098 1099 ret = ti_csi2rx_notifier_register(csi); 1100 if (ret) 1101 goto err_vb2q; 1102 1103 ret = of_platform_populate(csi->dev->of_node, NULL, NULL, csi->dev); 1104 if (ret) { 1105 dev_err(csi->dev, "Failed to create children: %d\n", ret); 1106 goto err_subdev; 1107 } 1108 1109 return 0; 1110 1111 err_subdev: 1112 ti_csi2rx_cleanup_subdev(csi); 1113 err_vb2q: 1114 ti_csi2rx_cleanup_vb2q(csi); 1115 err_v4l2: 1116 ti_csi2rx_cleanup_v4l2(csi); 1117 err_dma: 1118 ti_csi2rx_cleanup_dma(csi); 1119 err_mutex: 1120 mutex_destroy(&csi->mutex); 1121 return ret; 1122 } 1123 1124 static int ti_csi2rx_remove(struct platform_device *pdev) 1125 { 1126 struct ti_csi2rx_dev *csi = platform_get_drvdata(pdev); 1127 1128 video_unregister_device(&csi->vdev); 1129 1130 ti_csi2rx_cleanup_vb2q(csi); 1131 ti_csi2rx_cleanup_subdev(csi); 1132 ti_csi2rx_cleanup_v4l2(csi); 1133 ti_csi2rx_cleanup_dma(csi); 1134 1135 mutex_destroy(&csi->mutex); 1136 1137 return 0; 1138 } 1139 1140 static const struct of_device_id ti_csi2rx_of_match[] = { 1141 { .compatible = "ti,j721e-csi2rx-shim", }, 1142 { }, 1143 }; 1144 MODULE_DEVICE_TABLE(of, ti_csi2rx_of_match); 1145 1146 static struct platform_driver ti_csi2rx_pdrv = { 1147 .probe = ti_csi2rx_probe, 1148 .remove = ti_csi2rx_remove, 1149 .driver = { 1150 .name = TI_CSI2RX_MODULE_NAME, 1151 .of_match_table = ti_csi2rx_of_match, 1152 }, 1153 }; 1154 1155 module_platform_driver(ti_csi2rx_pdrv); 1156 1157 MODULE_DESCRIPTION("TI J721E CSI2 RX Driver"); 1158 MODULE_AUTHOR("Jai Luthra <j-luthra@ti.com>"); 1159 MODULE_LICENSE("GPL"); 1160