xref: /linux/drivers/media/platform/ti/davinci/vpif.h (revision 24168c5e6dfbdd5b414f048f47f75d64533296ca)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * VPIF header file
4  *
5  * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/
6  */
7 
8 #ifndef VPIF_H
9 #define VPIF_H
10 
11 #include <linux/io.h>
12 #include <linux/videodev2.h>
13 #include <media/davinci/vpif_types.h>
14 
15 /* Maximum channel allowed */
16 #define VPIF_NUM_CHANNELS		(4)
17 #define VPIF_CAPTURE_NUM_CHANNELS	(2)
18 #define VPIF_DISPLAY_NUM_CHANNELS	(2)
19 
20 /* Macros to read/write registers */
21 extern void __iomem *vpif_base;
22 extern spinlock_t vpif_lock;
23 
24 #define regr(reg)               readl((reg) + vpif_base)
25 #define regw(value, reg)        writel(value, (reg + vpif_base))
26 
27 /* Register Address Offsets */
28 #define VPIF_PID			(0x0000)
29 #define VPIF_CH0_CTRL			(0x0004)
30 #define VPIF_CH1_CTRL			(0x0008)
31 #define VPIF_CH2_CTRL			(0x000C)
32 #define VPIF_CH3_CTRL			(0x0010)
33 
34 #define VPIF_INTEN			(0x0020)
35 #define VPIF_INTEN_SET			(0x0024)
36 #define VPIF_INTEN_CLR			(0x0028)
37 #define VPIF_STATUS			(0x002C)
38 #define VPIF_STATUS_CLR			(0x0030)
39 #define VPIF_EMULATION_CTRL		(0x0034)
40 #define VPIF_REQ_SIZE			(0x0038)
41 
42 #define VPIF_CH0_TOP_STRT_ADD_LUMA	(0x0040)
43 #define VPIF_CH0_BTM_STRT_ADD_LUMA	(0x0044)
44 #define VPIF_CH0_TOP_STRT_ADD_CHROMA	(0x0048)
45 #define VPIF_CH0_BTM_STRT_ADD_CHROMA	(0x004c)
46 #define VPIF_CH0_TOP_STRT_ADD_HANC	(0x0050)
47 #define VPIF_CH0_BTM_STRT_ADD_HANC	(0x0054)
48 #define VPIF_CH0_TOP_STRT_ADD_VANC	(0x0058)
49 #define VPIF_CH0_BTM_STRT_ADD_VANC	(0x005c)
50 #define VPIF_CH0_SP_CFG			(0x0060)
51 #define VPIF_CH0_IMG_ADD_OFST		(0x0064)
52 #define VPIF_CH0_HANC_ADD_OFST		(0x0068)
53 #define VPIF_CH0_H_CFG			(0x006c)
54 #define VPIF_CH0_V_CFG_00		(0x0070)
55 #define VPIF_CH0_V_CFG_01		(0x0074)
56 #define VPIF_CH0_V_CFG_02		(0x0078)
57 #define VPIF_CH0_V_CFG_03		(0x007c)
58 
59 #define VPIF_CH1_TOP_STRT_ADD_LUMA	(0x0080)
60 #define VPIF_CH1_BTM_STRT_ADD_LUMA	(0x0084)
61 #define VPIF_CH1_TOP_STRT_ADD_CHROMA	(0x0088)
62 #define VPIF_CH1_BTM_STRT_ADD_CHROMA	(0x008c)
63 #define VPIF_CH1_TOP_STRT_ADD_HANC	(0x0090)
64 #define VPIF_CH1_BTM_STRT_ADD_HANC	(0x0094)
65 #define VPIF_CH1_TOP_STRT_ADD_VANC	(0x0098)
66 #define VPIF_CH1_BTM_STRT_ADD_VANC	(0x009c)
67 #define VPIF_CH1_SP_CFG			(0x00a0)
68 #define VPIF_CH1_IMG_ADD_OFST		(0x00a4)
69 #define VPIF_CH1_HANC_ADD_OFST		(0x00a8)
70 #define VPIF_CH1_H_CFG			(0x00ac)
71 #define VPIF_CH1_V_CFG_00		(0x00b0)
72 #define VPIF_CH1_V_CFG_01		(0x00b4)
73 #define VPIF_CH1_V_CFG_02		(0x00b8)
74 #define VPIF_CH1_V_CFG_03		(0x00bc)
75 
76 #define VPIF_CH2_TOP_STRT_ADD_LUMA	(0x00c0)
77 #define VPIF_CH2_BTM_STRT_ADD_LUMA	(0x00c4)
78 #define VPIF_CH2_TOP_STRT_ADD_CHROMA	(0x00c8)
79 #define VPIF_CH2_BTM_STRT_ADD_CHROMA	(0x00cc)
80 #define VPIF_CH2_TOP_STRT_ADD_HANC	(0x00d0)
81 #define VPIF_CH2_BTM_STRT_ADD_HANC	(0x00d4)
82 #define VPIF_CH2_TOP_STRT_ADD_VANC	(0x00d8)
83 #define VPIF_CH2_BTM_STRT_ADD_VANC	(0x00dc)
84 #define VPIF_CH2_SP_CFG			(0x00e0)
85 #define VPIF_CH2_IMG_ADD_OFST		(0x00e4)
86 #define VPIF_CH2_HANC_ADD_OFST		(0x00e8)
87 #define VPIF_CH2_H_CFG			(0x00ec)
88 #define VPIF_CH2_V_CFG_00		(0x00f0)
89 #define VPIF_CH2_V_CFG_01		(0x00f4)
90 #define VPIF_CH2_V_CFG_02		(0x00f8)
91 #define VPIF_CH2_V_CFG_03		(0x00fc)
92 #define VPIF_CH2_HANC0_STRT		(0x0100)
93 #define VPIF_CH2_HANC0_SIZE		(0x0104)
94 #define VPIF_CH2_HANC1_STRT		(0x0108)
95 #define VPIF_CH2_HANC1_SIZE		(0x010c)
96 #define VPIF_CH2_VANC0_STRT		(0x0110)
97 #define VPIF_CH2_VANC0_SIZE		(0x0114)
98 #define VPIF_CH2_VANC1_STRT		(0x0118)
99 #define VPIF_CH2_VANC1_SIZE		(0x011c)
100 
101 #define VPIF_CH3_TOP_STRT_ADD_LUMA	(0x0140)
102 #define VPIF_CH3_BTM_STRT_ADD_LUMA	(0x0144)
103 #define VPIF_CH3_TOP_STRT_ADD_CHROMA	(0x0148)
104 #define VPIF_CH3_BTM_STRT_ADD_CHROMA	(0x014c)
105 #define VPIF_CH3_TOP_STRT_ADD_HANC	(0x0150)
106 #define VPIF_CH3_BTM_STRT_ADD_HANC	(0x0154)
107 #define VPIF_CH3_TOP_STRT_ADD_VANC	(0x0158)
108 #define VPIF_CH3_BTM_STRT_ADD_VANC	(0x015c)
109 #define VPIF_CH3_SP_CFG			(0x0160)
110 #define VPIF_CH3_IMG_ADD_OFST		(0x0164)
111 #define VPIF_CH3_HANC_ADD_OFST		(0x0168)
112 #define VPIF_CH3_H_CFG			(0x016c)
113 #define VPIF_CH3_V_CFG_00		(0x0170)
114 #define VPIF_CH3_V_CFG_01		(0x0174)
115 #define VPIF_CH3_V_CFG_02		(0x0178)
116 #define VPIF_CH3_V_CFG_03		(0x017c)
117 #define VPIF_CH3_HANC0_STRT		(0x0180)
118 #define VPIF_CH3_HANC0_SIZE		(0x0184)
119 #define VPIF_CH3_HANC1_STRT		(0x0188)
120 #define VPIF_CH3_HANC1_SIZE		(0x018c)
121 #define VPIF_CH3_VANC0_STRT		(0x0190)
122 #define VPIF_CH3_VANC0_SIZE		(0x0194)
123 #define VPIF_CH3_VANC1_STRT		(0x0198)
124 #define VPIF_CH3_VANC1_SIZE		(0x019c)
125 
126 #define VPIF_IODFT_CTRL			(0x01c0)
127 
128 /* Functions for bit Manipulation */
129 static inline void vpif_set_bit(u32 reg, u32 bit)
130 {
131 	regw((regr(reg)) | (0x01 << bit), reg);
132 }
133 
134 static inline void vpif_clr_bit(u32 reg, u32 bit)
135 {
136 	regw(((regr(reg)) & ~(0x01 << bit)), reg);
137 }
138 
139 /* Macro for Generating mask */
140 #ifdef GENERATE_MASK
141 #undef GENERATE_MASK
142 #endif
143 
144 #define GENERATE_MASK(bits, pos) \
145 		((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
146 
147 /* Bit positions in the channel control registers */
148 #define VPIF_CH_DATA_MODE_BIT	(2)
149 #define VPIF_CH_YC_MUX_BIT	(3)
150 #define VPIF_CH_SDR_FMT_BIT	(4)
151 #define VPIF_CH_HANC_EN_BIT	(8)
152 #define VPIF_CH_VANC_EN_BIT	(9)
153 
154 #define VPIF_CAPTURE_CH_NIP	(10)
155 #define VPIF_DISPLAY_CH_NIP	(11)
156 
157 #define VPIF_DISPLAY_PIX_EN_BIT	(10)
158 
159 #define VPIF_CH_INPUT_FIELD_FRAME_BIT	(12)
160 
161 #define VPIF_CH_FID_POLARITY_BIT	(15)
162 #define VPIF_CH_V_VALID_POLARITY_BIT	(14)
163 #define VPIF_CH_H_VALID_POLARITY_BIT	(13)
164 #define VPIF_CH_DATA_WIDTH_BIT		(28)
165 
166 #define VPIF_CH_CLK_EDGE_CTRL_BIT	(31)
167 
168 /* Mask various length */
169 #define VPIF_CH_EAVSAV_MASK	GENERATE_MASK(13, 0)
170 #define VPIF_CH_LEN_MASK	GENERATE_MASK(12, 0)
171 #define VPIF_CH_WIDTH_MASK	GENERATE_MASK(13, 0)
172 #define VPIF_CH_LEN_SHIFT	(16)
173 
174 /* VPIF masks for registers */
175 #define VPIF_REQ_SIZE_MASK	(0x1ff)
176 
177 /* bit posotion of interrupt vpif_ch_intr register */
178 #define VPIF_INTEN_FRAME_CH0	(0x00000001)
179 #define VPIF_INTEN_FRAME_CH1	(0x00000002)
180 #define VPIF_INTEN_FRAME_CH2	(0x00000004)
181 #define VPIF_INTEN_FRAME_CH3	(0x00000008)
182 
183 /* bit position of clock and channel enable in vpif_chn_ctrl register */
184 
185 #define VPIF_CH0_CLK_EN		(0x00000002)
186 #define VPIF_CH0_EN		(0x00000001)
187 #define VPIF_CH1_CLK_EN		(0x00000002)
188 #define VPIF_CH1_EN		(0x00000001)
189 #define VPIF_CH2_CLK_EN		(0x00000002)
190 #define VPIF_CH2_EN		(0x00000001)
191 #define VPIF_CH3_CLK_EN		(0x00000002)
192 #define VPIF_CH3_EN		(0x00000001)
193 #define VPIF_CH_CLK_EN		(0x00000002)
194 #define VPIF_CH_EN		(0x00000001)
195 
196 #define VPIF_INT_TOP	(0x00)
197 #define VPIF_INT_BOTTOM	(0x01)
198 #define VPIF_INT_BOTH	(0x02)
199 
200 #define VPIF_CH0_INT_CTRL_SHIFT	(6)
201 #define VPIF_CH1_INT_CTRL_SHIFT	(6)
202 #define VPIF_CH2_INT_CTRL_SHIFT	(6)
203 #define VPIF_CH3_INT_CTRL_SHIFT	(6)
204 #define VPIF_CH_INT_CTRL_SHIFT	(6)
205 
206 #define VPIF_CH2_CLIP_ANC_EN	14
207 #define VPIF_CH2_CLIP_ACTIVE_EN	13
208 
209 #define VPIF_CH3_CLIP_ANC_EN	14
210 #define VPIF_CH3_CLIP_ACTIVE_EN	13
211 
212 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
213 #define channel0_intr_assert()	(regw((regr(VPIF_CH0_CTRL)|\
214 	(VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL))
215 
216 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
217 #define channel1_intr_assert()	(regw((regr(VPIF_CH1_CTRL)|\
218 	(VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL))
219 
220 /* enabled interrupt on both the fields on vpid_ch0_ctrl register */
221 #define channel2_intr_assert()	(regw((regr(VPIF_CH2_CTRL)|\
222 	(VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL))
223 
224 /* enabled interrupt on both the fields on vpid_ch1_ctrl register */
225 #define channel3_intr_assert()	(regw((regr(VPIF_CH3_CTRL)|\
226 	(VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL))
227 
228 #define VPIF_CH_FID_MASK	(0x20)
229 #define VPIF_CH_FID_SHIFT	(5)
230 
231 #define VPIF_NTSC_VBI_START_FIELD0	(1)
232 #define VPIF_NTSC_VBI_START_FIELD1	(263)
233 #define VPIF_PAL_VBI_START_FIELD0	(624)
234 #define VPIF_PAL_VBI_START_FIELD1	(311)
235 
236 #define VPIF_NTSC_HBI_START_FIELD0	(1)
237 #define VPIF_NTSC_HBI_START_FIELD1	(263)
238 #define VPIF_PAL_HBI_START_FIELD0	(624)
239 #define VPIF_PAL_HBI_START_FIELD1	(311)
240 
241 #define VPIF_NTSC_VBI_COUNT_FIELD0	(20)
242 #define VPIF_NTSC_VBI_COUNT_FIELD1	(19)
243 #define VPIF_PAL_VBI_COUNT_FIELD0	(24)
244 #define VPIF_PAL_VBI_COUNT_FIELD1	(25)
245 
246 #define VPIF_NTSC_HBI_COUNT_FIELD0	(263)
247 #define VPIF_NTSC_HBI_COUNT_FIELD1	(262)
248 #define VPIF_PAL_HBI_COUNT_FIELD0	(312)
249 #define VPIF_PAL_HBI_COUNT_FIELD1	(313)
250 
251 #define VPIF_NTSC_VBI_SAMPLES_PER_LINE	(720)
252 #define VPIF_PAL_VBI_SAMPLES_PER_LINE	(720)
253 #define VPIF_NTSC_HBI_SAMPLES_PER_LINE	(268)
254 #define VPIF_PAL_HBI_SAMPLES_PER_LINE	(280)
255 
256 #define VPIF_CH_VANC_EN			(0x20)
257 #define VPIF_DMA_REQ_SIZE		(0x080)
258 #define VPIF_EMULATION_DISABLE		(0x01)
259 
260 extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS];
261 
262 /* inline function to enable/disable channel0 */
263 static inline void enable_channel0(int enable)
264 {
265 	if (enable)
266 		regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
267 	else
268 		regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
269 }
270 
271 /* inline function to enable/disable channel1 */
272 static inline void enable_channel1(int enable)
273 {
274 	if (enable)
275 		regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
276 	else
277 		regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
278 }
279 
280 /* inline function to enable interrupt for channel0 */
281 static inline void channel0_intr_enable(int enable)
282 {
283 	unsigned long flags;
284 
285 	spin_lock_irqsave(&vpif_lock, flags);
286 
287 	if (enable) {
288 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
289 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
290 
291 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
292 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
293 							VPIF_INTEN_SET);
294 	} else {
295 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
296 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
297 							VPIF_INTEN_SET);
298 	}
299 	spin_unlock_irqrestore(&vpif_lock, flags);
300 }
301 
302 /* inline function to enable interrupt for channel1 */
303 static inline void channel1_intr_enable(int enable)
304 {
305 	unsigned long flags;
306 
307 	spin_lock_irqsave(&vpif_lock, flags);
308 
309 	if (enable) {
310 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
311 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
312 
313 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
314 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
315 							VPIF_INTEN_SET);
316 	} else {
317 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
318 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
319 							VPIF_INTEN_SET);
320 	}
321 	spin_unlock_irqrestore(&vpif_lock, flags);
322 }
323 
324 /* inline function to set buffer addresses in case of Y/C non mux mode */
325 static inline void ch0_set_video_buf_addr_yc_nmux(unsigned long top_strt_luma,
326 						  unsigned long btm_strt_luma,
327 						  unsigned long top_strt_chroma,
328 						  unsigned long btm_strt_chroma)
329 {
330 	regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
331 	regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
332 	regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
333 	regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
334 }
335 
336 /* inline function to set buffer addresses in VPIF registers for video data */
337 static inline void ch0_set_video_buf_addr(unsigned long top_strt_luma,
338 					  unsigned long btm_strt_luma,
339 					  unsigned long top_strt_chroma,
340 					  unsigned long btm_strt_chroma)
341 {
342 	regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
343 	regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
344 	regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA);
345 	regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA);
346 }
347 
348 static inline void ch1_set_video_buf_addr(unsigned long top_strt_luma,
349 					  unsigned long btm_strt_luma,
350 					  unsigned long top_strt_chroma,
351 					  unsigned long btm_strt_chroma)
352 {
353 
354 	regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA);
355 	regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA);
356 	regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
357 	regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
358 }
359 
360 static inline void ch0_set_vbi_addr(unsigned long top_vbi,
361 	unsigned long btm_vbi, unsigned long a, unsigned long b)
362 {
363 	regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC);
364 	regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC);
365 }
366 
367 static inline void ch0_set_hbi_addr(unsigned long top_vbi,
368 	unsigned long btm_vbi, unsigned long a, unsigned long b)
369 {
370 	regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC);
371 	regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC);
372 }
373 
374 static inline void ch1_set_vbi_addr(unsigned long top_vbi,
375 	unsigned long btm_vbi, unsigned long a, unsigned long b)
376 {
377 	regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC);
378 	regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC);
379 }
380 
381 static inline void ch1_set_hbi_addr(unsigned long top_vbi,
382 	unsigned long btm_vbi, unsigned long a, unsigned long b)
383 {
384 	regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC);
385 	regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC);
386 }
387 
388 /* Inline function to enable raw vbi in the given channel */
389 static inline void disable_raw_feature(u8 channel_id, u8 index)
390 {
391 	u32 ctrl_reg;
392 	if (0 == channel_id)
393 		ctrl_reg = VPIF_CH0_CTRL;
394 	else
395 		ctrl_reg = VPIF_CH1_CTRL;
396 
397 	if (1 == index)
398 		vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
399 	else
400 		vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
401 }
402 
403 static inline void enable_raw_feature(u8 channel_id, u8 index)
404 {
405 	u32 ctrl_reg;
406 	if (0 == channel_id)
407 		ctrl_reg = VPIF_CH0_CTRL;
408 	else
409 		ctrl_reg = VPIF_CH1_CTRL;
410 
411 	if (1 == index)
412 		vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
413 	else
414 		vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
415 }
416 
417 /* inline function to enable/disable channel2 */
418 static inline void enable_channel2(int enable)
419 {
420 	if (enable) {
421 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
422 		regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
423 	} else {
424 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
425 		regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
426 	}
427 }
428 
429 /* inline function to enable/disable channel3 */
430 static inline void enable_channel3(int enable)
431 {
432 	if (enable) {
433 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
434 		regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
435 	} else {
436 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
437 		regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
438 	}
439 }
440 
441 /* inline function to enable interrupt for channel2 */
442 static inline void channel2_intr_enable(int enable)
443 {
444 	unsigned long flags;
445 
446 	spin_lock_irqsave(&vpif_lock, flags);
447 
448 	if (enable) {
449 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
450 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
451 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
452 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
453 							VPIF_INTEN_SET);
454 	} else {
455 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
456 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
457 							VPIF_INTEN_SET);
458 	}
459 	spin_unlock_irqrestore(&vpif_lock, flags);
460 }
461 
462 /* inline function to enable interrupt for channel3 */
463 static inline void channel3_intr_enable(int enable)
464 {
465 	unsigned long flags;
466 
467 	spin_lock_irqsave(&vpif_lock, flags);
468 
469 	if (enable) {
470 		regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
471 		regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
472 
473 		regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
474 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
475 							VPIF_INTEN_SET);
476 	} else {
477 		regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
478 		regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
479 							VPIF_INTEN_SET);
480 	}
481 	spin_unlock_irqrestore(&vpif_lock, flags);
482 }
483 
484 /* inline function to enable raw vbi data for channel2 */
485 static inline void channel2_raw_enable(int enable, u8 index)
486 {
487 	u32 mask;
488 
489 	if (1 == index)
490 		mask = VPIF_CH_VANC_EN_BIT;
491 	else
492 		mask = VPIF_CH_HANC_EN_BIT;
493 
494 	if (enable)
495 		vpif_set_bit(VPIF_CH2_CTRL, mask);
496 	else
497 		vpif_clr_bit(VPIF_CH2_CTRL, mask);
498 }
499 
500 /* inline function to enable raw vbi data for channel3*/
501 static inline void channel3_raw_enable(int enable, u8 index)
502 {
503 	u32 mask;
504 
505 	if (1 == index)
506 		mask = VPIF_CH_VANC_EN_BIT;
507 	else
508 		mask = VPIF_CH_HANC_EN_BIT;
509 
510 	if (enable)
511 		vpif_set_bit(VPIF_CH3_CTRL, mask);
512 	else
513 		vpif_clr_bit(VPIF_CH3_CTRL, mask);
514 }
515 
516 /* function to enable clipping (for both active and blanking regions) on ch 2 */
517 static inline void channel2_clipping_enable(int enable)
518 {
519 	if (enable) {
520 		vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN);
521 		vpif_set_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN);
522 	} else {
523 		vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ANC_EN);
524 		vpif_clr_bit(VPIF_CH2_CTRL, VPIF_CH2_CLIP_ACTIVE_EN);
525 	}
526 }
527 
528 /* function to enable clipping (for both active and blanking regions) on ch 3 */
529 static inline void channel3_clipping_enable(int enable)
530 {
531 	if (enable) {
532 		vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN);
533 		vpif_set_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN);
534 	} else {
535 		vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ANC_EN);
536 		vpif_clr_bit(VPIF_CH3_CTRL, VPIF_CH3_CLIP_ACTIVE_EN);
537 	}
538 }
539 
540 /* inline function to set buffer addresses in case of Y/C non mux mode */
541 static inline void ch2_set_video_buf_addr_yc_nmux(unsigned long top_strt_luma,
542 						  unsigned long btm_strt_luma,
543 						  unsigned long top_strt_chroma,
544 						  unsigned long btm_strt_chroma)
545 {
546 	regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
547 	regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
548 	regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
549 	regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
550 }
551 
552 /* inline function to set buffer addresses in VPIF registers for video data */
553 static inline void ch2_set_video_buf_addr(unsigned long top_strt_luma,
554 					  unsigned long btm_strt_luma,
555 					  unsigned long top_strt_chroma,
556 					  unsigned long btm_strt_chroma)
557 {
558 	regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
559 	regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
560 	regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA);
561 	regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA);
562 }
563 
564 static inline void ch3_set_video_buf_addr(unsigned long top_strt_luma,
565 					  unsigned long btm_strt_luma,
566 					  unsigned long top_strt_chroma,
567 					  unsigned long btm_strt_chroma)
568 {
569 	regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA);
570 	regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA);
571 	regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
572 	regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
573 }
574 
575 /* inline function to set buffer addresses in VPIF registers for vbi data */
576 static inline void ch2_set_vbi_addr(unsigned long top_strt_luma,
577 				    unsigned long btm_strt_luma,
578 				    unsigned long top_strt_chroma,
579 				    unsigned long btm_strt_chroma)
580 {
581 	regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC);
582 	regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC);
583 }
584 
585 static inline void ch3_set_vbi_addr(unsigned long top_strt_luma,
586 				    unsigned long btm_strt_luma,
587 				    unsigned long top_strt_chroma,
588 				    unsigned long btm_strt_chroma)
589 {
590 	regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC);
591 	regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC);
592 }
593 
594 static inline int vpif_intr_status(int channel)
595 {
596 	int status = 0;
597 	int mask;
598 
599 	if (channel < 0 || channel > 3)
600 		return 0;
601 
602 	mask = 1 << channel;
603 	status = regr(VPIF_STATUS) & mask;
604 	regw(status, VPIF_STATUS_CLR);
605 
606 	return status;
607 }
608 
609 #define VPIF_MAX_NAME	(30)
610 
611 /* This structure will store size parameters as per the mode selected by user */
612 struct vpif_channel_config_params {
613 	char name[VPIF_MAX_NAME];	/* Name of the mode */
614 	u16 width;			/* Indicates width of the image */
615 	u16 height;			/* Indicates height of the image */
616 	u8 frm_fmt;			/* Interlaced (0) or progressive (1) */
617 	u8 ycmux_mode;			/* This mode requires one (0) or two (1)
618 					   channels */
619 	u16 eav2sav;			/* length of eav 2 sav */
620 	u16 sav2eav;			/* length of sav 2 eav */
621 	u16 l1, l3, l5, l7, l9, l11;	/* Other parameter configurations */
622 	u16 vsize;			/* Vertical size of the image */
623 	u8 capture_format;		/* Indicates whether capture format
624 					 * is in BT or in CCD/CMOS */
625 	u8  vbi_supported;		/* Indicates whether this mode
626 					 * supports capturing vbi or not */
627 	u8 hd_sd;			/* HDTV (1) or SDTV (0) format */
628 	v4l2_std_id stdid;		/* SDTV format */
629 	struct v4l2_dv_timings dv_timings;	/* HDTV format */
630 };
631 
632 extern const unsigned int vpif_ch_params_count;
633 extern const struct vpif_channel_config_params vpif_ch_params[];
634 
635 struct vpif_video_params;
636 struct vpif_params;
637 struct vpif_vbi_params;
638 
639 int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id);
640 void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
641 							u8 channel_id);
642 int vpif_channel_getfid(u8 channel_id);
643 
644 enum data_size {
645 	_8BITS = 0,
646 	_10BITS,
647 	_12BITS,
648 };
649 
650 /* Structure for vpif parameters for raw vbi data */
651 struct vpif_vbi_params {
652 	__u32 hstart0;  /* Horizontal start of raw vbi data for first field */
653 	__u32 vstart0;  /* Vertical start of raw vbi data for first field */
654 	__u32 hsize0;   /* Horizontal size of raw vbi data for first field */
655 	__u32 vsize0;   /* Vertical size of raw vbi data for first field */
656 	__u32 hstart1;  /* Horizontal start of raw vbi data for second field */
657 	__u32 vstart1;  /* Vertical start of raw vbi data for second field */
658 	__u32 hsize1;   /* Horizontal size of raw vbi data for second field */
659 	__u32 vsize1;   /* Vertical size of raw vbi data for second field */
660 };
661 
662 /* structure for vpif parameters */
663 struct vpif_video_params {
664 	__u8 storage_mode;	/* Indicates field or frame mode */
665 	unsigned long hpitch;
666 	v4l2_std_id stdid;
667 };
668 
669 struct vpif_params {
670 	struct vpif_interface iface;
671 	struct vpif_video_params video_params;
672 	struct vpif_channel_config_params std_info;
673 	union param {
674 		struct vpif_vbi_params	vbi_params;
675 		enum data_size data_sz;
676 	} params;
677 };
678 
679 #endif				/* End of #ifndef VPIF_H */
680