1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * TI Camera Access Layer (CAL) - CAMERARX 4 * 5 * Copyright (c) 2015-2020 Texas Instruments Inc. 6 * 7 * Authors: 8 * Benoit Parrot <bparrot@ti.com> 9 * Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/module.h> 16 #include <linux/of_graph.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/slab.h> 20 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-subdev.h> 24 25 #include "cal.h" 26 #include "cal_regs.h" 27 28 /* ------------------------------------------------------------------ 29 * I/O Register Accessors 30 * ------------------------------------------------------------------ 31 */ 32 33 static inline u32 camerarx_read(struct cal_camerarx *phy, u32 offset) 34 { 35 return ioread32(phy->base + offset); 36 } 37 38 static inline void camerarx_write(struct cal_camerarx *phy, u32 offset, u32 val) 39 { 40 iowrite32(val, phy->base + offset); 41 } 42 43 /* ------------------------------------------------------------------ 44 * CAMERARX Management 45 * ------------------------------------------------------------------ 46 */ 47 48 static s64 cal_camerarx_get_ext_link_freq(struct cal_camerarx *phy) 49 { 50 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2 = &phy->endpoint.bus.mipi_csi2; 51 u32 num_lanes = mipi_csi2->num_data_lanes; 52 const struct cal_format_info *fmtinfo; 53 struct v4l2_subdev_state *state; 54 struct v4l2_mbus_framefmt *fmt; 55 u32 bpp; 56 s64 freq; 57 58 state = v4l2_subdev_get_locked_active_state(&phy->subdev); 59 60 fmt = v4l2_subdev_state_get_format(state, CAL_CAMERARX_PAD_SINK); 61 62 fmtinfo = cal_format_by_code(fmt->code); 63 if (!fmtinfo) 64 return -EINVAL; 65 66 bpp = fmtinfo->bpp; 67 68 freq = v4l2_get_link_freq(&phy->source->entity.pads[phy->source_pad], 69 bpp, 2 * num_lanes); 70 if (freq < 0) { 71 phy_err(phy, "failed to get link freq for subdev '%s'\n", 72 phy->source->name); 73 return freq; 74 } 75 76 phy_dbg(3, phy, "Source Link Freq: %llu\n", freq); 77 78 return freq; 79 } 80 81 static void cal_camerarx_lane_config(struct cal_camerarx *phy) 82 { 83 u32 val = cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance)); 84 u32 lane_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK; 85 u32 polarity_mask = CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK; 86 struct v4l2_mbus_config_mipi_csi2 *mipi_csi2 = 87 &phy->endpoint.bus.mipi_csi2; 88 int lane; 89 90 cal_set_field(&val, mipi_csi2->clock_lane + 1, lane_mask); 91 cal_set_field(&val, mipi_csi2->lane_polarities[0], polarity_mask); 92 for (lane = 0; lane < mipi_csi2->num_data_lanes; lane++) { 93 /* 94 * Every lane are one nibble apart starting with the 95 * clock followed by the data lanes so shift masks by 4. 96 */ 97 lane_mask <<= 4; 98 polarity_mask <<= 4; 99 cal_set_field(&val, mipi_csi2->data_lanes[lane] + 1, lane_mask); 100 cal_set_field(&val, mipi_csi2->lane_polarities[lane + 1], 101 polarity_mask); 102 } 103 104 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), val); 105 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x\n", 106 phy->instance, val); 107 } 108 109 static void cal_camerarx_enable(struct cal_camerarx *phy) 110 { 111 u32 num_lanes = phy->cal->data->camerarx[phy->instance].num_lanes; 112 113 regmap_field_write(phy->fields[F_CAMMODE], 0); 114 /* Always enable all lanes at the phy control level */ 115 regmap_field_write(phy->fields[F_LANEENABLE], (1 << num_lanes) - 1); 116 /* F_CSI_MODE is not present on every architecture */ 117 if (phy->fields[F_CSI_MODE]) 118 regmap_field_write(phy->fields[F_CSI_MODE], 1); 119 regmap_field_write(phy->fields[F_CTRLCLKEN], 1); 120 } 121 122 void cal_camerarx_disable(struct cal_camerarx *phy) 123 { 124 regmap_field_write(phy->fields[F_CTRLCLKEN], 0); 125 } 126 127 /* 128 * TCLK values are OK at their reset values 129 */ 130 #define TCLK_TERM 0 131 #define TCLK_MISS 1 132 #define TCLK_SETTLE 14 133 134 static void cal_camerarx_config(struct cal_camerarx *phy, s64 link_freq) 135 { 136 unsigned int reg0, reg1; 137 unsigned int ths_term, ths_settle; 138 139 /* DPHY timing configuration */ 140 141 /* THS_TERM: Programmed value = floor(20 ns/DDRClk period) */ 142 ths_term = div_s64(20 * link_freq, 1000 * 1000 * 1000); 143 phy_dbg(1, phy, "ths_term: %d (0x%02x)\n", ths_term, ths_term); 144 145 /* THS_SETTLE: Programmed value = floor(105 ns/DDRClk period) + 4 */ 146 ths_settle = div_s64(105 * link_freq, 1000 * 1000 * 1000) + 4; 147 phy_dbg(1, phy, "ths_settle: %d (0x%02x)\n", ths_settle, ths_settle); 148 149 reg0 = camerarx_read(phy, CAL_CSI2_PHY_REG0); 150 cal_set_field(®0, CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE, 151 CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK); 152 cal_set_field(®0, ths_term, CAL_CSI2_PHY_REG0_THS_TERM_MASK); 153 cal_set_field(®0, ths_settle, CAL_CSI2_PHY_REG0_THS_SETTLE_MASK); 154 155 phy_dbg(1, phy, "CSI2_%d_REG0 = 0x%08x\n", phy->instance, reg0); 156 camerarx_write(phy, CAL_CSI2_PHY_REG0, reg0); 157 158 reg1 = camerarx_read(phy, CAL_CSI2_PHY_REG1); 159 cal_set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK); 160 cal_set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK); 161 cal_set_field(®1, TCLK_MISS, 162 CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK); 163 cal_set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK); 164 165 phy_dbg(1, phy, "CSI2_%d_REG1 = 0x%08x\n", phy->instance, reg1); 166 camerarx_write(phy, CAL_CSI2_PHY_REG1, reg1); 167 } 168 169 static void cal_camerarx_power(struct cal_camerarx *phy, bool enable) 170 { 171 u32 target_state; 172 unsigned int i; 173 174 target_state = enable ? CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON : 175 CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF; 176 177 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), 178 target_state, CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK); 179 180 for (i = 0; i < 10; i++) { 181 u32 current_state; 182 183 current_state = cal_read_field(phy->cal, 184 CAL_CSI2_COMPLEXIO_CFG(phy->instance), 185 CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK); 186 187 if (current_state == target_state) 188 break; 189 190 usleep_range(1000, 1100); 191 } 192 193 if (i == 10) 194 phy_err(phy, "Failed to power %s complexio\n", 195 enable ? "up" : "down"); 196 } 197 198 static void cal_camerarx_wait_reset(struct cal_camerarx *phy) 199 { 200 unsigned long timeout; 201 202 timeout = jiffies + msecs_to_jiffies(750); 203 while (time_before(jiffies, timeout)) { 204 if (cal_read_field(phy->cal, 205 CAL_CSI2_COMPLEXIO_CFG(phy->instance), 206 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == 207 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) 208 break; 209 usleep_range(500, 5000); 210 } 211 212 if (cal_read_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), 213 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) != 214 CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) 215 phy_err(phy, "Timeout waiting for Complex IO reset done\n"); 216 } 217 218 static void cal_camerarx_wait_stop_state(struct cal_camerarx *phy) 219 { 220 unsigned long timeout; 221 222 timeout = jiffies + msecs_to_jiffies(750); 223 while (time_before(jiffies, timeout)) { 224 if (cal_read_field(phy->cal, 225 CAL_CSI2_TIMING(phy->instance), 226 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0) 227 break; 228 usleep_range(500, 5000); 229 } 230 231 if (cal_read_field(phy->cal, CAL_CSI2_TIMING(phy->instance), 232 CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) != 0) 233 phy_err(phy, "Timeout waiting for stop state\n"); 234 } 235 236 static void cal_camerarx_enable_irqs(struct cal_camerarx *phy) 237 { 238 const u32 cio_err_mask = 239 CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK | 240 CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK | 241 CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK | 242 CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK; 243 const u32 vc_err_mask = 244 CAL_CSI2_VC_IRQ_CS_IRQ_MASK(0) | 245 CAL_CSI2_VC_IRQ_CS_IRQ_MASK(1) | 246 CAL_CSI2_VC_IRQ_CS_IRQ_MASK(2) | 247 CAL_CSI2_VC_IRQ_CS_IRQ_MASK(3) | 248 CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(0) | 249 CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(1) | 250 CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(2) | 251 CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(3); 252 253 /* Enable CIO & VC error IRQs. */ 254 cal_write(phy->cal, CAL_HL_IRQENABLE_SET(0), 255 CAL_HL_IRQ_CIO_MASK(phy->instance) | 256 CAL_HL_IRQ_VC_MASK(phy->instance)); 257 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 258 cio_err_mask); 259 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(phy->instance), 260 vc_err_mask); 261 } 262 263 static void cal_camerarx_disable_irqs(struct cal_camerarx *phy) 264 { 265 /* Disable CIO error irqs */ 266 cal_write(phy->cal, CAL_HL_IRQENABLE_CLR(0), 267 CAL_HL_IRQ_CIO_MASK(phy->instance) | 268 CAL_HL_IRQ_VC_MASK(phy->instance)); 269 cal_write(phy->cal, CAL_CSI2_COMPLEXIO_IRQENABLE(phy->instance), 0); 270 cal_write(phy->cal, CAL_CSI2_VC_IRQENABLE(phy->instance), 0); 271 } 272 273 static void cal_camerarx_ppi_enable(struct cal_camerarx *phy) 274 { 275 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), 276 1, CAL_CSI2_PPI_CTRL_ECC_EN_MASK); 277 278 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), 279 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK); 280 } 281 282 static void cal_camerarx_ppi_disable(struct cal_camerarx *phy) 283 { 284 cal_write_field(phy->cal, CAL_CSI2_PPI_CTRL(phy->instance), 285 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK); 286 } 287 288 static int cal_camerarx_start(struct cal_camerarx *phy) 289 { 290 s64 link_freq; 291 u32 sscounter; 292 u32 val; 293 int ret; 294 295 if (phy->enable_count > 0) { 296 phy->enable_count++; 297 return 0; 298 } 299 300 link_freq = cal_camerarx_get_ext_link_freq(phy); 301 if (link_freq < 0) 302 return link_freq; 303 304 ret = v4l2_subdev_call(phy->source, core, s_power, 1); 305 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) { 306 phy_err(phy, "power on failed in subdev\n"); 307 return ret; 308 } 309 310 cal_camerarx_enable_irqs(phy); 311 312 /* 313 * CSI-2 PHY Link Initialization Sequence, according to the DRA74xP / 314 * DRA75xP / DRA76xP / DRA77xP TRM. The DRA71x / DRA72x and the AM65x / 315 * DRA80xM TRMs have a slightly simplified sequence. 316 */ 317 318 /* 319 * 1. Configure all CSI-2 low level protocol registers to be ready to 320 * receive signals/data from the CSI-2 PHY. 321 * 322 * i.-v. Configure the lanes position and polarity. 323 */ 324 cal_camerarx_lane_config(phy); 325 326 /* 327 * vi.-vii. Configure D-PHY mode, enable the required lanes and 328 * enable the CAMERARX clock. 329 */ 330 cal_camerarx_enable(phy); 331 332 /* 333 * 2. CSI PHY and link initialization sequence. 334 * 335 * a. Deassert the CSI-2 PHY reset. Do not wait for reset completion 336 * at this point, as it requires the external source to send the 337 * CSI-2 HS clock. 338 */ 339 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), 340 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL, 341 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); 342 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x De-assert Complex IO Reset\n", 343 phy->instance, 344 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance))); 345 346 /* Dummy read to allow SCP reset to complete. */ 347 camerarx_read(phy, CAL_CSI2_PHY_REG0); 348 349 /* Program the PHY timing parameters. */ 350 cal_camerarx_config(phy, link_freq); 351 352 /* 353 * b. Assert the FORCERXMODE signal. 354 * 355 * The stop-state-counter is based on fclk cycles, and we always use 356 * the x16 and x4 settings, so stop-state-timeout = 357 * fclk-cycle * 16 * 4 * counter. 358 * 359 * Stop-state-timeout must be more than 100us as per CSI-2 spec, so we 360 * calculate a timeout that's 100us (rounding up). 361 */ 362 sscounter = DIV_ROUND_UP(clk_get_rate(phy->cal->fclk), 10000 * 16 * 4); 363 364 val = cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance)); 365 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK); 366 cal_set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK); 367 cal_set_field(&val, sscounter, 368 CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK); 369 cal_write(phy->cal, CAL_CSI2_TIMING(phy->instance), val); 370 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n", 371 phy->instance, 372 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance))); 373 374 /* Assert the FORCERXMODE signal. */ 375 cal_write_field(phy->cal, CAL_CSI2_TIMING(phy->instance), 376 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK); 377 phy_dbg(3, phy, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n", 378 phy->instance, 379 cal_read(phy->cal, CAL_CSI2_TIMING(phy->instance))); 380 381 /* 382 * c. Connect pull-down on CSI-2 PHY link (using pad control). 383 * 384 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not 385 * implemented. 386 */ 387 388 /* 389 * d. Power up the CSI-2 PHY. 390 * e. Check whether the state status reaches the ON state. 391 */ 392 cal_camerarx_power(phy, true); 393 394 /* 395 * Start the source to enable the CSI-2 HS clock. We can now wait for 396 * CSI-2 PHY reset to complete. 397 */ 398 ret = v4l2_subdev_call(phy->source, video, s_stream, 1); 399 if (ret) { 400 v4l2_subdev_call(phy->source, core, s_power, 0); 401 cal_camerarx_disable_irqs(phy); 402 phy_err(phy, "stream on failed in subdev\n"); 403 return ret; 404 } 405 406 cal_camerarx_wait_reset(phy); 407 408 /* f. Wait for STOPSTATE=1 for all enabled lane modules. */ 409 cal_camerarx_wait_stop_state(phy); 410 411 phy_dbg(1, phy, "CSI2_%u_REG1 = 0x%08x (bits 31-28 should be set)\n", 412 phy->instance, camerarx_read(phy, CAL_CSI2_PHY_REG1)); 413 414 /* 415 * g. Disable pull-down on CSI-2 PHY link (using pad control). 416 * 417 * This is not required on DRA71x, DRA72x, AM65x and DRA80xM. Not 418 * implemented. 419 */ 420 421 /* Finally, enable the PHY Protocol Interface (PPI). */ 422 cal_camerarx_ppi_enable(phy); 423 424 phy->enable_count++; 425 426 return 0; 427 } 428 429 static void cal_camerarx_stop(struct cal_camerarx *phy) 430 { 431 int ret; 432 433 if (--phy->enable_count > 0) 434 return; 435 436 cal_camerarx_ppi_disable(phy); 437 438 cal_camerarx_disable_irqs(phy); 439 440 cal_camerarx_power(phy, false); 441 442 /* Assert Complex IO Reset */ 443 cal_write_field(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance), 444 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL, 445 CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK); 446 447 phy_dbg(3, phy, "CAL_CSI2_COMPLEXIO_CFG(%d) = 0x%08x Complex IO in Reset\n", 448 phy->instance, 449 cal_read(phy->cal, CAL_CSI2_COMPLEXIO_CFG(phy->instance))); 450 451 /* Disable the phy */ 452 cal_camerarx_disable(phy); 453 454 if (v4l2_subdev_call(phy->source, video, s_stream, 0)) 455 phy_err(phy, "stream off failed in subdev\n"); 456 457 ret = v4l2_subdev_call(phy->source, core, s_power, 0); 458 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV) 459 phy_err(phy, "power off failed in subdev\n"); 460 } 461 462 /* 463 * Errata i913: CSI2 LDO Needs to be disabled when module is powered on 464 * 465 * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2 466 * LDOs on the device are disabled if CSI-2 module is powered on 467 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304 468 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high 469 * current draw on the module supply in active mode. 470 * 471 * Errata does not apply when CSI-2 module is powered off 472 * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0). 473 * 474 * SW Workaround: 475 * Set the following register bits to disable the LDO, 476 * which is essentially CSI2 REG10 bit 6: 477 * 478 * Core 0: 0x4845 B828 = 0x0000 0040 479 * Core 1: 0x4845 B928 = 0x0000 0040 480 */ 481 void cal_camerarx_i913_errata(struct cal_camerarx *phy) 482 { 483 u32 reg10 = camerarx_read(phy, CAL_CSI2_PHY_REG10); 484 485 cal_set_field(®10, 1, CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK); 486 487 phy_dbg(1, phy, "CSI2_%d_REG10 = 0x%08x\n", phy->instance, reg10); 488 camerarx_write(phy, CAL_CSI2_PHY_REG10, reg10); 489 } 490 491 static int cal_camerarx_regmap_init(struct cal_dev *cal, 492 struct cal_camerarx *phy) 493 { 494 const struct cal_camerarx_data *phy_data; 495 unsigned int i; 496 497 if (!cal->data) 498 return -EINVAL; 499 500 phy_data = &cal->data->camerarx[phy->instance]; 501 502 for (i = 0; i < F_MAX_FIELDS; i++) { 503 struct reg_field field = { 504 .reg = cal->syscon_camerrx_offset, 505 .lsb = phy_data->fields[i].lsb, 506 .msb = phy_data->fields[i].msb, 507 }; 508 509 /* 510 * Here we update the reg offset with the 511 * value found in DT 512 */ 513 phy->fields[i] = devm_regmap_field_alloc(cal->dev, 514 cal->syscon_camerrx, 515 field); 516 if (IS_ERR(phy->fields[i])) { 517 cal_err(cal, "Unable to allocate regmap fields\n"); 518 return PTR_ERR(phy->fields[i]); 519 } 520 } 521 522 return 0; 523 } 524 525 static int cal_camerarx_parse_dt(struct cal_camerarx *phy) 526 { 527 struct v4l2_fwnode_endpoint *endpoint = &phy->endpoint; 528 char data_lanes[V4L2_MBUS_CSI2_MAX_DATA_LANES * 2]; 529 struct device_node *ep_node; 530 unsigned int i; 531 int ret; 532 533 /* 534 * Find the endpoint node for the port corresponding to the PHY 535 * instance, and parse its CSI-2-related properties. 536 */ 537 ep_node = of_graph_get_endpoint_by_regs(phy->cal->dev->of_node, 538 phy->instance, 0); 539 if (!ep_node) { 540 /* 541 * The endpoint is not mandatory, not all PHY instances need to 542 * be connected in DT. 543 */ 544 phy_dbg(3, phy, "Port has no endpoint\n"); 545 return 0; 546 } 547 548 endpoint->bus_type = V4L2_MBUS_CSI2_DPHY; 549 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(ep_node), endpoint); 550 if (ret < 0) { 551 phy_err(phy, "Failed to parse endpoint\n"); 552 goto done; 553 } 554 555 for (i = 0; i < endpoint->bus.mipi_csi2.num_data_lanes; i++) { 556 unsigned int lane = endpoint->bus.mipi_csi2.data_lanes[i]; 557 558 if (lane > 4) { 559 phy_err(phy, "Invalid position %u for data lane %u\n", 560 lane, i); 561 ret = -EINVAL; 562 goto done; 563 } 564 565 data_lanes[i*2] = '0' + lane; 566 data_lanes[i*2+1] = ' '; 567 } 568 569 data_lanes[i*2-1] = '\0'; 570 571 phy_dbg(3, phy, 572 "CSI-2 bus: clock lane <%u>, data lanes <%s>, flags 0x%08x\n", 573 endpoint->bus.mipi_csi2.clock_lane, data_lanes, 574 endpoint->bus.mipi_csi2.flags); 575 576 /* Retrieve the connected device and store it for later use. */ 577 phy->source_ep_node = of_graph_get_remote_endpoint(ep_node); 578 phy->source_node = of_graph_get_port_parent(phy->source_ep_node); 579 if (!phy->source_node) { 580 phy_dbg(3, phy, "Can't get remote parent\n"); 581 of_node_put(phy->source_ep_node); 582 ret = -EINVAL; 583 goto done; 584 } 585 586 phy_dbg(1, phy, "Found connected device %pOFn\n", phy->source_node); 587 588 done: 589 of_node_put(ep_node); 590 return ret; 591 } 592 593 /* ------------------------------------------------------------------ 594 * V4L2 Subdev Operations 595 * ------------------------------------------------------------------ 596 */ 597 598 static inline struct cal_camerarx *to_cal_camerarx(struct v4l2_subdev *sd) 599 { 600 return container_of(sd, struct cal_camerarx, subdev); 601 } 602 603 static int cal_camerarx_sd_s_stream(struct v4l2_subdev *sd, int enable) 604 { 605 struct cal_camerarx *phy = to_cal_camerarx(sd); 606 struct v4l2_subdev_state *state; 607 int ret = 0; 608 609 state = v4l2_subdev_lock_and_get_active_state(sd); 610 611 if (enable) 612 ret = cal_camerarx_start(phy); 613 else 614 cal_camerarx_stop(phy); 615 616 v4l2_subdev_unlock_state(state); 617 618 return ret; 619 } 620 621 static int cal_camerarx_sd_enum_mbus_code(struct v4l2_subdev *sd, 622 struct v4l2_subdev_state *state, 623 struct v4l2_subdev_mbus_code_enum *code) 624 { 625 /* No transcoding, source and sink codes must match. */ 626 if (cal_rx_pad_is_source(code->pad)) { 627 struct v4l2_mbus_framefmt *fmt; 628 629 if (code->index > 0) 630 return -EINVAL; 631 632 fmt = v4l2_subdev_state_get_format(state, 633 CAL_CAMERARX_PAD_SINK); 634 code->code = fmt->code; 635 } else { 636 if (code->index >= cal_num_formats) 637 return -EINVAL; 638 639 code->code = cal_formats[code->index].code; 640 } 641 642 return 0; 643 } 644 645 static int cal_camerarx_sd_enum_frame_size(struct v4l2_subdev *sd, 646 struct v4l2_subdev_state *state, 647 struct v4l2_subdev_frame_size_enum *fse) 648 { 649 const struct cal_format_info *fmtinfo; 650 651 if (fse->index > 0) 652 return -EINVAL; 653 654 /* No transcoding, source and sink formats must match. */ 655 if (cal_rx_pad_is_source(fse->pad)) { 656 struct v4l2_mbus_framefmt *fmt; 657 658 fmt = v4l2_subdev_state_get_format(state, 659 CAL_CAMERARX_PAD_SINK); 660 if (fse->code != fmt->code) 661 return -EINVAL; 662 663 fse->min_width = fmt->width; 664 fse->max_width = fmt->width; 665 fse->min_height = fmt->height; 666 fse->max_height = fmt->height; 667 } else { 668 fmtinfo = cal_format_by_code(fse->code); 669 if (!fmtinfo) 670 return -EINVAL; 671 672 fse->min_width = CAL_MIN_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); 673 fse->max_width = CAL_MAX_WIDTH_BYTES * 8 / ALIGN(fmtinfo->bpp, 8); 674 fse->min_height = CAL_MIN_HEIGHT_LINES; 675 fse->max_height = CAL_MAX_HEIGHT_LINES; 676 } 677 678 return 0; 679 } 680 681 static int cal_camerarx_sd_set_fmt(struct v4l2_subdev *sd, 682 struct v4l2_subdev_state *state, 683 struct v4l2_subdev_format *format) 684 { 685 const struct cal_format_info *fmtinfo; 686 struct v4l2_mbus_framefmt *fmt; 687 unsigned int bpp; 688 689 /* No transcoding, source and sink formats must match. */ 690 if (cal_rx_pad_is_source(format->pad)) 691 return v4l2_subdev_get_fmt(sd, state, format); 692 693 /* 694 * Default to the first format if the requested media bus code isn't 695 * supported. 696 */ 697 fmtinfo = cal_format_by_code(format->format.code); 698 if (!fmtinfo) 699 fmtinfo = &cal_formats[0]; 700 701 /* Clamp the size, update the code. The colorspace is accepted as-is. */ 702 bpp = ALIGN(fmtinfo->bpp, 8); 703 704 format->format.width = clamp_t(unsigned int, format->format.width, 705 CAL_MIN_WIDTH_BYTES * 8 / bpp, 706 CAL_MAX_WIDTH_BYTES * 8 / bpp); 707 format->format.height = clamp_t(unsigned int, format->format.height, 708 CAL_MIN_HEIGHT_LINES, 709 CAL_MAX_HEIGHT_LINES); 710 format->format.code = fmtinfo->code; 711 format->format.field = V4L2_FIELD_NONE; 712 713 /* Store the format and propagate it to the source pad. */ 714 715 fmt = v4l2_subdev_state_get_format(state, CAL_CAMERARX_PAD_SINK); 716 *fmt = format->format; 717 718 fmt = v4l2_subdev_state_get_format(state, 719 CAL_CAMERARX_PAD_FIRST_SOURCE); 720 *fmt = format->format; 721 722 return 0; 723 } 724 725 static int cal_camerarx_sd_init_state(struct v4l2_subdev *sd, 726 struct v4l2_subdev_state *state) 727 { 728 struct v4l2_subdev_format format = { 729 .which = state ? V4L2_SUBDEV_FORMAT_TRY 730 : V4L2_SUBDEV_FORMAT_ACTIVE, 731 .pad = CAL_CAMERARX_PAD_SINK, 732 .format = { 733 .width = 640, 734 .height = 480, 735 .code = MEDIA_BUS_FMT_UYVY8_1X16, 736 .field = V4L2_FIELD_NONE, 737 .colorspace = V4L2_COLORSPACE_SRGB, 738 .ycbcr_enc = V4L2_YCBCR_ENC_601, 739 .quantization = V4L2_QUANTIZATION_LIM_RANGE, 740 .xfer_func = V4L2_XFER_FUNC_SRGB, 741 }, 742 }; 743 744 return cal_camerarx_sd_set_fmt(sd, state, &format); 745 } 746 747 static int cal_camerarx_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 748 struct v4l2_mbus_frame_desc *fd) 749 { 750 struct cal_camerarx *phy = to_cal_camerarx(sd); 751 struct v4l2_mbus_frame_desc remote_desc; 752 const struct media_pad *remote_pad; 753 int ret; 754 755 remote_pad = media_pad_remote_pad_first(&phy->pads[CAL_CAMERARX_PAD_SINK]); 756 if (!remote_pad) 757 return -EPIPE; 758 759 ret = v4l2_subdev_call(phy->source, pad, get_frame_desc, 760 remote_pad->index, &remote_desc); 761 if (ret) 762 return ret; 763 764 if (remote_desc.type != V4L2_MBUS_FRAME_DESC_TYPE_CSI2) { 765 cal_err(phy->cal, 766 "Frame descriptor does not describe CSI-2 link"); 767 return -EINVAL; 768 } 769 770 if (remote_desc.num_entries > 1) 771 cal_err(phy->cal, 772 "Multiple streams not supported in remote frame descriptor, using the first one\n"); 773 774 fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2; 775 fd->num_entries = 1; 776 fd->entry[0] = remote_desc.entry[0]; 777 778 return 0; 779 } 780 781 static const struct v4l2_subdev_video_ops cal_camerarx_video_ops = { 782 .s_stream = cal_camerarx_sd_s_stream, 783 }; 784 785 static const struct v4l2_subdev_pad_ops cal_camerarx_pad_ops = { 786 .enum_mbus_code = cal_camerarx_sd_enum_mbus_code, 787 .enum_frame_size = cal_camerarx_sd_enum_frame_size, 788 .get_fmt = v4l2_subdev_get_fmt, 789 .set_fmt = cal_camerarx_sd_set_fmt, 790 .get_frame_desc = cal_camerarx_get_frame_desc, 791 }; 792 793 static const struct v4l2_subdev_ops cal_camerarx_subdev_ops = { 794 .video = &cal_camerarx_video_ops, 795 .pad = &cal_camerarx_pad_ops, 796 }; 797 798 static const struct v4l2_subdev_internal_ops cal_camerarx_internal_ops = { 799 .init_state = cal_camerarx_sd_init_state, 800 }; 801 802 static const struct media_entity_operations cal_camerarx_media_ops = { 803 .link_validate = v4l2_subdev_link_validate, 804 }; 805 806 /* ------------------------------------------------------------------ 807 * Create and Destroy 808 * ------------------------------------------------------------------ 809 */ 810 811 struct cal_camerarx *cal_camerarx_create(struct cal_dev *cal, 812 unsigned int instance) 813 { 814 struct platform_device *pdev = to_platform_device(cal->dev); 815 struct cal_camerarx *phy; 816 struct v4l2_subdev *sd; 817 unsigned int i; 818 int ret; 819 820 phy = devm_kzalloc(cal->dev, sizeof(*phy), GFP_KERNEL); 821 if (!phy) 822 return ERR_PTR(-ENOMEM); 823 824 phy->cal = cal; 825 phy->instance = instance; 826 827 spin_lock_init(&phy->vc_lock); 828 829 phy->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 830 (instance == 0) ? 831 "cal_rx_core0" : 832 "cal_rx_core1"); 833 phy->base = devm_ioremap_resource(cal->dev, phy->res); 834 if (IS_ERR(phy->base)) { 835 cal_err(cal, "failed to ioremap\n"); 836 return ERR_CAST(phy->base); 837 } 838 839 cal_dbg(1, cal, "ioresource %s at %pa - %pa\n", 840 phy->res->name, &phy->res->start, &phy->res->end); 841 842 ret = cal_camerarx_regmap_init(cal, phy); 843 if (ret) 844 return ERR_PTR(ret); 845 846 ret = cal_camerarx_parse_dt(phy); 847 if (ret) 848 return ERR_PTR(ret); 849 850 /* Initialize the V4L2 subdev and media entity. */ 851 sd = &phy->subdev; 852 v4l2_subdev_init(sd, &cal_camerarx_subdev_ops); 853 sd->internal_ops = &cal_camerarx_internal_ops; 854 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 855 sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 856 snprintf(sd->name, sizeof(sd->name), "CAMERARX%u", instance); 857 sd->dev = cal->dev; 858 859 phy->pads[CAL_CAMERARX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 860 for (i = CAL_CAMERARX_PAD_FIRST_SOURCE; i < CAL_CAMERARX_NUM_PADS; ++i) 861 phy->pads[i].flags = MEDIA_PAD_FL_SOURCE; 862 sd->entity.ops = &cal_camerarx_media_ops; 863 ret = media_entity_pads_init(&sd->entity, ARRAY_SIZE(phy->pads), 864 phy->pads); 865 if (ret) 866 goto err_node_put; 867 868 ret = v4l2_subdev_init_finalize(sd); 869 if (ret) 870 goto err_entity_cleanup; 871 872 ret = v4l2_device_register_subdev(&cal->v4l2_dev, sd); 873 if (ret) 874 goto err_free_state; 875 876 return phy; 877 878 err_free_state: 879 v4l2_subdev_cleanup(sd); 880 err_entity_cleanup: 881 media_entity_cleanup(&phy->subdev.entity); 882 err_node_put: 883 of_node_put(phy->source_ep_node); 884 of_node_put(phy->source_node); 885 return ERR_PTR(ret); 886 } 887 888 void cal_camerarx_destroy(struct cal_camerarx *phy) 889 { 890 if (!phy) 891 return; 892 893 v4l2_device_unregister_subdev(&phy->subdev); 894 v4l2_subdev_cleanup(&phy->subdev); 895 media_entity_cleanup(&phy->subdev.entity); 896 of_node_put(phy->source_ep_node); 897 of_node_put(phy->source_node); 898 } 899