1*7b59b132SShreeya Patel /* SPDX-License-Identifier: GPL-2.0 */ 2*7b59b132SShreeya Patel /* 3*7b59b132SShreeya Patel * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4*7b59b132SShreeya Patel * 5*7b59b132SShreeya Patel * Author: Shunqing Chen <csq@rock-chips.com> 6*7b59b132SShreeya Patel */ 7*7b59b132SShreeya Patel 8*7b59b132SShreeya Patel #ifndef DW_HDMI_RX_CEC_H 9*7b59b132SShreeya Patel #define DW_HDMI_RX_CEC_H 10*7b59b132SShreeya Patel 11*7b59b132SShreeya Patel struct snps_hdmirx_dev; 12*7b59b132SShreeya Patel 13*7b59b132SShreeya Patel struct hdmirx_cec_ops { 14*7b59b132SShreeya Patel void (*write)(struct snps_hdmirx_dev *hdmirx_dev, int reg, u32 val); 15*7b59b132SShreeya Patel u32 (*read)(struct snps_hdmirx_dev *hdmirx_dev, int reg); 16*7b59b132SShreeya Patel void (*enable)(struct snps_hdmirx_dev *hdmirx); 17*7b59b132SShreeya Patel void (*disable)(struct snps_hdmirx_dev *hdmirx); 18*7b59b132SShreeya Patel }; 19*7b59b132SShreeya Patel 20*7b59b132SShreeya Patel struct hdmirx_cec_data { 21*7b59b132SShreeya Patel struct snps_hdmirx_dev *hdmirx; 22*7b59b132SShreeya Patel const struct hdmirx_cec_ops *ops; 23*7b59b132SShreeya Patel struct device *dev; 24*7b59b132SShreeya Patel int irq; 25*7b59b132SShreeya Patel }; 26*7b59b132SShreeya Patel 27*7b59b132SShreeya Patel struct hdmirx_cec { 28*7b59b132SShreeya Patel struct snps_hdmirx_dev *hdmirx; 29*7b59b132SShreeya Patel struct device *dev; 30*7b59b132SShreeya Patel const struct hdmirx_cec_ops *ops; 31*7b59b132SShreeya Patel u32 addresses; 32*7b59b132SShreeya Patel struct cec_adapter *adap; 33*7b59b132SShreeya Patel struct cec_msg rx_msg; 34*7b59b132SShreeya Patel unsigned int tx_status; 35*7b59b132SShreeya Patel bool tx_done; 36*7b59b132SShreeya Patel bool rx_done; 37*7b59b132SShreeya Patel int irq; 38*7b59b132SShreeya Patel }; 39*7b59b132SShreeya Patel 40*7b59b132SShreeya Patel struct hdmirx_cec *snps_hdmirx_cec_register(struct hdmirx_cec_data *data); 41*7b59b132SShreeya Patel void snps_hdmirx_cec_unregister(struct hdmirx_cec *cec); 42*7b59b132SShreeya Patel 43*7b59b132SShreeya Patel #endif /* DW_HDMI_RX_CEC_H */ 44