1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Synopsys DesignWare MIPI CSI-2 Receiver Driver 4 * 5 * Copyright (C) 2019 Rockchip Electronics Co., Ltd. 6 * Copyright (C) 2025 Michael Riesch <michael.riesch@wolfvision.net> 7 * Copyright (C) 2026 Collabora, Ltd. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 22 #include <media/mipi-csi2.h> 23 #include <media/v4l2-ctrls.h> 24 #include <media/v4l2-fwnode.h> 25 #include <media/v4l2-mc.h> 26 #include <media/v4l2-subdev.h> 27 28 #define SW_CPHY_EN(x) ((x) << 0) 29 #define SW_DSI_EN(x) ((x) << 4) 30 #define SW_DATATYPE_FS(x) ((x) << 8) 31 #define SW_DATATYPE_FE(x) ((x) << 14) 32 #define SW_DATATYPE_LS(x) ((x) << 20) 33 #define SW_DATATYPE_LE(x) ((x) << 26) 34 35 #define DW_REG_EXIST BIT(31) 36 #define DW_REG(x) (DW_REG_EXIST | (x)) 37 38 #define DPHY_TEST_CTRL0_TEST_CLR BIT(0) 39 40 #define IPI_VCID_VC(x) FIELD_PREP(GENMASK(1, 0), (x)) 41 #define IPI_VCID_VC_0_1(x) FIELD_PREP(GENMASK(3, 2), (x)) 42 #define IPI_VCID_VC_2 BIT(4) 43 44 #define IPI_DATA_TYPE_DT(x) FIELD_PREP(GENMASK(5, 0), (x)) 45 #define IPI_DATA_TYPE_EMB_DATA_EN BIT(8) 46 47 #define IPI_MODE_CONTROLLER BIT(1) 48 #define IPI_MODE_COLOR_MODE16 BIT(8) 49 #define IPI_MODE_CUT_THROUGH BIT(16) 50 #define IPI_MODE_ENABLE BIT(24) 51 52 #define IPI_MEM_FLUSH_AUTO BIT(8) 53 54 enum dw_mipi_csi2rx_regs_index { 55 DW_MIPI_CSI2RX_N_LANES, 56 DW_MIPI_CSI2RX_RESETN, 57 DW_MIPI_CSI2RX_PHY_STATE, 58 DW_MIPI_CSI2RX_ERR1, 59 DW_MIPI_CSI2RX_ERR2, 60 DW_MIPI_CSI2RX_MSK1, 61 DW_MIPI_CSI2RX_MSK2, 62 DW_MIPI_CSI2RX_CONTROL, 63 /* imx93 (v150) new register */ 64 DW_MIPI_CSI2RX_DPHY_RSTZ, 65 DW_MIPI_CSI2RX_PHY_TST_CTRL0, 66 DW_MIPI_CSI2RX_PHY_TST_CTRL1, 67 DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 68 DW_MIPI_CSI2RX_IPI_DATATYPE, 69 DW_MIPI_CSI2RX_IPI_MEM_FLUSH, 70 DW_MIPI_CSI2RX_IPI_MODE, 71 DW_MIPI_CSI2RX_IPI_SOFTRSTN, 72 DW_MIPI_CSI2RX_IPI_VCID, 73 74 DW_MIPI_CSI2RX_MAX, 75 }; 76 77 enum { 78 DW_MIPI_CSI2RX_PAD_SINK, 79 DW_MIPI_CSI2RX_PAD_SRC, 80 DW_MIPI_CSI2RX_PAD_MAX, 81 }; 82 83 struct dw_mipi_csi2rx_device; 84 85 struct dw_mipi_csi2rx_drvdata { 86 const u32 *regs; 87 void (*dphy_assert_reset)(struct dw_mipi_csi2rx_device *csi2); 88 void (*dphy_deassert_reset)(struct dw_mipi_csi2rx_device *csi2); 89 void (*ipi_enable)(struct dw_mipi_csi2rx_device *csi2); 90 }; 91 92 struct dw_mipi_csi2rx_format { 93 u32 code; 94 u8 depth; 95 u8 csi_dt; 96 }; 97 98 struct dw_mipi_csi2rx_device { 99 struct device *dev; 100 101 void __iomem *base_addr; 102 struct clk_bulk_data *clks; 103 unsigned int clks_num; 104 struct phy *phy; 105 struct reset_control *reset; 106 107 const struct dw_mipi_csi2rx_format *formats; 108 unsigned int formats_num; 109 110 struct media_pad pads[DW_MIPI_CSI2RX_PAD_MAX]; 111 struct v4l2_async_notifier notifier; 112 struct v4l2_subdev sd; 113 114 enum v4l2_mbus_type bus_type; 115 u32 lanes_num; 116 117 const struct dw_mipi_csi2rx_drvdata *drvdata; 118 }; 119 120 static const u32 rk3568_regs[DW_MIPI_CSI2RX_MAX] = { 121 [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4), 122 [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x10), 123 [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x14), 124 [DW_MIPI_CSI2RX_ERR1] = DW_REG(0x20), 125 [DW_MIPI_CSI2RX_ERR2] = DW_REG(0x24), 126 [DW_MIPI_CSI2RX_MSK1] = DW_REG(0x28), 127 [DW_MIPI_CSI2RX_MSK2] = DW_REG(0x2c), 128 [DW_MIPI_CSI2RX_CONTROL] = DW_REG(0x40), 129 }; 130 131 static const struct dw_mipi_csi2rx_drvdata rk3568_drvdata = { 132 .regs = rk3568_regs, 133 }; 134 135 static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = { 136 [DW_MIPI_CSI2RX_N_LANES] = DW_REG(0x4), 137 [DW_MIPI_CSI2RX_RESETN] = DW_REG(0x8), 138 [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40), 139 [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44), 140 [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48), 141 [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50), 142 [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54), 143 [DW_MIPI_CSI2RX_IPI_MODE] = DW_REG(0x80), 144 [DW_MIPI_CSI2RX_IPI_VCID] = DW_REG(0x84), 145 [DW_MIPI_CSI2RX_IPI_DATATYPE] = DW_REG(0x88), 146 [DW_MIPI_CSI2RX_IPI_MEM_FLUSH] = DW_REG(0x8c), 147 [DW_MIPI_CSI2RX_IPI_SOFTRSTN] = DW_REG(0xa0), 148 }; 149 150 static const struct v4l2_mbus_framefmt default_format = { 151 .width = 3840, 152 .height = 2160, 153 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 154 .field = V4L2_FIELD_NONE, 155 .colorspace = V4L2_COLORSPACE_RAW, 156 .ycbcr_enc = V4L2_YCBCR_ENC_601, 157 .quantization = V4L2_QUANTIZATION_FULL_RANGE, 158 .xfer_func = V4L2_XFER_FUNC_NONE, 159 }; 160 161 static const struct dw_mipi_csi2rx_format formats[] = { 162 /* YUV formats */ 163 { 164 .code = MEDIA_BUS_FMT_YUYV8_1X16, 165 .depth = 16, 166 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 167 }, 168 { 169 .code = MEDIA_BUS_FMT_UYVY8_1X16, 170 .depth = 16, 171 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 172 }, 173 { 174 .code = MEDIA_BUS_FMT_YVYU8_1X16, 175 .depth = 16, 176 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 177 }, 178 { 179 .code = MEDIA_BUS_FMT_VYUY8_1X16, 180 .depth = 16, 181 .csi_dt = MIPI_CSI2_DT_YUV422_8B, 182 }, 183 /* RGB formats */ 184 { 185 .code = MEDIA_BUS_FMT_RGB888_1X24, 186 .depth = 24, 187 .csi_dt = MIPI_CSI2_DT_RGB888, 188 }, 189 { 190 .code = MEDIA_BUS_FMT_BGR888_1X24, 191 .depth = 24, 192 .csi_dt = MIPI_CSI2_DT_RGB888, 193 }, 194 /* Bayer formats */ 195 { 196 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 197 .depth = 8, 198 .csi_dt = MIPI_CSI2_DT_RAW8, 199 }, 200 { 201 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 202 .depth = 8, 203 .csi_dt = MIPI_CSI2_DT_RAW8, 204 }, 205 { 206 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 207 .depth = 8, 208 .csi_dt = MIPI_CSI2_DT_RAW8, 209 }, 210 { 211 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 212 .depth = 8, 213 .csi_dt = MIPI_CSI2_DT_RAW8, 214 }, 215 { 216 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 217 .depth = 10, 218 .csi_dt = MIPI_CSI2_DT_RAW10, 219 }, 220 { 221 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 222 .depth = 10, 223 .csi_dt = MIPI_CSI2_DT_RAW10, 224 }, 225 { 226 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 227 .depth = 10, 228 .csi_dt = MIPI_CSI2_DT_RAW10, 229 }, 230 { 231 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 232 .depth = 10, 233 .csi_dt = MIPI_CSI2_DT_RAW10, 234 }, 235 { 236 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 237 .depth = 12, 238 .csi_dt = MIPI_CSI2_DT_RAW12, 239 }, 240 { 241 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 242 .depth = 12, 243 .csi_dt = MIPI_CSI2_DT_RAW12, 244 }, 245 { 246 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 247 .depth = 12, 248 .csi_dt = MIPI_CSI2_DT_RAW12, 249 }, 250 { 251 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 252 .depth = 12, 253 .csi_dt = MIPI_CSI2_DT_RAW12, 254 }, 255 }; 256 257 static inline struct dw_mipi_csi2rx_device *to_csi2(struct v4l2_subdev *sd) 258 { 259 return container_of(sd, struct dw_mipi_csi2rx_device, sd); 260 } 261 262 static bool dw_mipi_csi2rx_has_reg(struct dw_mipi_csi2rx_device *csi2, 263 enum dw_mipi_csi2rx_regs_index index) 264 { 265 if (index < DW_MIPI_CSI2RX_MAX && 266 (csi2->drvdata->regs[index] & DW_REG_EXIST)) 267 return true; 268 269 return false; 270 } 271 272 static void __iomem * 273 dw_mipi_csi2rx_get_regaddr(struct dw_mipi_csi2rx_device *csi2, 274 enum dw_mipi_csi2rx_regs_index index) 275 { 276 u32 off = (~DW_REG_EXIST) & csi2->drvdata->regs[index]; 277 278 return csi2->base_addr + off; 279 } 280 281 static inline void dw_mipi_csi2rx_write(struct dw_mipi_csi2rx_device *csi2, 282 enum dw_mipi_csi2rx_regs_index index, 283 u32 val) 284 { 285 if (!dw_mipi_csi2rx_has_reg(csi2, index)) { 286 dev_err_once(csi2->dev, 287 "write to non-existent register index: %d\n", 288 index); 289 return; 290 } 291 292 writel(val, dw_mipi_csi2rx_get_regaddr(csi2, index)); 293 } 294 295 static inline u32 dw_mipi_csi2rx_read(struct dw_mipi_csi2rx_device *csi2, 296 enum dw_mipi_csi2rx_regs_index index) 297 { 298 if (!dw_mipi_csi2rx_has_reg(csi2, index)) { 299 dev_err_once(csi2->dev, 300 "read non-existent register index: %d\n", index); 301 /* return 0 for non-existent registers */ 302 return 0; 303 } 304 305 return readl(dw_mipi_csi2rx_get_regaddr(csi2, index)); 306 } 307 308 static const struct dw_mipi_csi2rx_format * 309 dw_mipi_csi2rx_find_format(struct dw_mipi_csi2rx_device *csi2, u32 mbus_code) 310 { 311 WARN_ON(csi2->formats_num == 0); 312 313 for (unsigned int i = 0; i < csi2->formats_num; i++) { 314 const struct dw_mipi_csi2rx_format *format = &csi2->formats[i]; 315 316 if (format->code == mbus_code) 317 return format; 318 } 319 320 return NULL; 321 } 322 323 static int dw_mipi_csi2rx_start(struct dw_mipi_csi2rx_device *csi2) 324 { 325 struct media_pad *source_pad; 326 union phy_configure_opts opts; 327 u32 lanes = csi2->lanes_num; 328 u32 control = 0; 329 s64 link_freq; 330 int ret; 331 332 if (lanes < 1 || lanes > 4) 333 return -EINVAL; 334 335 source_pad = media_pad_remote_pad_unique( 336 &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]); 337 if (IS_ERR(source_pad)) 338 return PTR_ERR(source_pad); 339 340 /* set mult and div to 0, thus completely rely on V4L2_CID_LINK_FREQ */ 341 link_freq = v4l2_get_link_freq(source_pad, 0, 0); 342 if (link_freq < 0) 343 return link_freq; 344 345 switch (csi2->bus_type) { 346 case V4L2_MBUS_CSI2_DPHY: 347 ret = phy_mipi_dphy_get_default_config_for_hsclk(link_freq * 2, 348 lanes, &opts.mipi_dphy); 349 if (ret) 350 return ret; 351 352 ret = phy_set_mode(csi2->phy, PHY_MODE_MIPI_DPHY); 353 if (ret) 354 return ret; 355 356 ret = phy_configure(csi2->phy, &opts); 357 if (ret) 358 return ret; 359 360 control |= SW_CPHY_EN(0); 361 break; 362 363 case V4L2_MBUS_CSI2_CPHY: 364 /* TODO: implement CPHY configuration */ 365 return -EOPNOTSUPP; 366 default: 367 return -EINVAL; 368 } 369 370 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); 371 372 if (csi2->drvdata->dphy_assert_reset) 373 csi2->drvdata->dphy_assert_reset(csi2); 374 375 control |= SW_DATATYPE_FS(0x00) | SW_DATATYPE_FE(0x01) | 376 SW_DATATYPE_LS(0x02) | SW_DATATYPE_LE(0x03); 377 378 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_N_LANES, lanes - 1); 379 380 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_CONTROL)) 381 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_CONTROL, control); 382 383 ret = phy_power_on(csi2->phy); 384 if (ret) 385 return ret; 386 387 if (csi2->drvdata->dphy_deassert_reset) 388 csi2->drvdata->dphy_deassert_reset(csi2); 389 390 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 1); 391 392 if (csi2->drvdata->ipi_enable) 393 csi2->drvdata->ipi_enable(csi2); 394 395 return 0; 396 } 397 398 static void dw_mipi_csi2rx_stop(struct dw_mipi_csi2rx_device *csi2) 399 { 400 phy_power_off(csi2->phy); 401 402 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 0); 403 404 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK1)) 405 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK1, ~0); 406 407 if (dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_MSK2)) 408 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_MSK2, ~0); 409 } 410 411 static const struct media_entity_operations dw_mipi_csi2rx_media_ops = { 412 .link_validate = v4l2_subdev_link_validate, 413 }; 414 415 static int 416 dw_mipi_csi2rx_enum_mbus_code(struct v4l2_subdev *sd, 417 struct v4l2_subdev_state *sd_state, 418 struct v4l2_subdev_mbus_code_enum *code) 419 { 420 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 421 422 switch (code->pad) { 423 case DW_MIPI_CSI2RX_PAD_SRC: 424 if (code->index) 425 return -EINVAL; 426 427 code->code = 428 v4l2_subdev_state_get_format(sd_state, 429 DW_MIPI_CSI2RX_PAD_SINK)->code; 430 431 return 0; 432 case DW_MIPI_CSI2RX_PAD_SINK: 433 if (code->index >= csi2->formats_num) 434 return -EINVAL; 435 436 code->code = csi2->formats[code->index].code; 437 return 0; 438 default: 439 return -EINVAL; 440 } 441 } 442 443 static int dw_mipi_csi2rx_set_fmt(struct v4l2_subdev *sd, 444 struct v4l2_subdev_state *state, 445 struct v4l2_subdev_format *format) 446 { 447 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 448 const struct dw_mipi_csi2rx_format *fmt; 449 struct v4l2_mbus_framefmt *sink, *src; 450 451 /* the format on the source pad always matches the sink pad */ 452 if (format->pad == DW_MIPI_CSI2RX_PAD_SRC) 453 return v4l2_subdev_get_fmt(sd, state, format); 454 455 sink = v4l2_subdev_state_get_format(state, format->pad, format->stream); 456 if (!sink) 457 return -EINVAL; 458 459 fmt = dw_mipi_csi2rx_find_format(csi2, format->format.code); 460 if (!fmt) 461 format->format = default_format; 462 463 *sink = format->format; 464 465 /* propagate the format to the source pad */ 466 src = v4l2_subdev_state_get_opposite_stream_format(state, format->pad, 467 format->stream); 468 if (!src) 469 return -EINVAL; 470 471 *src = *sink; 472 473 return 0; 474 } 475 476 static int dw_mipi_csi2rx_set_routing(struct v4l2_subdev *sd, 477 struct v4l2_subdev_state *state, 478 enum v4l2_subdev_format_whence which, 479 struct v4l2_subdev_krouting *routing) 480 { 481 int ret; 482 483 ret = v4l2_subdev_routing_validate(sd, routing, 484 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1); 485 if (ret) 486 return ret; 487 488 return v4l2_subdev_set_routing_with_fmt(sd, state, routing, 489 &default_format); 490 } 491 492 static int dw_mipi_csi2rx_enable_streams(struct v4l2_subdev *sd, 493 struct v4l2_subdev_state *state, 494 u32 pad, u64 streams_mask) 495 { 496 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 497 struct v4l2_subdev *remote_sd; 498 struct media_pad *sink_pad, *remote_pad; 499 struct device *dev = csi2->dev; 500 u64 mask; 501 int ret; 502 503 sink_pad = &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; 504 remote_pad = media_pad_remote_pad_first(sink_pad); 505 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 506 507 mask = v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, 508 DW_MIPI_CSI2RX_PAD_SRC, 509 &streams_mask); 510 511 ret = pm_runtime_resume_and_get(dev); 512 if (ret) 513 goto err; 514 515 ret = dw_mipi_csi2rx_start(csi2); 516 if (ret) { 517 dev_err(dev, "failed to enable CSI hardware\n"); 518 goto err_pm_runtime_put; 519 } 520 521 ret = v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask); 522 if (ret) 523 goto err_csi_stop; 524 525 return 0; 526 527 err_csi_stop: 528 dw_mipi_csi2rx_stop(csi2); 529 err_pm_runtime_put: 530 pm_runtime_put(dev); 531 err: 532 return ret; 533 } 534 535 static int dw_mipi_csi2rx_disable_streams(struct v4l2_subdev *sd, 536 struct v4l2_subdev_state *state, 537 u32 pad, u64 streams_mask) 538 { 539 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 540 struct v4l2_subdev *remote_sd; 541 struct media_pad *sink_pad, *remote_pad; 542 struct device *dev = csi2->dev; 543 u64 mask; 544 int ret; 545 546 sink_pad = &sd->entity.pads[DW_MIPI_CSI2RX_PAD_SINK]; 547 remote_pad = media_pad_remote_pad_first(sink_pad); 548 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 549 550 mask = v4l2_subdev_state_xlate_streams(state, DW_MIPI_CSI2RX_PAD_SINK, 551 DW_MIPI_CSI2RX_PAD_SRC, 552 &streams_mask); 553 554 ret = v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask); 555 556 dw_mipi_csi2rx_stop(csi2); 557 558 pm_runtime_put(dev); 559 560 return ret; 561 } 562 563 static int 564 dw_mipi_csi2rx_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, 565 struct v4l2_mbus_frame_desc *fd) 566 { 567 struct dw_mipi_csi2rx_device *csi2 = to_csi2(sd); 568 struct v4l2_subdev *remote_sd; 569 struct media_pad *remote_pad; 570 571 remote_pad = media_pad_remote_pad_unique(&csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]); 572 if (IS_ERR(remote_pad)) { 573 dev_err(csi2->dev, "can't get remote source pad\n"); 574 return PTR_ERR(remote_pad); 575 } 576 577 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 578 579 return v4l2_subdev_call(remote_sd, pad, get_frame_desc, 580 remote_pad->index, fd); 581 } 582 583 static const struct v4l2_subdev_pad_ops dw_mipi_csi2rx_pad_ops = { 584 .enum_mbus_code = dw_mipi_csi2rx_enum_mbus_code, 585 .get_fmt = v4l2_subdev_get_fmt, 586 .set_fmt = dw_mipi_csi2rx_set_fmt, 587 .get_frame_desc = dw_mipi_csi2rx_get_frame_desc, 588 .set_routing = dw_mipi_csi2rx_set_routing, 589 .enable_streams = dw_mipi_csi2rx_enable_streams, 590 .disable_streams = dw_mipi_csi2rx_disable_streams, 591 }; 592 593 static const struct v4l2_subdev_ops dw_mipi_csi2rx_ops = { 594 .pad = &dw_mipi_csi2rx_pad_ops, 595 }; 596 597 static int dw_mipi_csi2rx_init_state(struct v4l2_subdev *sd, 598 struct v4l2_subdev_state *state) 599 { 600 struct v4l2_subdev_route routes[] = { 601 { 602 .sink_pad = DW_MIPI_CSI2RX_PAD_SINK, 603 .sink_stream = 0, 604 .source_pad = DW_MIPI_CSI2RX_PAD_SRC, 605 .source_stream = 0, 606 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE, 607 }, 608 }; 609 struct v4l2_subdev_krouting routing = { 610 .len_routes = ARRAY_SIZE(routes), 611 .num_routes = ARRAY_SIZE(routes), 612 .routes = routes, 613 }; 614 615 return v4l2_subdev_set_routing_with_fmt(sd, state, &routing, 616 &default_format); 617 } 618 619 static const struct v4l2_subdev_internal_ops dw_mipi_csi2rx_internal_ops = { 620 .init_state = dw_mipi_csi2rx_init_state, 621 }; 622 623 static int dw_mipi_csi2rx_notifier_bound(struct v4l2_async_notifier *notifier, 624 struct v4l2_subdev *sd, 625 struct v4l2_async_connection *asd) 626 { 627 struct dw_mipi_csi2rx_device *csi2 = 628 container_of(notifier, struct dw_mipi_csi2rx_device, notifier); 629 struct media_pad *sink_pad = &csi2->pads[DW_MIPI_CSI2RX_PAD_SINK]; 630 int ret; 631 632 ret = v4l2_create_fwnode_links_to_pad(sd, sink_pad, 633 MEDIA_LNK_FL_ENABLED); 634 if (ret) { 635 dev_err(csi2->dev, "failed to link source pad of %s\n", 636 sd->name); 637 return ret; 638 } 639 640 return 0; 641 } 642 643 static const struct v4l2_async_notifier_operations dw_mipi_csi2rx_notifier_ops = { 644 .bound = dw_mipi_csi2rx_notifier_bound, 645 }; 646 647 static int dw_mipi_csi2rx_register_notifier(struct dw_mipi_csi2rx_device *csi2) 648 { 649 struct v4l2_async_connection *asd; 650 struct v4l2_async_notifier *ntf = &csi2->notifier; 651 struct v4l2_fwnode_endpoint vep; 652 struct v4l2_subdev *sd = &csi2->sd; 653 struct device *dev = csi2->dev; 654 int ret; 655 656 struct fwnode_handle *ep __free(fwnode_handle) = 657 fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); 658 if (!ep) 659 return dev_err_probe(dev, -ENODEV, "failed to get endpoint\n"); 660 661 vep.bus_type = V4L2_MBUS_UNKNOWN; 662 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 663 if (ret) 664 return dev_err_probe(dev, ret, "failed to parse endpoint\n"); 665 666 if (vep.bus_type != V4L2_MBUS_CSI2_DPHY && 667 vep.bus_type != V4L2_MBUS_CSI2_CPHY) 668 return dev_err_probe(dev, -EINVAL, 669 "invalid bus type of endpoint\n"); 670 671 csi2->bus_type = vep.bus_type; 672 csi2->lanes_num = vep.bus.mipi_csi2.num_data_lanes; 673 674 v4l2_async_subdev_nf_init(ntf, sd); 675 ntf->ops = &dw_mipi_csi2rx_notifier_ops; 676 677 asd = v4l2_async_nf_add_fwnode_remote(ntf, ep, 678 struct v4l2_async_connection); 679 if (IS_ERR(asd)) { 680 ret = PTR_ERR(asd); 681 goto err_nf_cleanup; 682 } 683 684 ret = v4l2_async_nf_register(ntf); 685 if (ret) { 686 ret = dev_err_probe(dev, ret, "failed to register notifier\n"); 687 goto err_nf_cleanup; 688 } 689 690 return 0; 691 692 err_nf_cleanup: 693 v4l2_async_nf_cleanup(ntf); 694 695 return ret; 696 } 697 698 static int dw_mipi_csi2rx_register(struct dw_mipi_csi2rx_device *csi2) 699 { 700 struct media_pad *pads = csi2->pads; 701 struct v4l2_subdev *sd = &csi2->sd; 702 int ret; 703 704 ret = dw_mipi_csi2rx_register_notifier(csi2); 705 if (ret) 706 goto err; 707 708 v4l2_subdev_init(sd, &dw_mipi_csi2rx_ops); 709 sd->dev = csi2->dev; 710 sd->entity.ops = &dw_mipi_csi2rx_media_ops; 711 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 712 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS; 713 sd->internal_ops = &dw_mipi_csi2rx_internal_ops; 714 snprintf(sd->name, sizeof(sd->name), "dw-mipi-csi2rx %s", 715 dev_name(csi2->dev)); 716 717 pads[DW_MIPI_CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK | 718 MEDIA_PAD_FL_MUST_CONNECT; 719 pads[DW_MIPI_CSI2RX_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 720 ret = media_entity_pads_init(&sd->entity, DW_MIPI_CSI2RX_PAD_MAX, pads); 721 if (ret) 722 goto err_notifier_unregister; 723 724 ret = v4l2_subdev_init_finalize(sd); 725 if (ret) 726 goto err_entity_cleanup; 727 728 ret = v4l2_async_register_subdev(sd); 729 if (ret) { 730 dev_err(sd->dev, "failed to register CSI-2 subdev\n"); 731 goto err_subdev_cleanup; 732 } 733 734 return 0; 735 736 err_subdev_cleanup: 737 v4l2_subdev_cleanup(sd); 738 err_entity_cleanup: 739 media_entity_cleanup(&sd->entity); 740 err_notifier_unregister: 741 v4l2_async_nf_unregister(&csi2->notifier); 742 v4l2_async_nf_cleanup(&csi2->notifier); 743 err: 744 return ret; 745 } 746 747 static void dw_mipi_csi2rx_unregister(struct dw_mipi_csi2rx_device *csi2) 748 { 749 struct v4l2_subdev *sd = &csi2->sd; 750 751 v4l2_async_unregister_subdev(sd); 752 v4l2_subdev_cleanup(sd); 753 media_entity_cleanup(&sd->entity); 754 v4l2_async_nf_unregister(&csi2->notifier); 755 v4l2_async_nf_cleanup(&csi2->notifier); 756 } 757 758 static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *csi2) 759 { 760 u32 val; 761 762 /* Release Synopsys DPHY test codes from reset */ 763 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0); 764 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0); 765 766 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); 767 val &= ~DPHY_TEST_CTRL0_TEST_CLR; 768 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); 769 770 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0); 771 /* Wait for at least 15ns */ 772 ndelay(15); 773 val |= DPHY_TEST_CTRL0_TEST_CLR; 774 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val); 775 } 776 777 static void imx93_csi2rx_dphy_deassert_reset(struct dw_mipi_csi2rx_device *csi2) 778 { 779 /* Release PHY from reset */ 780 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0x1); 781 /* 782 * ndelay() is not necessary have MMIO operation, need dummy read to 783 * ensure that the write operation above reaches its target. 784 */ 785 dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ); 786 ndelay(5); 787 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0x1); 788 789 dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ); 790 ndelay(5); 791 } 792 793 static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi2) 794 { 795 int dt = csi2->formats->csi_dt; 796 u32 val; 797 798 /* Do IPI soft reset */ 799 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x0); 800 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_SOFTRSTN, 0x1); 801 802 /* Select virtual channel and data type to be processed by IPI */ 803 val = IPI_DATA_TYPE_DT(dt); 804 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_DATATYPE, val); 805 806 /* Set virtual channel 0 as default */ 807 val = IPI_VCID_VC(0); 808 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_VCID, val); 809 810 /* 811 * Select IPI camera timing mode and allow the pixel stream 812 * to be non-continuous when pixel interface FIFO is empty 813 */ 814 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); 815 val &= ~IPI_MODE_CONTROLLER; 816 val &= ~IPI_MODE_COLOR_MODE16; 817 val |= IPI_MODE_CUT_THROUGH; 818 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); 819 820 /* Memory is automatically flushed at each Frame Start */ 821 val = IPI_MEM_FLUSH_AUTO; 822 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MEM_FLUSH, val); 823 824 /* Enable IPI */ 825 val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_IPI_MODE); 826 val |= IPI_MODE_ENABLE; 827 dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); 828 } 829 830 static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = { 831 .regs = imx93_regs, 832 .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset, 833 .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset, 834 .ipi_enable = imx93_csi2rx_dphy_ipi_enable, 835 }; 836 837 static const struct of_device_id dw_mipi_csi2rx_of_match[] = { 838 { 839 .compatible = "fsl,imx93-mipi-csi2", 840 .data = &imx93_drvdata, 841 }, 842 { 843 .compatible = "rockchip,rk3568-mipi-csi2", 844 .data = &rk3568_drvdata, 845 }, 846 {} 847 }; 848 MODULE_DEVICE_TABLE(of, dw_mipi_csi2rx_of_match); 849 850 static int dw_mipi_csi2rx_probe(struct platform_device *pdev) 851 { 852 struct device *dev = &pdev->dev; 853 struct dw_mipi_csi2rx_device *csi2; 854 int ret; 855 856 csi2 = devm_kzalloc(dev, sizeof(*csi2), GFP_KERNEL); 857 if (!csi2) 858 return -ENOMEM; 859 csi2->dev = dev; 860 dev_set_drvdata(dev, csi2); 861 862 csi2->base_addr = devm_platform_ioremap_resource(pdev, 0); 863 if (IS_ERR(csi2->base_addr)) 864 return PTR_ERR(csi2->base_addr); 865 866 csi2->drvdata = device_get_match_data(dev); 867 if (!csi2->drvdata) 868 return dev_err_probe(dev, -EINVAL, 869 "failed to get driver data\n"); 870 871 ret = devm_clk_bulk_get_all(dev, &csi2->clks); 872 if (ret < 0) 873 return dev_err_probe(dev, -ENODEV, "failed to get clocks\n"); 874 csi2->clks_num = ret; 875 876 csi2->phy = devm_phy_get(dev, NULL); 877 if (IS_ERR(csi2->phy)) 878 return dev_err_probe(dev, PTR_ERR(csi2->phy), 879 "failed to get MIPI CSI-2 PHY\n"); 880 881 csi2->reset = devm_reset_control_get_optional_exclusive(dev, NULL); 882 if (IS_ERR(csi2->reset)) 883 return dev_err_probe(dev, PTR_ERR(csi2->reset), 884 "failed to get reset\n"); 885 886 csi2->formats = formats; 887 csi2->formats_num = ARRAY_SIZE(formats); 888 889 ret = devm_pm_runtime_enable(dev); 890 if (ret) 891 return dev_err_probe(dev, ret, "failed to enable pm runtime\n"); 892 893 ret = phy_init(csi2->phy); 894 if (ret) 895 return dev_err_probe(dev, ret, 896 "failed to initialize MIPI CSI-2 PHY\n"); 897 898 ret = dw_mipi_csi2rx_register(csi2); 899 if (ret) 900 goto err_phy_exit; 901 902 return 0; 903 904 err_phy_exit: 905 phy_exit(csi2->phy); 906 907 return ret; 908 } 909 910 static void dw_mipi_csi2rx_remove(struct platform_device *pdev) 911 { 912 struct dw_mipi_csi2rx_device *csi2 = platform_get_drvdata(pdev); 913 914 dw_mipi_csi2rx_unregister(csi2); 915 phy_exit(csi2->phy); 916 } 917 918 static int dw_mipi_csi2rx_runtime_suspend(struct device *dev) 919 { 920 struct dw_mipi_csi2rx_device *csi2 = dev_get_drvdata(dev); 921 922 clk_bulk_disable_unprepare(csi2->clks_num, csi2->clks); 923 924 return 0; 925 } 926 927 static int dw_mipi_csi2rx_runtime_resume(struct device *dev) 928 { 929 struct dw_mipi_csi2rx_device *csi2 = dev_get_drvdata(dev); 930 int ret; 931 932 reset_control_assert(csi2->reset); 933 udelay(5); 934 reset_control_deassert(csi2->reset); 935 936 ret = clk_bulk_prepare_enable(csi2->clks_num, csi2->clks); 937 if (ret) { 938 dev_err(dev, "failed to enable clocks\n"); 939 return ret; 940 } 941 942 return 0; 943 } 944 945 static DEFINE_RUNTIME_DEV_PM_OPS(dw_mipi_csi2rx_pm_ops, 946 dw_mipi_csi2rx_runtime_suspend, 947 dw_mipi_csi2rx_runtime_resume, NULL); 948 949 static struct platform_driver dw_mipi_csi2rx_drv = { 950 .driver = { 951 .name = "dw-mipi-csi2rx", 952 .of_match_table = dw_mipi_csi2rx_of_match, 953 .pm = pm_ptr(&dw_mipi_csi2rx_pm_ops), 954 }, 955 .probe = dw_mipi_csi2rx_probe, 956 .remove = dw_mipi_csi2rx_remove, 957 }; 958 module_platform_driver(dw_mipi_csi2rx_drv); 959 960 MODULE_DESCRIPTION("Synopsys DesignWare MIPI CSI-2 Receiver platform driver"); 961 MODULE_LICENSE("GPL"); 962