1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STM32 Digital Camera Memory Interface 4 * 5 * Copyright (C) STMicroelectronics SA 2017 6 * Authors: Yannick Fertre <yannick.fertre@st.com> 7 * Hugues Fruchet <hugues.fruchet@st.com> 8 * for STMicroelectronics. 9 * 10 * This driver is based on atmel_isi.c 11 * 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_graph.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/reset.h> 28 #include <linux/videodev2.h> 29 30 #include <media/v4l2-ctrls.h> 31 #include <media/v4l2-dev.h> 32 #include <media/v4l2-device.h> 33 #include <media/v4l2-event.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-image-sizes.h> 36 #include <media/v4l2-ioctl.h> 37 #include <media/v4l2-rect.h> 38 #include <media/videobuf2-dma-contig.h> 39 40 #define DRV_NAME "stm32-dcmi" 41 42 /* Registers offset for DCMI */ 43 #define DCMI_CR 0x00 /* Control Register */ 44 #define DCMI_SR 0x04 /* Status Register */ 45 #define DCMI_RIS 0x08 /* Raw Interrupt Status register */ 46 #define DCMI_IER 0x0C /* Interrupt Enable Register */ 47 #define DCMI_MIS 0x10 /* Masked Interrupt Status register */ 48 #define DCMI_ICR 0x14 /* Interrupt Clear Register */ 49 #define DCMI_ESCR 0x18 /* Embedded Synchronization Code Register */ 50 #define DCMI_ESUR 0x1C /* Embedded Synchronization Unmask Register */ 51 #define DCMI_CWSTRT 0x20 /* Crop Window STaRT */ 52 #define DCMI_CWSIZE 0x24 /* Crop Window SIZE */ 53 #define DCMI_DR 0x28 /* Data Register */ 54 #define DCMI_IDR 0x2C /* IDentifier Register */ 55 56 /* Bits definition for control register (DCMI_CR) */ 57 #define CR_CAPTURE BIT(0) 58 #define CR_CM BIT(1) 59 #define CR_CROP BIT(2) 60 #define CR_JPEG BIT(3) 61 #define CR_ESS BIT(4) 62 #define CR_PCKPOL BIT(5) 63 #define CR_HSPOL BIT(6) 64 #define CR_VSPOL BIT(7) 65 #define CR_FCRC_0 BIT(8) 66 #define CR_FCRC_1 BIT(9) 67 #define CR_EDM_0 BIT(10) 68 #define CR_EDM_1 BIT(11) 69 #define CR_ENABLE BIT(14) 70 71 /* Bits definition for status register (DCMI_SR) */ 72 #define SR_HSYNC BIT(0) 73 #define SR_VSYNC BIT(1) 74 #define SR_FNE BIT(2) 75 76 /* 77 * Bits definition for interrupt registers 78 * (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR) 79 */ 80 #define IT_FRAME BIT(0) 81 #define IT_OVR BIT(1) 82 #define IT_ERR BIT(2) 83 #define IT_VSYNC BIT(3) 84 #define IT_LINE BIT(4) 85 86 enum state { 87 STOPPED = 0, 88 WAIT_FOR_BUFFER, 89 RUNNING, 90 }; 91 92 #define MIN_WIDTH 16U 93 #define MAX_WIDTH 2592U 94 #define MIN_HEIGHT 16U 95 #define MAX_HEIGHT 2592U 96 97 #define TIMEOUT_MS 1000 98 99 #define OVERRUN_ERROR_THRESHOLD 3 100 101 struct dcmi_format { 102 u32 fourcc; 103 u32 mbus_code; 104 u8 bpp; 105 }; 106 107 struct dcmi_framesize { 108 u32 width; 109 u32 height; 110 }; 111 112 struct dcmi_buf { 113 struct vb2_v4l2_buffer vb; 114 bool prepared; 115 struct sg_table sgt; 116 size_t size; 117 struct list_head list; 118 }; 119 120 struct stm32_dcmi { 121 /* Protects the access of variables shared within the interrupt */ 122 spinlock_t irqlock; 123 struct device *dev; 124 void __iomem *regs; 125 struct resource *res; 126 struct reset_control *rstc; 127 int sequence; 128 struct list_head buffers; 129 struct dcmi_buf *active; 130 int irq; 131 132 struct v4l2_device v4l2_dev; 133 struct video_device *vdev; 134 struct v4l2_async_notifier notifier; 135 struct v4l2_subdev *source; 136 struct v4l2_subdev *s_subdev; 137 struct v4l2_format fmt; 138 struct v4l2_rect crop; 139 bool do_crop; 140 141 const struct dcmi_format **sd_formats; 142 unsigned int num_of_sd_formats; 143 const struct dcmi_format *sd_format; 144 struct dcmi_framesize *sd_framesizes; 145 unsigned int num_of_sd_framesizes; 146 struct dcmi_framesize sd_framesize; 147 struct v4l2_rect sd_bounds; 148 149 /* Protect this data structure */ 150 struct mutex lock; 151 struct vb2_queue queue; 152 153 struct v4l2_mbus_config_parallel bus; 154 enum v4l2_mbus_type bus_type; 155 struct completion complete; 156 struct clk *mclk; 157 enum state state; 158 struct dma_chan *dma_chan; 159 dma_cookie_t dma_cookie; 160 u32 dma_max_burst; 161 u32 misr; 162 int errors_count; 163 int overrun_count; 164 int buffers_count; 165 166 /* Ensure DMA operations atomicity */ 167 struct mutex dma_lock; 168 169 struct media_device mdev; 170 struct media_pad vid_cap_pad; 171 struct media_pipeline pipeline; 172 }; 173 174 static inline struct stm32_dcmi *notifier_to_dcmi(struct v4l2_async_notifier *n) 175 { 176 return container_of(n, struct stm32_dcmi, notifier); 177 } 178 179 static inline u32 reg_read(void __iomem *base, u32 reg) 180 { 181 return readl_relaxed(base + reg); 182 } 183 184 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 185 { 186 writel_relaxed(val, base + reg); 187 } 188 189 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 190 { 191 reg_write(base, reg, reg_read(base, reg) | mask); 192 } 193 194 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 195 { 196 reg_write(base, reg, reg_read(base, reg) & ~mask); 197 } 198 199 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf); 200 201 static void dcmi_buffer_done(struct stm32_dcmi *dcmi, 202 struct dcmi_buf *buf, 203 size_t bytesused, 204 int err) 205 { 206 struct vb2_v4l2_buffer *vbuf; 207 208 if (!buf) 209 return; 210 211 list_del_init(&buf->list); 212 213 vbuf = &buf->vb; 214 215 vbuf->sequence = dcmi->sequence++; 216 vbuf->field = V4L2_FIELD_NONE; 217 vbuf->vb2_buf.timestamp = ktime_get_ns(); 218 vb2_set_plane_payload(&vbuf->vb2_buf, 0, bytesused); 219 vb2_buffer_done(&vbuf->vb2_buf, 220 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 221 dev_dbg(dcmi->dev, "buffer[%d] done seq=%d, bytesused=%zu\n", 222 vbuf->vb2_buf.index, vbuf->sequence, bytesused); 223 224 dcmi->buffers_count++; 225 dcmi->active = NULL; 226 } 227 228 static int dcmi_restart_capture(struct stm32_dcmi *dcmi) 229 { 230 struct dcmi_buf *buf; 231 232 spin_lock_irq(&dcmi->irqlock); 233 234 if (dcmi->state != RUNNING) { 235 spin_unlock_irq(&dcmi->irqlock); 236 return -EINVAL; 237 } 238 239 /* Restart a new DMA transfer with next buffer */ 240 if (list_empty(&dcmi->buffers)) { 241 dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n"); 242 dcmi->state = WAIT_FOR_BUFFER; 243 spin_unlock_irq(&dcmi->irqlock); 244 return 0; 245 } 246 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list); 247 dcmi->active = buf; 248 249 spin_unlock_irq(&dcmi->irqlock); 250 251 return dcmi_start_capture(dcmi, buf); 252 } 253 254 static void dcmi_dma_callback(void *param) 255 { 256 struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param; 257 struct dma_tx_state state; 258 enum dma_status status; 259 struct dcmi_buf *buf = dcmi->active; 260 261 spin_lock_irq(&dcmi->irqlock); 262 263 /* Check DMA status */ 264 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); 265 266 switch (status) { 267 case DMA_IN_PROGRESS: 268 dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__); 269 break; 270 case DMA_PAUSED: 271 dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__); 272 break; 273 case DMA_ERROR: 274 dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__); 275 276 /* Return buffer to V4L2 in error state */ 277 dcmi_buffer_done(dcmi, buf, 0, -EIO); 278 break; 279 case DMA_COMPLETE: 280 dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__); 281 282 /* Return buffer to V4L2 */ 283 dcmi_buffer_done(dcmi, buf, buf->size, 0); 284 285 spin_unlock_irq(&dcmi->irqlock); 286 287 /* Restart capture */ 288 if (dcmi_restart_capture(dcmi)) 289 dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n", 290 __func__); 291 return; 292 default: 293 dev_err(dcmi->dev, "%s: Received unknown status\n", __func__); 294 break; 295 } 296 297 spin_unlock_irq(&dcmi->irqlock); 298 } 299 300 static int dcmi_start_dma(struct stm32_dcmi *dcmi, 301 struct dcmi_buf *buf) 302 { 303 struct dma_async_tx_descriptor *desc = NULL; 304 struct dma_slave_config config; 305 int ret; 306 307 memset(&config, 0, sizeof(config)); 308 309 config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR; 310 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 311 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 312 config.dst_maxburst = 4; 313 314 /* Configure DMA channel */ 315 ret = dmaengine_slave_config(dcmi->dma_chan, &config); 316 if (ret < 0) { 317 dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n", 318 __func__, ret); 319 return ret; 320 } 321 322 /* 323 * Avoid call of dmaengine_terminate_sync() between 324 * dmaengine_prep_slave_single() and dmaengine_submit() 325 * by locking the whole DMA submission sequence 326 */ 327 mutex_lock(&dcmi->dma_lock); 328 329 /* Prepare a DMA transaction */ 330 desc = dmaengine_prep_slave_sg(dcmi->dma_chan, buf->sgt.sgl, buf->sgt.nents, 331 DMA_DEV_TO_MEM, 332 DMA_PREP_INTERRUPT); 333 if (!desc) { 334 dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_sg failed\n", __func__); 335 mutex_unlock(&dcmi->dma_lock); 336 return -EINVAL; 337 } 338 339 /* Set completion callback routine for notification */ 340 desc->callback = dcmi_dma_callback; 341 desc->callback_param = dcmi; 342 343 /* Push current DMA transaction in the pending queue */ 344 dcmi->dma_cookie = dmaengine_submit(desc); 345 if (dma_submit_error(dcmi->dma_cookie)) { 346 dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__); 347 mutex_unlock(&dcmi->dma_lock); 348 return -ENXIO; 349 } 350 351 mutex_unlock(&dcmi->dma_lock); 352 353 dma_async_issue_pending(dcmi->dma_chan); 354 355 return 0; 356 } 357 358 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf) 359 { 360 int ret; 361 362 if (!buf) 363 return -EINVAL; 364 365 ret = dcmi_start_dma(dcmi, buf); 366 if (ret) { 367 dcmi->errors_count++; 368 return ret; 369 } 370 371 /* Enable capture */ 372 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE); 373 374 return 0; 375 } 376 377 static void dcmi_set_crop(struct stm32_dcmi *dcmi) 378 { 379 u32 size, start; 380 381 /* Crop resolution */ 382 size = ((dcmi->crop.height - 1) << 16) | 383 ((dcmi->crop.width << 1) - 1); 384 reg_write(dcmi->regs, DCMI_CWSIZE, size); 385 386 /* Crop start point */ 387 start = ((dcmi->crop.top) << 16) | 388 ((dcmi->crop.left << 1)); 389 reg_write(dcmi->regs, DCMI_CWSTRT, start); 390 391 dev_dbg(dcmi->dev, "Cropping to %ux%u@%u:%u\n", 392 dcmi->crop.width, dcmi->crop.height, 393 dcmi->crop.left, dcmi->crop.top); 394 395 /* Enable crop */ 396 reg_set(dcmi->regs, DCMI_CR, CR_CROP); 397 } 398 399 static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) 400 { 401 struct dma_tx_state state; 402 enum dma_status status; 403 struct dcmi_buf *buf = dcmi->active; 404 405 if (!buf) 406 return; 407 408 /* 409 * Because of variable JPEG buffer size sent by sensor, 410 * DMA transfer never completes due to transfer size never reached. 411 * In order to ensure that all the JPEG data are transferred 412 * in active buffer memory, DMA is drained. 413 * Then DMA tx status gives the amount of data transferred 414 * to memory, which is then returned to V4L2 through the active 415 * buffer payload. 416 */ 417 418 /* Drain DMA */ 419 dmaengine_synchronize(dcmi->dma_chan); 420 421 /* Get DMA residue to get JPEG size */ 422 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); 423 if (status != DMA_ERROR && state.residue < buf->size) { 424 /* Return JPEG buffer to V4L2 with received JPEG buffer size */ 425 dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0); 426 } else { 427 dcmi->errors_count++; 428 dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n", 429 __func__); 430 /* Return JPEG buffer to V4L2 in ERROR state */ 431 dcmi_buffer_done(dcmi, buf, 0, -EIO); 432 } 433 434 /* Abort DMA operation */ 435 dmaengine_terminate_sync(dcmi->dma_chan); 436 437 /* Restart capture */ 438 if (dcmi_restart_capture(dcmi)) 439 dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n", 440 __func__); 441 } 442 443 static irqreturn_t dcmi_irq_thread(int irq, void *arg) 444 { 445 struct stm32_dcmi *dcmi = arg; 446 447 spin_lock_irq(&dcmi->irqlock); 448 449 if (dcmi->misr & IT_OVR) { 450 dcmi->overrun_count++; 451 if (dcmi->overrun_count > OVERRUN_ERROR_THRESHOLD) 452 dcmi->errors_count++; 453 } 454 if (dcmi->misr & IT_ERR) 455 dcmi->errors_count++; 456 457 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG && 458 dcmi->misr & IT_FRAME) { 459 /* JPEG received */ 460 spin_unlock_irq(&dcmi->irqlock); 461 dcmi_process_jpeg(dcmi); 462 return IRQ_HANDLED; 463 } 464 465 spin_unlock_irq(&dcmi->irqlock); 466 return IRQ_HANDLED; 467 } 468 469 static irqreturn_t dcmi_irq_callback(int irq, void *arg) 470 { 471 struct stm32_dcmi *dcmi = arg; 472 unsigned long flags; 473 474 spin_lock_irqsave(&dcmi->irqlock, flags); 475 476 dcmi->misr = reg_read(dcmi->regs, DCMI_MIS); 477 478 /* Clear interrupt */ 479 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR); 480 481 spin_unlock_irqrestore(&dcmi->irqlock, flags); 482 483 return IRQ_WAKE_THREAD; 484 } 485 486 static int dcmi_queue_setup(struct vb2_queue *vq, 487 unsigned int *nbuffers, 488 unsigned int *nplanes, 489 unsigned int sizes[], 490 struct device *alloc_devs[]) 491 { 492 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 493 unsigned int size; 494 495 size = dcmi->fmt.fmt.pix.sizeimage; 496 497 /* Make sure the image size is large enough */ 498 if (*nplanes) 499 return sizes[0] < size ? -EINVAL : 0; 500 501 *nplanes = 1; 502 sizes[0] = size; 503 504 dev_dbg(dcmi->dev, "Setup queue, count=%d, size=%d\n", 505 *nbuffers, size); 506 507 return 0; 508 } 509 510 static int dcmi_buf_init(struct vb2_buffer *vb) 511 { 512 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 513 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 514 515 INIT_LIST_HEAD(&buf->list); 516 517 return 0; 518 } 519 520 static int dcmi_buf_prepare(struct vb2_buffer *vb) 521 { 522 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue); 523 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 524 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 525 unsigned long size; 526 unsigned int num_sgs = 1; 527 dma_addr_t dma_buf; 528 struct scatterlist *sg; 529 int i, ret; 530 531 size = dcmi->fmt.fmt.pix.sizeimage; 532 533 if (vb2_plane_size(vb, 0) < size) { 534 dev_err(dcmi->dev, "%s data will not fit into plane (%lu < %lu)\n", 535 __func__, vb2_plane_size(vb, 0), size); 536 return -EINVAL; 537 } 538 539 vb2_set_plane_payload(vb, 0, size); 540 541 if (!buf->prepared) { 542 /* Get memory addresses */ 543 buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0); 544 if (buf->size > dcmi->dma_max_burst) 545 num_sgs = DIV_ROUND_UP(buf->size, dcmi->dma_max_burst); 546 547 ret = sg_alloc_table(&buf->sgt, num_sgs, GFP_ATOMIC); 548 if (ret) { 549 dev_err(dcmi->dev, "sg table alloc failed\n"); 550 return ret; 551 } 552 553 dma_buf = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 554 555 dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n", 556 vb->index, &dma_buf, buf->size); 557 558 for_each_sg(buf->sgt.sgl, sg, num_sgs, i) { 559 size_t bytes = min_t(size_t, size, dcmi->dma_max_burst); 560 561 sg_dma_address(sg) = dma_buf; 562 sg_dma_len(sg) = bytes; 563 dma_buf += bytes; 564 size -= bytes; 565 } 566 567 buf->prepared = true; 568 569 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size); 570 } 571 572 return 0; 573 } 574 575 static void dcmi_buf_queue(struct vb2_buffer *vb) 576 { 577 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue); 578 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 579 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 580 581 spin_lock_irq(&dcmi->irqlock); 582 583 /* Enqueue to video buffers list */ 584 list_add_tail(&buf->list, &dcmi->buffers); 585 586 if (dcmi->state == WAIT_FOR_BUFFER) { 587 dcmi->state = RUNNING; 588 dcmi->active = buf; 589 590 dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n", 591 buf->vb.vb2_buf.index); 592 593 spin_unlock_irq(&dcmi->irqlock); 594 if (dcmi_start_capture(dcmi, buf)) 595 dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n", 596 __func__); 597 return; 598 } 599 600 spin_unlock_irq(&dcmi->irqlock); 601 } 602 603 static struct media_entity *dcmi_find_source(struct stm32_dcmi *dcmi) 604 { 605 struct media_entity *entity = &dcmi->vdev->entity; 606 struct media_pad *pad; 607 608 /* Walk searching for entity having no sink */ 609 while (1) { 610 pad = &entity->pads[0]; 611 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 612 break; 613 614 pad = media_pad_remote_pad_first(pad); 615 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 616 break; 617 618 entity = pad->entity; 619 } 620 621 return entity; 622 } 623 624 static int dcmi_pipeline_s_fmt(struct stm32_dcmi *dcmi, 625 struct v4l2_subdev_format *format) 626 { 627 struct media_entity *entity = &dcmi->source->entity; 628 struct v4l2_subdev *subdev; 629 struct media_pad *sink_pad = NULL; 630 struct media_pad *src_pad = NULL; 631 struct media_pad *pad = NULL; 632 struct v4l2_subdev_format fmt = *format; 633 bool found = false; 634 int ret; 635 636 /* 637 * Starting from sensor subdevice, walk within 638 * pipeline and set format on each subdevice 639 */ 640 while (1) { 641 unsigned int i; 642 643 /* Search if current entity has a source pad */ 644 for (i = 0; i < entity->num_pads; i++) { 645 pad = &entity->pads[i]; 646 if (pad->flags & MEDIA_PAD_FL_SOURCE) { 647 src_pad = pad; 648 found = true; 649 break; 650 } 651 } 652 if (!found) 653 break; 654 655 subdev = media_entity_to_v4l2_subdev(entity); 656 657 /* Propagate format on sink pad if any, otherwise source pad */ 658 if (sink_pad) 659 pad = sink_pad; 660 661 dev_dbg(dcmi->dev, "\"%s\":%d pad format set to 0x%x %ux%u\n", 662 subdev->name, pad->index, format->format.code, 663 format->format.width, format->format.height); 664 665 fmt.pad = pad->index; 666 ret = v4l2_subdev_call(subdev, pad, set_fmt, NULL, &fmt); 667 if (ret < 0) { 668 dev_err(dcmi->dev, "%s: Failed to set format 0x%x %ux%u on \"%s\":%d pad (%d)\n", 669 __func__, format->format.code, 670 format->format.width, format->format.height, 671 subdev->name, pad->index, ret); 672 return ret; 673 } 674 675 if (fmt.format.code != format->format.code || 676 fmt.format.width != format->format.width || 677 fmt.format.height != format->format.height) { 678 dev_dbg(dcmi->dev, "\"%s\":%d pad format has been changed to 0x%x %ux%u\n", 679 subdev->name, pad->index, fmt.format.code, 680 fmt.format.width, fmt.format.height); 681 } 682 683 /* Walk to next entity */ 684 sink_pad = media_pad_remote_pad_first(src_pad); 685 if (!sink_pad || !is_media_entity_v4l2_subdev(sink_pad->entity)) 686 break; 687 688 entity = sink_pad->entity; 689 } 690 *format = fmt; 691 692 return 0; 693 } 694 695 static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) 696 { 697 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 698 struct dcmi_buf *buf, *node; 699 u32 val = 0; 700 int ret; 701 702 ret = pm_runtime_resume_and_get(dcmi->dev); 703 if (ret < 0) { 704 dev_err(dcmi->dev, "%s: Failed to start streaming, cannot get sync (%d)\n", 705 __func__, ret); 706 goto err_unlocked; 707 } 708 709 ret = video_device_pipeline_start(dcmi->vdev, &dcmi->pipeline); 710 if (ret < 0) { 711 dev_err(dcmi->dev, "%s: Failed to start streaming, media pipeline start error (%d)\n", 712 __func__, ret); 713 goto err_pm_put; 714 } 715 716 ret = v4l2_subdev_call(dcmi->s_subdev, video, s_stream, 1); 717 if (ret < 0) { 718 dev_err(dcmi->dev, "%s: Failed to start source subdev, error (%d)\n", 719 __func__, ret); 720 goto err_media_pipeline_stop; 721 } 722 723 spin_lock_irq(&dcmi->irqlock); 724 725 /* Set bus width */ 726 switch (dcmi->bus.bus_width) { 727 case 14: 728 val |= CR_EDM_0 | CR_EDM_1; 729 break; 730 case 12: 731 val |= CR_EDM_1; 732 break; 733 case 10: 734 val |= CR_EDM_0; 735 break; 736 default: 737 /* Set bus width to 8 bits by default */ 738 break; 739 } 740 741 /* Set vertical synchronization polarity */ 742 if (dcmi->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 743 val |= CR_VSPOL; 744 745 /* Set horizontal synchronization polarity */ 746 if (dcmi->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 747 val |= CR_HSPOL; 748 749 /* Set pixel clock polarity */ 750 if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 751 val |= CR_PCKPOL; 752 753 /* 754 * BT656 embedded synchronisation bus mode. 755 * 756 * Default SAV/EAV mode is supported here with default codes 757 * SAV=0xff000080 & EAV=0xff00009d. 758 * With DCMI this means LSC=SAV=0x80 & LEC=EAV=0x9d. 759 */ 760 if (dcmi->bus_type == V4L2_MBUS_BT656) { 761 val |= CR_ESS; 762 763 /* Unmask all codes */ 764 reg_write(dcmi->regs, DCMI_ESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */ 765 766 /* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */ 767 reg_write(dcmi->regs, DCMI_ESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */ 768 } 769 770 reg_write(dcmi->regs, DCMI_CR, val); 771 772 /* Set crop */ 773 if (dcmi->do_crop) 774 dcmi_set_crop(dcmi); 775 776 /* Enable jpeg capture */ 777 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) 778 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */ 779 780 /* Enable dcmi */ 781 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE); 782 783 dcmi->sequence = 0; 784 dcmi->errors_count = 0; 785 dcmi->overrun_count = 0; 786 dcmi->buffers_count = 0; 787 788 /* 789 * Start transfer if at least one buffer has been queued, 790 * otherwise transfer is deferred at buffer queueing 791 */ 792 if (list_empty(&dcmi->buffers)) { 793 dev_dbg(dcmi->dev, "Start streaming is deferred to next buffer queueing\n"); 794 dcmi->state = WAIT_FOR_BUFFER; 795 spin_unlock_irq(&dcmi->irqlock); 796 return 0; 797 } 798 799 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list); 800 dcmi->active = buf; 801 802 dcmi->state = RUNNING; 803 804 dev_dbg(dcmi->dev, "Start streaming, starting capture\n"); 805 806 spin_unlock_irq(&dcmi->irqlock); 807 ret = dcmi_start_capture(dcmi, buf); 808 if (ret) { 809 dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n", 810 __func__); 811 goto err_pipeline_stop; 812 } 813 814 /* Enable interruptions */ 815 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) 816 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); 817 else 818 reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR); 819 820 return 0; 821 822 err_pipeline_stop: 823 v4l2_subdev_call(dcmi->s_subdev, video, s_stream, 0); 824 825 err_media_pipeline_stop: 826 video_device_pipeline_stop(dcmi->vdev); 827 828 err_pm_put: 829 pm_runtime_put(dcmi->dev); 830 err_unlocked: 831 spin_lock_irq(&dcmi->irqlock); 832 /* 833 * Return all buffers to vb2 in QUEUED state. 834 * This will give ownership back to userspace 835 */ 836 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) { 837 list_del_init(&buf->list); 838 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); 839 } 840 dcmi->active = NULL; 841 spin_unlock_irq(&dcmi->irqlock); 842 843 return ret; 844 } 845 846 static void dcmi_stop_streaming(struct vb2_queue *vq) 847 { 848 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 849 struct dcmi_buf *buf, *node; 850 int ret; 851 852 ret = v4l2_subdev_call(dcmi->s_subdev, video, s_stream, 0); 853 if (ret < 0) 854 dev_err(dcmi->dev, "%s: Failed to stop source subdev, error (%d)\n", 855 __func__, ret); 856 857 video_device_pipeline_stop(dcmi->vdev); 858 859 spin_lock_irq(&dcmi->irqlock); 860 861 /* Disable interruptions */ 862 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); 863 864 /* Disable DCMI */ 865 reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE); 866 867 /* Return all queued buffers to vb2 in ERROR state */ 868 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) { 869 list_del_init(&buf->list); 870 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 871 } 872 873 dcmi->active = NULL; 874 dcmi->state = STOPPED; 875 876 spin_unlock_irq(&dcmi->irqlock); 877 878 /* Stop all pending DMA operations */ 879 mutex_lock(&dcmi->dma_lock); 880 dmaengine_terminate_sync(dcmi->dma_chan); 881 mutex_unlock(&dcmi->dma_lock); 882 883 pm_runtime_put(dcmi->dev); 884 885 if (dcmi->errors_count) 886 dev_warn(dcmi->dev, "Some errors found while streaming: errors=%d (overrun=%d), buffers=%d\n", 887 dcmi->errors_count, dcmi->overrun_count, 888 dcmi->buffers_count); 889 dev_dbg(dcmi->dev, "Stop streaming, errors=%d (overrun=%d), buffers=%d\n", 890 dcmi->errors_count, dcmi->overrun_count, 891 dcmi->buffers_count); 892 } 893 894 static const struct vb2_ops dcmi_video_qops = { 895 .queue_setup = dcmi_queue_setup, 896 .buf_init = dcmi_buf_init, 897 .buf_prepare = dcmi_buf_prepare, 898 .buf_queue = dcmi_buf_queue, 899 .start_streaming = dcmi_start_streaming, 900 .stop_streaming = dcmi_stop_streaming, 901 .wait_prepare = vb2_ops_wait_prepare, 902 .wait_finish = vb2_ops_wait_finish, 903 }; 904 905 static int dcmi_g_fmt_vid_cap(struct file *file, void *priv, 906 struct v4l2_format *fmt) 907 { 908 struct stm32_dcmi *dcmi = video_drvdata(file); 909 910 *fmt = dcmi->fmt; 911 912 return 0; 913 } 914 915 static const struct dcmi_format *find_format_by_fourcc(struct stm32_dcmi *dcmi, 916 unsigned int fourcc) 917 { 918 unsigned int num_formats = dcmi->num_of_sd_formats; 919 const struct dcmi_format *fmt; 920 unsigned int i; 921 922 for (i = 0; i < num_formats; i++) { 923 fmt = dcmi->sd_formats[i]; 924 if (fmt->fourcc == fourcc) 925 return fmt; 926 } 927 928 return NULL; 929 } 930 931 static void __find_outer_frame_size(struct stm32_dcmi *dcmi, 932 struct v4l2_pix_format *pix, 933 struct dcmi_framesize *framesize) 934 { 935 struct dcmi_framesize *match = NULL; 936 unsigned int i; 937 unsigned int min_err = UINT_MAX; 938 939 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 940 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i]; 941 int w_err = (fsize->width - pix->width); 942 int h_err = (fsize->height - pix->height); 943 int err = w_err + h_err; 944 945 if (w_err >= 0 && h_err >= 0 && err < min_err) { 946 min_err = err; 947 match = fsize; 948 } 949 } 950 if (!match) 951 match = &dcmi->sd_framesizes[0]; 952 953 *framesize = *match; 954 } 955 956 static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f, 957 const struct dcmi_format **sd_format, 958 struct dcmi_framesize *sd_framesize) 959 { 960 const struct dcmi_format *sd_fmt; 961 struct dcmi_framesize sd_fsize; 962 struct v4l2_pix_format *pix = &f->fmt.pix; 963 struct v4l2_subdev_format format = { 964 .which = V4L2_SUBDEV_FORMAT_TRY, 965 }; 966 bool do_crop; 967 int ret; 968 969 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat); 970 if (!sd_fmt) { 971 if (!dcmi->num_of_sd_formats) 972 return -ENODATA; 973 974 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1]; 975 pix->pixelformat = sd_fmt->fourcc; 976 } 977 978 /* Limit to hardware capabilities */ 979 pix->width = clamp(pix->width, MIN_WIDTH, MAX_WIDTH); 980 pix->height = clamp(pix->height, MIN_HEIGHT, MAX_HEIGHT); 981 982 /* No crop if JPEG is requested */ 983 do_crop = dcmi->do_crop && (pix->pixelformat != V4L2_PIX_FMT_JPEG); 984 985 if (do_crop && dcmi->num_of_sd_framesizes) { 986 struct dcmi_framesize outer_sd_fsize; 987 /* 988 * If crop is requested and sensor have discrete frame sizes, 989 * select the frame size that is just larger than request 990 */ 991 __find_outer_frame_size(dcmi, pix, &outer_sd_fsize); 992 pix->width = outer_sd_fsize.width; 993 pix->height = outer_sd_fsize.height; 994 } 995 996 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); 997 ret = v4l2_subdev_call_state_try(dcmi->source, pad, set_fmt, &format); 998 if (ret < 0) 999 return ret; 1000 1001 /* Update pix regarding to what sensor can do */ 1002 v4l2_fill_pix_format(pix, &format.format); 1003 1004 /* Save resolution that sensor can actually do */ 1005 sd_fsize.width = pix->width; 1006 sd_fsize.height = pix->height; 1007 1008 if (do_crop) { 1009 struct v4l2_rect c = dcmi->crop; 1010 struct v4l2_rect max_rect; 1011 1012 /* 1013 * Adjust crop by making the intersection between 1014 * format resolution request and crop request 1015 */ 1016 max_rect.top = 0; 1017 max_rect.left = 0; 1018 max_rect.width = pix->width; 1019 max_rect.height = pix->height; 1020 v4l2_rect_map_inside(&c, &max_rect); 1021 c.top = clamp_t(s32, c.top, 0, pix->height - c.height); 1022 c.left = clamp_t(s32, c.left, 0, pix->width - c.width); 1023 dcmi->crop = c; 1024 1025 /* Adjust format resolution request to crop */ 1026 pix->width = dcmi->crop.width; 1027 pix->height = dcmi->crop.height; 1028 } 1029 1030 pix->field = V4L2_FIELD_NONE; 1031 pix->bytesperline = pix->width * sd_fmt->bpp; 1032 pix->sizeimage = pix->bytesperline * pix->height; 1033 1034 if (sd_format) 1035 *sd_format = sd_fmt; 1036 if (sd_framesize) 1037 *sd_framesize = sd_fsize; 1038 1039 return 0; 1040 } 1041 1042 static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f) 1043 { 1044 struct v4l2_subdev_format format = { 1045 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1046 }; 1047 const struct dcmi_format *sd_format; 1048 struct dcmi_framesize sd_framesize; 1049 struct v4l2_mbus_framefmt *mf = &format.format; 1050 struct v4l2_pix_format *pix = &f->fmt.pix; 1051 int ret; 1052 1053 /* 1054 * Try format, fmt.width/height could have been changed 1055 * to match sensor capability or crop request 1056 * sd_format & sd_framesize will contain what subdev 1057 * can do for this request. 1058 */ 1059 ret = dcmi_try_fmt(dcmi, f, &sd_format, &sd_framesize); 1060 if (ret) 1061 return ret; 1062 1063 /* Disable crop if JPEG is requested or BT656 bus is selected */ 1064 if (pix->pixelformat == V4L2_PIX_FMT_JPEG && 1065 dcmi->bus_type != V4L2_MBUS_BT656) 1066 dcmi->do_crop = false; 1067 1068 /* pix to mbus format */ 1069 v4l2_fill_mbus_format(mf, pix, 1070 sd_format->mbus_code); 1071 mf->width = sd_framesize.width; 1072 mf->height = sd_framesize.height; 1073 1074 ret = dcmi_pipeline_s_fmt(dcmi, &format); 1075 if (ret < 0) 1076 return ret; 1077 1078 dev_dbg(dcmi->dev, "Sensor format set to 0x%x %ux%u\n", 1079 mf->code, mf->width, mf->height); 1080 dev_dbg(dcmi->dev, "Buffer format set to %4.4s %ux%u\n", 1081 (char *)&pix->pixelformat, 1082 pix->width, pix->height); 1083 1084 dcmi->fmt = *f; 1085 dcmi->sd_format = sd_format; 1086 dcmi->sd_framesize = sd_framesize; 1087 1088 return 0; 1089 } 1090 1091 static int dcmi_s_fmt_vid_cap(struct file *file, void *priv, 1092 struct v4l2_format *f) 1093 { 1094 struct stm32_dcmi *dcmi = video_drvdata(file); 1095 1096 if (vb2_is_streaming(&dcmi->queue)) 1097 return -EBUSY; 1098 1099 return dcmi_set_fmt(dcmi, f); 1100 } 1101 1102 static int dcmi_try_fmt_vid_cap(struct file *file, void *priv, 1103 struct v4l2_format *f) 1104 { 1105 struct stm32_dcmi *dcmi = video_drvdata(file); 1106 1107 return dcmi_try_fmt(dcmi, f, NULL, NULL); 1108 } 1109 1110 static int dcmi_enum_fmt_vid_cap(struct file *file, void *priv, 1111 struct v4l2_fmtdesc *f) 1112 { 1113 struct stm32_dcmi *dcmi = video_drvdata(file); 1114 1115 if (f->index >= dcmi->num_of_sd_formats) 1116 return -EINVAL; 1117 1118 f->pixelformat = dcmi->sd_formats[f->index]->fourcc; 1119 return 0; 1120 } 1121 1122 static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi, 1123 struct v4l2_pix_format *pix) 1124 { 1125 struct v4l2_subdev_format fmt = { 1126 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1127 }; 1128 int ret; 1129 1130 ret = v4l2_subdev_call(dcmi->source, pad, get_fmt, NULL, &fmt); 1131 if (ret) 1132 return ret; 1133 1134 v4l2_fill_pix_format(pix, &fmt.format); 1135 1136 return 0; 1137 } 1138 1139 static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi, 1140 struct v4l2_pix_format *pix) 1141 { 1142 const struct dcmi_format *sd_fmt; 1143 struct v4l2_subdev_format format = { 1144 .which = V4L2_SUBDEV_FORMAT_TRY, 1145 }; 1146 int ret; 1147 1148 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat); 1149 if (!sd_fmt) { 1150 if (!dcmi->num_of_sd_formats) 1151 return -ENODATA; 1152 1153 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1]; 1154 pix->pixelformat = sd_fmt->fourcc; 1155 } 1156 1157 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); 1158 ret = v4l2_subdev_call_state_try(dcmi->source, pad, set_fmt, &format); 1159 if (ret < 0) 1160 return ret; 1161 1162 return 0; 1163 } 1164 1165 static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi, 1166 struct v4l2_rect *r) 1167 { 1168 struct v4l2_subdev_selection bounds = { 1169 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1170 .target = V4L2_SEL_TGT_CROP_BOUNDS, 1171 }; 1172 unsigned int max_width, max_height, max_pixsize; 1173 struct v4l2_pix_format pix; 1174 unsigned int i; 1175 int ret; 1176 1177 /* 1178 * Get sensor bounds first 1179 */ 1180 ret = v4l2_subdev_call(dcmi->source, pad, get_selection, 1181 NULL, &bounds); 1182 if (!ret) 1183 *r = bounds.r; 1184 if (ret != -ENOIOCTLCMD) 1185 return ret; 1186 1187 /* 1188 * If selection is not implemented, 1189 * fallback by enumerating sensor frame sizes 1190 * and take the largest one 1191 */ 1192 max_width = 0; 1193 max_height = 0; 1194 max_pixsize = 0; 1195 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 1196 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i]; 1197 unsigned int pixsize = fsize->width * fsize->height; 1198 1199 if (pixsize > max_pixsize) { 1200 max_pixsize = pixsize; 1201 max_width = fsize->width; 1202 max_height = fsize->height; 1203 } 1204 } 1205 if (max_pixsize > 0) { 1206 r->top = 0; 1207 r->left = 0; 1208 r->width = max_width; 1209 r->height = max_height; 1210 return 0; 1211 } 1212 1213 /* 1214 * If frame sizes enumeration is not implemented, 1215 * fallback by getting current sensor frame size 1216 */ 1217 ret = dcmi_get_sensor_format(dcmi, &pix); 1218 if (ret) 1219 return ret; 1220 1221 r->top = 0; 1222 r->left = 0; 1223 r->width = pix.width; 1224 r->height = pix.height; 1225 1226 return 0; 1227 } 1228 1229 static int dcmi_g_selection(struct file *file, void *fh, 1230 struct v4l2_selection *s) 1231 { 1232 struct stm32_dcmi *dcmi = video_drvdata(file); 1233 1234 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1235 return -EINVAL; 1236 1237 switch (s->target) { 1238 case V4L2_SEL_TGT_CROP_DEFAULT: 1239 case V4L2_SEL_TGT_CROP_BOUNDS: 1240 s->r = dcmi->sd_bounds; 1241 return 0; 1242 case V4L2_SEL_TGT_CROP: 1243 if (dcmi->do_crop) { 1244 s->r = dcmi->crop; 1245 } else { 1246 s->r.top = 0; 1247 s->r.left = 0; 1248 s->r.width = dcmi->fmt.fmt.pix.width; 1249 s->r.height = dcmi->fmt.fmt.pix.height; 1250 } 1251 break; 1252 default: 1253 return -EINVAL; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int dcmi_s_selection(struct file *file, void *priv, 1260 struct v4l2_selection *s) 1261 { 1262 struct stm32_dcmi *dcmi = video_drvdata(file); 1263 struct v4l2_rect r = s->r; 1264 struct v4l2_rect max_rect; 1265 struct v4l2_pix_format pix; 1266 1267 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || 1268 s->target != V4L2_SEL_TGT_CROP) 1269 return -EINVAL; 1270 1271 /* Reset sensor resolution to max resolution */ 1272 pix.pixelformat = dcmi->fmt.fmt.pix.pixelformat; 1273 pix.width = dcmi->sd_bounds.width; 1274 pix.height = dcmi->sd_bounds.height; 1275 dcmi_set_sensor_format(dcmi, &pix); 1276 1277 /* 1278 * Make the intersection between 1279 * sensor resolution 1280 * and crop request 1281 */ 1282 max_rect.top = 0; 1283 max_rect.left = 0; 1284 max_rect.width = pix.width; 1285 max_rect.height = pix.height; 1286 v4l2_rect_map_inside(&r, &max_rect); 1287 r.top = clamp_t(s32, r.top, 0, pix.height - r.height); 1288 r.left = clamp_t(s32, r.left, 0, pix.width - r.width); 1289 1290 if (!(r.top == dcmi->sd_bounds.top && 1291 r.left == dcmi->sd_bounds.left && 1292 r.width == dcmi->sd_bounds.width && 1293 r.height == dcmi->sd_bounds.height)) { 1294 /* Crop if request is different than sensor resolution */ 1295 dcmi->do_crop = true; 1296 dcmi->crop = r; 1297 dev_dbg(dcmi->dev, "s_selection: crop %ux%u@(%u,%u) from %ux%u\n", 1298 r.width, r.height, r.left, r.top, 1299 pix.width, pix.height); 1300 } else { 1301 /* Disable crop */ 1302 dcmi->do_crop = false; 1303 dev_dbg(dcmi->dev, "s_selection: crop is disabled\n"); 1304 } 1305 1306 s->r = r; 1307 return 0; 1308 } 1309 1310 static int dcmi_querycap(struct file *file, void *priv, 1311 struct v4l2_capability *cap) 1312 { 1313 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 1314 strscpy(cap->card, "STM32 Camera Memory Interface", 1315 sizeof(cap->card)); 1316 strscpy(cap->bus_info, "platform:dcmi", sizeof(cap->bus_info)); 1317 return 0; 1318 } 1319 1320 static int dcmi_enum_input(struct file *file, void *priv, 1321 struct v4l2_input *i) 1322 { 1323 if (i->index != 0) 1324 return -EINVAL; 1325 1326 i->type = V4L2_INPUT_TYPE_CAMERA; 1327 strscpy(i->name, "Camera", sizeof(i->name)); 1328 return 0; 1329 } 1330 1331 static int dcmi_g_input(struct file *file, void *priv, unsigned int *i) 1332 { 1333 *i = 0; 1334 return 0; 1335 } 1336 1337 static int dcmi_s_input(struct file *file, void *priv, unsigned int i) 1338 { 1339 if (i > 0) 1340 return -EINVAL; 1341 return 0; 1342 } 1343 1344 static int dcmi_enum_framesizes(struct file *file, void *fh, 1345 struct v4l2_frmsizeenum *fsize) 1346 { 1347 struct stm32_dcmi *dcmi = video_drvdata(file); 1348 const struct dcmi_format *sd_fmt; 1349 struct v4l2_subdev_frame_size_enum fse = { 1350 .index = fsize->index, 1351 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1352 }; 1353 int ret; 1354 1355 sd_fmt = find_format_by_fourcc(dcmi, fsize->pixel_format); 1356 if (!sd_fmt) 1357 return -EINVAL; 1358 1359 fse.code = sd_fmt->mbus_code; 1360 1361 ret = v4l2_subdev_call(dcmi->source, pad, enum_frame_size, 1362 NULL, &fse); 1363 if (ret) 1364 return ret; 1365 1366 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1367 fsize->discrete.width = fse.max_width; 1368 fsize->discrete.height = fse.max_height; 1369 1370 return 0; 1371 } 1372 1373 static int dcmi_g_parm(struct file *file, void *priv, 1374 struct v4l2_streamparm *p) 1375 { 1376 struct stm32_dcmi *dcmi = video_drvdata(file); 1377 1378 return v4l2_g_parm_cap(video_devdata(file), dcmi->source, p); 1379 } 1380 1381 static int dcmi_s_parm(struct file *file, void *priv, 1382 struct v4l2_streamparm *p) 1383 { 1384 struct stm32_dcmi *dcmi = video_drvdata(file); 1385 1386 return v4l2_s_parm_cap(video_devdata(file), dcmi->source, p); 1387 } 1388 1389 static int dcmi_enum_frameintervals(struct file *file, void *fh, 1390 struct v4l2_frmivalenum *fival) 1391 { 1392 struct stm32_dcmi *dcmi = video_drvdata(file); 1393 const struct dcmi_format *sd_fmt; 1394 struct v4l2_subdev_frame_interval_enum fie = { 1395 .index = fival->index, 1396 .width = fival->width, 1397 .height = fival->height, 1398 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1399 }; 1400 int ret; 1401 1402 sd_fmt = find_format_by_fourcc(dcmi, fival->pixel_format); 1403 if (!sd_fmt) 1404 return -EINVAL; 1405 1406 fie.code = sd_fmt->mbus_code; 1407 1408 ret = v4l2_subdev_call(dcmi->source, pad, 1409 enum_frame_interval, NULL, &fie); 1410 if (ret) 1411 return ret; 1412 1413 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; 1414 fival->discrete = fie.interval; 1415 1416 return 0; 1417 } 1418 1419 static const struct of_device_id stm32_dcmi_of_match[] = { 1420 { .compatible = "st,stm32-dcmi"}, 1421 { /* end node */ }, 1422 }; 1423 MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match); 1424 1425 static int dcmi_open(struct file *file) 1426 { 1427 struct stm32_dcmi *dcmi = video_drvdata(file); 1428 struct v4l2_subdev *sd = dcmi->source; 1429 int ret; 1430 1431 if (mutex_lock_interruptible(&dcmi->lock)) 1432 return -ERESTARTSYS; 1433 1434 ret = v4l2_fh_open(file); 1435 if (ret < 0) 1436 goto unlock; 1437 1438 if (!v4l2_fh_is_singular_file(file)) 1439 goto fh_rel; 1440 1441 ret = v4l2_subdev_call(sd, core, s_power, 1); 1442 if (ret < 0 && ret != -ENOIOCTLCMD) 1443 goto fh_rel; 1444 1445 ret = dcmi_set_fmt(dcmi, &dcmi->fmt); 1446 if (ret) 1447 v4l2_subdev_call(sd, core, s_power, 0); 1448 fh_rel: 1449 if (ret) 1450 v4l2_fh_release(file); 1451 unlock: 1452 mutex_unlock(&dcmi->lock); 1453 return ret; 1454 } 1455 1456 static int dcmi_release(struct file *file) 1457 { 1458 struct stm32_dcmi *dcmi = video_drvdata(file); 1459 struct v4l2_subdev *sd = dcmi->source; 1460 bool fh_singular; 1461 int ret; 1462 1463 mutex_lock(&dcmi->lock); 1464 1465 fh_singular = v4l2_fh_is_singular_file(file); 1466 1467 ret = _vb2_fop_release(file, NULL); 1468 1469 if (fh_singular) 1470 v4l2_subdev_call(sd, core, s_power, 0); 1471 1472 mutex_unlock(&dcmi->lock); 1473 1474 return ret; 1475 } 1476 1477 static const struct v4l2_ioctl_ops dcmi_ioctl_ops = { 1478 .vidioc_querycap = dcmi_querycap, 1479 1480 .vidioc_try_fmt_vid_cap = dcmi_try_fmt_vid_cap, 1481 .vidioc_g_fmt_vid_cap = dcmi_g_fmt_vid_cap, 1482 .vidioc_s_fmt_vid_cap = dcmi_s_fmt_vid_cap, 1483 .vidioc_enum_fmt_vid_cap = dcmi_enum_fmt_vid_cap, 1484 .vidioc_g_selection = dcmi_g_selection, 1485 .vidioc_s_selection = dcmi_s_selection, 1486 1487 .vidioc_enum_input = dcmi_enum_input, 1488 .vidioc_g_input = dcmi_g_input, 1489 .vidioc_s_input = dcmi_s_input, 1490 1491 .vidioc_g_parm = dcmi_g_parm, 1492 .vidioc_s_parm = dcmi_s_parm, 1493 1494 .vidioc_enum_framesizes = dcmi_enum_framesizes, 1495 .vidioc_enum_frameintervals = dcmi_enum_frameintervals, 1496 1497 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1498 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1499 .vidioc_querybuf = vb2_ioctl_querybuf, 1500 .vidioc_qbuf = vb2_ioctl_qbuf, 1501 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1502 .vidioc_expbuf = vb2_ioctl_expbuf, 1503 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1504 .vidioc_streamon = vb2_ioctl_streamon, 1505 .vidioc_streamoff = vb2_ioctl_streamoff, 1506 1507 .vidioc_log_status = v4l2_ctrl_log_status, 1508 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1509 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1510 }; 1511 1512 static const struct v4l2_file_operations dcmi_fops = { 1513 .owner = THIS_MODULE, 1514 .unlocked_ioctl = video_ioctl2, 1515 .open = dcmi_open, 1516 .release = dcmi_release, 1517 .poll = vb2_fop_poll, 1518 .mmap = vb2_fop_mmap, 1519 #ifndef CONFIG_MMU 1520 .get_unmapped_area = vb2_fop_get_unmapped_area, 1521 #endif 1522 .read = vb2_fop_read, 1523 }; 1524 1525 static int dcmi_set_default_fmt(struct stm32_dcmi *dcmi) 1526 { 1527 struct v4l2_format f = { 1528 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, 1529 .fmt.pix = { 1530 .width = CIF_WIDTH, 1531 .height = CIF_HEIGHT, 1532 .field = V4L2_FIELD_NONE, 1533 .pixelformat = dcmi->sd_formats[0]->fourcc, 1534 }, 1535 }; 1536 int ret; 1537 1538 ret = dcmi_try_fmt(dcmi, &f, NULL, NULL); 1539 if (ret) 1540 return ret; 1541 dcmi->sd_format = dcmi->sd_formats[0]; 1542 dcmi->fmt = f; 1543 return 0; 1544 } 1545 1546 static const struct dcmi_format dcmi_formats[] = { 1547 { 1548 .fourcc = V4L2_PIX_FMT_RGB565, 1549 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 1550 .bpp = 2, 1551 }, { 1552 .fourcc = V4L2_PIX_FMT_RGB565, 1553 .mbus_code = MEDIA_BUS_FMT_RGB565_1X16, 1554 .bpp = 2, 1555 }, { 1556 .fourcc = V4L2_PIX_FMT_YUYV, 1557 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 1558 .bpp = 2, 1559 }, { 1560 .fourcc = V4L2_PIX_FMT_YUYV, 1561 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, 1562 .bpp = 2, 1563 }, { 1564 .fourcc = V4L2_PIX_FMT_UYVY, 1565 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, 1566 .bpp = 2, 1567 }, { 1568 .fourcc = V4L2_PIX_FMT_UYVY, 1569 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, 1570 .bpp = 2, 1571 }, { 1572 .fourcc = V4L2_PIX_FMT_JPEG, 1573 .mbus_code = MEDIA_BUS_FMT_JPEG_1X8, 1574 .bpp = 1, 1575 }, { 1576 .fourcc = V4L2_PIX_FMT_SBGGR8, 1577 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 1578 .bpp = 1, 1579 }, { 1580 .fourcc = V4L2_PIX_FMT_SGBRG8, 1581 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, 1582 .bpp = 1, 1583 }, { 1584 .fourcc = V4L2_PIX_FMT_SGRBG8, 1585 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, 1586 .bpp = 1, 1587 }, { 1588 .fourcc = V4L2_PIX_FMT_SRGGB8, 1589 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, 1590 .bpp = 1, 1591 }, { 1592 .fourcc = V4L2_PIX_FMT_SBGGR10, 1593 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, 1594 .bpp = 2, 1595 }, { 1596 .fourcc = V4L2_PIX_FMT_SGBRG10, 1597 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, 1598 .bpp = 2, 1599 }, { 1600 .fourcc = V4L2_PIX_FMT_SGRBG10, 1601 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, 1602 .bpp = 2, 1603 }, { 1604 .fourcc = V4L2_PIX_FMT_SRGGB10, 1605 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, 1606 .bpp = 2, 1607 }, { 1608 .fourcc = V4L2_PIX_FMT_SBGGR12, 1609 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, 1610 .bpp = 2, 1611 }, { 1612 .fourcc = V4L2_PIX_FMT_SGBRG12, 1613 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, 1614 .bpp = 2, 1615 }, { 1616 .fourcc = V4L2_PIX_FMT_SGRBG12, 1617 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, 1618 .bpp = 2, 1619 }, { 1620 .fourcc = V4L2_PIX_FMT_SRGGB12, 1621 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, 1622 .bpp = 2, 1623 }, { 1624 .fourcc = V4L2_PIX_FMT_SBGGR14, 1625 .mbus_code = MEDIA_BUS_FMT_SBGGR14_1X14, 1626 .bpp = 2, 1627 }, { 1628 .fourcc = V4L2_PIX_FMT_SGBRG14, 1629 .mbus_code = MEDIA_BUS_FMT_SGBRG14_1X14, 1630 .bpp = 2, 1631 }, { 1632 .fourcc = V4L2_PIX_FMT_SGRBG14, 1633 .mbus_code = MEDIA_BUS_FMT_SGRBG14_1X14, 1634 .bpp = 2, 1635 }, { 1636 .fourcc = V4L2_PIX_FMT_SRGGB14, 1637 .mbus_code = MEDIA_BUS_FMT_SRGGB14_1X14, 1638 .bpp = 2, 1639 }, 1640 }; 1641 1642 static int dcmi_formats_init(struct stm32_dcmi *dcmi) 1643 { 1644 const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)]; 1645 unsigned int num_fmts = 0, i, j; 1646 struct v4l2_subdev *subdev = dcmi->source; 1647 struct v4l2_subdev_mbus_code_enum mbus_code = { 1648 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1649 }; 1650 1651 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, 1652 NULL, &mbus_code)) { 1653 for (i = 0; i < ARRAY_SIZE(dcmi_formats); i++) { 1654 if (dcmi_formats[i].mbus_code != mbus_code.code) 1655 continue; 1656 1657 /* Exclude JPEG if BT656 bus is selected */ 1658 if (dcmi_formats[i].fourcc == V4L2_PIX_FMT_JPEG && 1659 dcmi->bus_type == V4L2_MBUS_BT656) 1660 continue; 1661 1662 /* Code supported, have we got this fourcc yet? */ 1663 for (j = 0; j < num_fmts; j++) 1664 if (sd_fmts[j]->fourcc == 1665 dcmi_formats[i].fourcc) { 1666 /* Already available */ 1667 dev_dbg(dcmi->dev, "Skipping fourcc/code: %4.4s/0x%x\n", 1668 (char *)&sd_fmts[j]->fourcc, 1669 mbus_code.code); 1670 break; 1671 } 1672 if (j == num_fmts) { 1673 /* New */ 1674 sd_fmts[num_fmts++] = dcmi_formats + i; 1675 dev_dbg(dcmi->dev, "Supported fourcc/code: %4.4s/0x%x\n", 1676 (char *)&sd_fmts[num_fmts - 1]->fourcc, 1677 sd_fmts[num_fmts - 1]->mbus_code); 1678 } 1679 } 1680 mbus_code.index++; 1681 } 1682 1683 if (!num_fmts) 1684 return -ENXIO; 1685 1686 dcmi->num_of_sd_formats = num_fmts; 1687 dcmi->sd_formats = devm_kcalloc(dcmi->dev, 1688 num_fmts, sizeof(struct dcmi_format *), 1689 GFP_KERNEL); 1690 if (!dcmi->sd_formats) { 1691 dev_err(dcmi->dev, "Could not allocate memory\n"); 1692 return -ENOMEM; 1693 } 1694 1695 memcpy(dcmi->sd_formats, sd_fmts, 1696 num_fmts * sizeof(struct dcmi_format *)); 1697 dcmi->sd_format = dcmi->sd_formats[0]; 1698 1699 return 0; 1700 } 1701 1702 static int dcmi_framesizes_init(struct stm32_dcmi *dcmi) 1703 { 1704 unsigned int num_fsize = 0; 1705 struct v4l2_subdev *subdev = dcmi->source; 1706 struct v4l2_subdev_frame_size_enum fse = { 1707 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1708 .code = dcmi->sd_format->mbus_code, 1709 }; 1710 unsigned int ret; 1711 unsigned int i; 1712 1713 /* Allocate discrete framesizes array */ 1714 while (!v4l2_subdev_call(subdev, pad, enum_frame_size, 1715 NULL, &fse)) 1716 fse.index++; 1717 1718 num_fsize = fse.index; 1719 if (!num_fsize) 1720 return 0; 1721 1722 dcmi->num_of_sd_framesizes = num_fsize; 1723 dcmi->sd_framesizes = devm_kcalloc(dcmi->dev, num_fsize, 1724 sizeof(struct dcmi_framesize), 1725 GFP_KERNEL); 1726 if (!dcmi->sd_framesizes) { 1727 dev_err(dcmi->dev, "Could not allocate memory\n"); 1728 return -ENOMEM; 1729 } 1730 1731 /* Fill array with sensor supported framesizes */ 1732 dev_dbg(dcmi->dev, "Sensor supports %u frame sizes:\n", num_fsize); 1733 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 1734 fse.index = i; 1735 ret = v4l2_subdev_call(subdev, pad, enum_frame_size, 1736 NULL, &fse); 1737 if (ret) 1738 return ret; 1739 dcmi->sd_framesizes[fse.index].width = fse.max_width; 1740 dcmi->sd_framesizes[fse.index].height = fse.max_height; 1741 dev_dbg(dcmi->dev, "%ux%u\n", fse.max_width, fse.max_height); 1742 } 1743 1744 return 0; 1745 } 1746 1747 static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier) 1748 { 1749 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1750 int ret; 1751 1752 /* 1753 * Now that the graph is complete, 1754 * we search for the source subdevice 1755 * in order to expose it through V4L2 interface 1756 */ 1757 dcmi->source = media_entity_to_v4l2_subdev(dcmi_find_source(dcmi)); 1758 if (!dcmi->source) { 1759 dev_err(dcmi->dev, "Source subdevice not found\n"); 1760 return -ENODEV; 1761 } 1762 1763 dcmi->vdev->ctrl_handler = dcmi->source->ctrl_handler; 1764 1765 ret = dcmi_formats_init(dcmi); 1766 if (ret) { 1767 dev_err(dcmi->dev, "No supported mediabus format found\n"); 1768 return ret; 1769 } 1770 1771 ret = dcmi_framesizes_init(dcmi); 1772 if (ret) { 1773 dev_err(dcmi->dev, "Could not initialize framesizes\n"); 1774 return ret; 1775 } 1776 1777 ret = dcmi_get_sensor_bounds(dcmi, &dcmi->sd_bounds); 1778 if (ret) { 1779 dev_err(dcmi->dev, "Could not get sensor bounds\n"); 1780 return ret; 1781 } 1782 1783 ret = dcmi_set_default_fmt(dcmi); 1784 if (ret) { 1785 dev_err(dcmi->dev, "Could not set default format\n"); 1786 return ret; 1787 } 1788 1789 ret = devm_request_threaded_irq(dcmi->dev, dcmi->irq, dcmi_irq_callback, 1790 dcmi_irq_thread, IRQF_ONESHOT, 1791 dev_name(dcmi->dev), dcmi); 1792 if (ret) { 1793 dev_err(dcmi->dev, "Unable to request irq %d\n", dcmi->irq); 1794 return ret; 1795 } 1796 1797 return 0; 1798 } 1799 1800 static void dcmi_graph_notify_unbind(struct v4l2_async_notifier *notifier, 1801 struct v4l2_subdev *sd, 1802 struct v4l2_async_connection *asd) 1803 { 1804 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1805 1806 dev_dbg(dcmi->dev, "Removing %s\n", video_device_node_name(dcmi->vdev)); 1807 1808 /* Checks internally if vdev has been init or not */ 1809 video_unregister_device(dcmi->vdev); 1810 } 1811 1812 static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier, 1813 struct v4l2_subdev *subdev, 1814 struct v4l2_async_connection *asd) 1815 { 1816 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1817 unsigned int ret; 1818 int src_pad; 1819 1820 dev_dbg(dcmi->dev, "Subdev \"%s\" bound\n", subdev->name); 1821 1822 /* 1823 * Link this sub-device to DCMI, it could be 1824 * a parallel camera sensor or a bridge 1825 */ 1826 src_pad = media_entity_get_fwnode_pad(&subdev->entity, 1827 subdev->fwnode, 1828 MEDIA_PAD_FL_SOURCE); 1829 1830 ret = media_create_pad_link(&subdev->entity, src_pad, 1831 &dcmi->vdev->entity, 0, 1832 MEDIA_LNK_FL_IMMUTABLE | 1833 MEDIA_LNK_FL_ENABLED); 1834 if (ret) 1835 dev_err(dcmi->dev, "Failed to create media pad link with subdev \"%s\"\n", 1836 subdev->name); 1837 else 1838 dev_dbg(dcmi->dev, "DCMI is now linked to \"%s\"\n", 1839 subdev->name); 1840 1841 dcmi->s_subdev = subdev; 1842 1843 return ret; 1844 } 1845 1846 static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = { 1847 .bound = dcmi_graph_notify_bound, 1848 .unbind = dcmi_graph_notify_unbind, 1849 .complete = dcmi_graph_notify_complete, 1850 }; 1851 1852 static int dcmi_graph_init(struct stm32_dcmi *dcmi) 1853 { 1854 struct v4l2_async_connection *asd; 1855 struct device_node *ep; 1856 int ret; 1857 1858 ep = of_graph_get_endpoint_by_regs(dcmi->dev->of_node, 0, -1); 1859 if (!ep) { 1860 dev_err(dcmi->dev, "Failed to get next endpoint\n"); 1861 return -EINVAL; 1862 } 1863 1864 v4l2_async_nf_init(&dcmi->notifier, &dcmi->v4l2_dev); 1865 1866 asd = v4l2_async_nf_add_fwnode_remote(&dcmi->notifier, 1867 of_fwnode_handle(ep), 1868 struct v4l2_async_connection); 1869 1870 of_node_put(ep); 1871 1872 if (IS_ERR(asd)) { 1873 dev_err(dcmi->dev, "Failed to add subdev notifier\n"); 1874 return PTR_ERR(asd); 1875 } 1876 1877 dcmi->notifier.ops = &dcmi_graph_notify_ops; 1878 1879 ret = v4l2_async_nf_register(&dcmi->notifier); 1880 if (ret < 0) { 1881 dev_err(dcmi->dev, "Failed to register notifier\n"); 1882 v4l2_async_nf_cleanup(&dcmi->notifier); 1883 return ret; 1884 } 1885 1886 return 0; 1887 } 1888 1889 static int dcmi_probe(struct platform_device *pdev) 1890 { 1891 struct device_node *np = pdev->dev.of_node; 1892 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; 1893 struct stm32_dcmi *dcmi; 1894 struct vb2_queue *q; 1895 struct dma_chan *chan; 1896 struct dma_slave_caps caps; 1897 struct clk *mclk; 1898 int ret = 0; 1899 1900 dcmi = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dcmi), GFP_KERNEL); 1901 if (!dcmi) 1902 return -ENOMEM; 1903 1904 dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1905 if (IS_ERR(dcmi->rstc)) 1906 return dev_err_probe(&pdev->dev, PTR_ERR(dcmi->rstc), 1907 "Could not get reset control\n"); 1908 1909 /* Get bus characteristics from devicetree */ 1910 np = of_graph_get_endpoint_by_regs(np, 0, -1); 1911 if (!np) { 1912 dev_err(&pdev->dev, "Could not find the endpoint\n"); 1913 return -ENODEV; 1914 } 1915 1916 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep); 1917 of_node_put(np); 1918 if (ret) { 1919 dev_err(&pdev->dev, "Could not parse the endpoint\n"); 1920 return ret; 1921 } 1922 1923 if (ep.bus_type == V4L2_MBUS_CSI2_DPHY) { 1924 dev_err(&pdev->dev, "CSI bus not supported\n"); 1925 return -ENODEV; 1926 } 1927 1928 if (ep.bus_type == V4L2_MBUS_BT656 && 1929 ep.bus.parallel.bus_width != 8) { 1930 dev_err(&pdev->dev, "BT656 bus conflicts with %u bits bus width (8 bits required)\n", 1931 ep.bus.parallel.bus_width); 1932 return -ENODEV; 1933 } 1934 1935 dcmi->bus.flags = ep.bus.parallel.flags; 1936 dcmi->bus.bus_width = ep.bus.parallel.bus_width; 1937 dcmi->bus.data_shift = ep.bus.parallel.data_shift; 1938 dcmi->bus_type = ep.bus_type; 1939 1940 dcmi->irq = platform_get_irq(pdev, 0); 1941 if (dcmi->irq < 0) 1942 return dcmi->irq; 1943 1944 dcmi->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &dcmi->res); 1945 if (IS_ERR(dcmi->regs)) 1946 return PTR_ERR(dcmi->regs); 1947 1948 mclk = devm_clk_get(&pdev->dev, "mclk"); 1949 if (IS_ERR(mclk)) 1950 return dev_err_probe(&pdev->dev, PTR_ERR(mclk), 1951 "Unable to get mclk\n"); 1952 1953 chan = dma_request_chan(&pdev->dev, "tx"); 1954 if (IS_ERR(chan)) 1955 return dev_err_probe(&pdev->dev, PTR_ERR(chan), 1956 "Failed to request DMA channel\n"); 1957 1958 dcmi->dma_max_burst = UINT_MAX; 1959 ret = dma_get_slave_caps(chan, &caps); 1960 if (!ret && caps.max_sg_burst) 1961 dcmi->dma_max_burst = caps.max_sg_burst * DMA_SLAVE_BUSWIDTH_4_BYTES; 1962 1963 spin_lock_init(&dcmi->irqlock); 1964 mutex_init(&dcmi->lock); 1965 mutex_init(&dcmi->dma_lock); 1966 init_completion(&dcmi->complete); 1967 INIT_LIST_HEAD(&dcmi->buffers); 1968 1969 dcmi->dev = &pdev->dev; 1970 dcmi->mclk = mclk; 1971 dcmi->state = STOPPED; 1972 dcmi->dma_chan = chan; 1973 1974 q = &dcmi->queue; 1975 1976 dcmi->v4l2_dev.mdev = &dcmi->mdev; 1977 1978 /* Initialize media device */ 1979 strscpy(dcmi->mdev.model, DRV_NAME, sizeof(dcmi->mdev.model)); 1980 dcmi->mdev.dev = &pdev->dev; 1981 media_device_init(&dcmi->mdev); 1982 1983 /* Initialize the top-level structure */ 1984 ret = v4l2_device_register(&pdev->dev, &dcmi->v4l2_dev); 1985 if (ret) 1986 goto err_media_device_cleanup; 1987 1988 dcmi->vdev = video_device_alloc(); 1989 if (!dcmi->vdev) { 1990 ret = -ENOMEM; 1991 goto err_device_unregister; 1992 } 1993 1994 /* Video node */ 1995 dcmi->vdev->fops = &dcmi_fops; 1996 dcmi->vdev->v4l2_dev = &dcmi->v4l2_dev; 1997 dcmi->vdev->queue = &dcmi->queue; 1998 strscpy(dcmi->vdev->name, KBUILD_MODNAME, sizeof(dcmi->vdev->name)); 1999 dcmi->vdev->release = video_device_release; 2000 dcmi->vdev->ioctl_ops = &dcmi_ioctl_ops; 2001 dcmi->vdev->lock = &dcmi->lock; 2002 dcmi->vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | 2003 V4L2_CAP_READWRITE; 2004 video_set_drvdata(dcmi->vdev, dcmi); 2005 2006 /* Media entity pads */ 2007 dcmi->vid_cap_pad.flags = MEDIA_PAD_FL_SINK; 2008 ret = media_entity_pads_init(&dcmi->vdev->entity, 2009 1, &dcmi->vid_cap_pad); 2010 if (ret) { 2011 dev_err(dcmi->dev, "Failed to init media entity pad\n"); 2012 goto err_device_release; 2013 } 2014 dcmi->vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT; 2015 2016 ret = video_register_device(dcmi->vdev, VFL_TYPE_VIDEO, -1); 2017 if (ret) { 2018 dev_err(dcmi->dev, "Failed to register video device\n"); 2019 goto err_media_entity_cleanup; 2020 } 2021 2022 dev_dbg(dcmi->dev, "Device registered as %s\n", 2023 video_device_node_name(dcmi->vdev)); 2024 2025 /* Buffer queue */ 2026 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 2027 q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; 2028 q->lock = &dcmi->lock; 2029 q->drv_priv = dcmi; 2030 q->buf_struct_size = sizeof(struct dcmi_buf); 2031 q->ops = &dcmi_video_qops; 2032 q->mem_ops = &vb2_dma_contig_memops; 2033 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 2034 q->min_queued_buffers = 2; 2035 q->allow_cache_hints = 1; 2036 q->dev = &pdev->dev; 2037 2038 ret = vb2_queue_init(q); 2039 if (ret < 0) { 2040 dev_err(&pdev->dev, "Failed to initialize vb2 queue\n"); 2041 goto err_media_entity_cleanup; 2042 } 2043 2044 ret = dcmi_graph_init(dcmi); 2045 if (ret < 0) 2046 goto err_media_entity_cleanup; 2047 2048 /* Reset device */ 2049 ret = reset_control_assert(dcmi->rstc); 2050 if (ret) { 2051 dev_err(&pdev->dev, "Failed to assert the reset line\n"); 2052 goto err_cleanup; 2053 } 2054 2055 usleep_range(3000, 5000); 2056 2057 ret = reset_control_deassert(dcmi->rstc); 2058 if (ret) { 2059 dev_err(&pdev->dev, "Failed to deassert the reset line\n"); 2060 goto err_cleanup; 2061 } 2062 2063 dev_info(&pdev->dev, "Probe done\n"); 2064 2065 platform_set_drvdata(pdev, dcmi); 2066 2067 pm_runtime_enable(&pdev->dev); 2068 2069 return 0; 2070 2071 err_cleanup: 2072 v4l2_async_nf_cleanup(&dcmi->notifier); 2073 err_media_entity_cleanup: 2074 media_entity_cleanup(&dcmi->vdev->entity); 2075 err_device_release: 2076 video_device_release(dcmi->vdev); 2077 err_device_unregister: 2078 v4l2_device_unregister(&dcmi->v4l2_dev); 2079 err_media_device_cleanup: 2080 media_device_cleanup(&dcmi->mdev); 2081 dma_release_channel(dcmi->dma_chan); 2082 2083 return ret; 2084 } 2085 2086 static void dcmi_remove(struct platform_device *pdev) 2087 { 2088 struct stm32_dcmi *dcmi = platform_get_drvdata(pdev); 2089 2090 pm_runtime_disable(&pdev->dev); 2091 2092 v4l2_async_nf_unregister(&dcmi->notifier); 2093 v4l2_async_nf_cleanup(&dcmi->notifier); 2094 media_entity_cleanup(&dcmi->vdev->entity); 2095 v4l2_device_unregister(&dcmi->v4l2_dev); 2096 media_device_cleanup(&dcmi->mdev); 2097 2098 dma_release_channel(dcmi->dma_chan); 2099 } 2100 2101 static __maybe_unused int dcmi_runtime_suspend(struct device *dev) 2102 { 2103 struct stm32_dcmi *dcmi = dev_get_drvdata(dev); 2104 2105 clk_disable_unprepare(dcmi->mclk); 2106 2107 return 0; 2108 } 2109 2110 static __maybe_unused int dcmi_runtime_resume(struct device *dev) 2111 { 2112 struct stm32_dcmi *dcmi = dev_get_drvdata(dev); 2113 int ret; 2114 2115 ret = clk_prepare_enable(dcmi->mclk); 2116 if (ret) 2117 dev_err(dev, "%s: Failed to prepare_enable clock\n", __func__); 2118 2119 return ret; 2120 } 2121 2122 static __maybe_unused int dcmi_suspend(struct device *dev) 2123 { 2124 /* disable clock */ 2125 pm_runtime_force_suspend(dev); 2126 2127 /* change pinctrl state */ 2128 pinctrl_pm_select_sleep_state(dev); 2129 2130 return 0; 2131 } 2132 2133 static __maybe_unused int dcmi_resume(struct device *dev) 2134 { 2135 /* restore pinctl default state */ 2136 pinctrl_pm_select_default_state(dev); 2137 2138 /* clock enable */ 2139 pm_runtime_force_resume(dev); 2140 2141 return 0; 2142 } 2143 2144 static const struct dev_pm_ops dcmi_pm_ops = { 2145 SET_SYSTEM_SLEEP_PM_OPS(dcmi_suspend, dcmi_resume) 2146 SET_RUNTIME_PM_OPS(dcmi_runtime_suspend, 2147 dcmi_runtime_resume, NULL) 2148 }; 2149 2150 static struct platform_driver stm32_dcmi_driver = { 2151 .probe = dcmi_probe, 2152 .remove_new = dcmi_remove, 2153 .driver = { 2154 .name = DRV_NAME, 2155 .of_match_table = of_match_ptr(stm32_dcmi_of_match), 2156 .pm = &dcmi_pm_ops, 2157 }, 2158 }; 2159 2160 module_platform_driver(stm32_dcmi_driver); 2161 2162 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2163 MODULE_AUTHOR("Hugues Fruchet <hugues.fruchet@st.com>"); 2164 MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface driver"); 2165 MODULE_LICENSE("GPL"); 2166