1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Register definition file for Samsung MFC V8.x Interface (FIMV) driver 4 * 5 * Copyright (c) 2014 Samsung Electronics Co., Ltd. 6 * http://www.samsung.com/ 7 */ 8 9 #ifndef _REGS_MFC_V8_H 10 #define _REGS_MFC_V8_H 11 12 #include <linux/sizes.h> 13 #include "regs-mfc-v7.h" 14 15 /* Additional registers for v8 */ 16 #define S5P_FIMV_D_MVC_NUM_VIEWS_V8 0xf104 17 #define S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8 0xf108 18 #define S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8 0xf144 19 #define S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8 0xf148 20 #define S5P_FIMV_D_THIRD_PLANE_DPB_SIZE_V8 0xf14C 21 #define S5P_FIMV_D_MV_BUFFER_SIZE_V8 0xf150 22 23 #define S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8 0xf138 24 #define S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8 0xf13c 25 #define S5P_FIMV_D_THIRD_PLANE_DPB_STRIDE_SIZE_V8 0xf140 26 27 #define S5P_FIMV_D_FIRST_PLANE_DPB_V8 0xf160 28 #define S5P_FIMV_D_SECOND_PLANE_DPB_V8 0xf260 29 #define S5P_FIMV_D_THIRD_PLANE_DPB_V8 0xf360 30 #define S5P_FIMV_D_MV_BUFFER_V8 0xf460 31 32 #define S5P_FIMV_D_NUM_MV_V8 0xf134 33 #define S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8 0xf154 34 35 #define S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8 0xf560 36 #define S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8 0xf564 37 38 #define S5P_FIMV_D_CPB_BUFFER_ADDR_V8 0xf5b0 39 #define S5P_FIMV_D_CPB_BUFFER_SIZE_V8 0xf5b4 40 #define S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8 0xf5bc 41 #define S5P_FIMV_D_CPB_BUFFER_OFFSET_V8 0xf5c0 42 #define S5P_FIMV_D_SLICE_IF_ENABLE_V8 0xf5c4 43 #define S5P_FIMV_D_STREAM_DATA_SIZE_V8 0xf5d0 44 45 /* Display information register */ 46 #define S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8 0xf600 47 #define S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8 0xf604 48 49 /* Display status */ 50 #define S5P_FIMV_D_DISPLAY_STATUS_V8 0xf608 51 52 #define S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8 0xf60c 53 #define S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8 0xf610 54 55 #define S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8 0xf618 56 #define S5P_FIMV_D_DISPLAY_CROP_INFO1_V8 0xf61c 57 #define S5P_FIMV_D_DISPLAY_CROP_INFO2_V8 0xf620 58 #define S5P_FIMV_D_DISPLAY_PICTURE_PROFILE_V8 0xf624 59 60 /* Decoded picture information register */ 61 #define S5P_FIMV_D_DECODED_STATUS_V8 0xf644 62 #define S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8 0xf648 63 #define S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8 0xf64c 64 #define S5P_FIMV_D_DECODED_THIRD_PLANE_ADDR_V8 0xf650 65 #define S5P_FIMV_D_DECODED_FRAME_TYPE_V8 0xf654 66 #define S5P_FIMV_D_DECODED_NAL_SIZE_V8 0xf664 67 68 /* Returned value register for specific setting */ 69 #define S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8 0xf674 70 #define S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8 0xf678 71 #define S5P_FIMV_D_MVC_VIEW_ID_V8 0xf6d8 72 73 /* SEI related information */ 74 #define S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8 0xf6dc 75 76 /* Encoder Registers */ 77 #define S5P_FIMV_E_FIXED_PICTURE_QP_V8 0xf794 78 #define S5P_FIMV_E_RC_CONFIG_V8 0xf798 79 #define S5P_FIMV_E_RC_QP_BOUND_V8 0xf79c 80 #define S5P_FIMV_E_RC_RPARAM_V8 0xf7a4 81 #define S5P_FIMV_E_MB_RC_CONFIG_V8 0xf7a8 82 #define S5P_FIMV_E_PADDING_CTRL_V8 0xf7ac 83 #define S5P_FIMV_E_MV_HOR_RANGE_V8 0xf7b4 84 #define S5P_FIMV_E_MV_VER_RANGE_V8 0xf7b8 85 86 #define S5P_FIMV_E_VBV_BUFFER_SIZE_V8 0xf78c 87 #define S5P_FIMV_E_VBV_INIT_DELAY_V8 0xf790 88 #define S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8 0xf894 89 90 #define S5P_FIMV_E_ASPECT_RATIO_V8 0xfb4c 91 #define S5P_FIMV_E_EXTENDED_SAR_V8 0xfb50 92 #define S5P_FIMV_E_H264_OPTIONS_V8 0xfb54 93 94 /* MFCv8 Context buffer sizes */ 95 #define MFC_CTX_BUF_SIZE_V8 (36 * SZ_1K) /* 36KB */ 96 #define MFC_H264_DEC_CTX_BUF_SIZE_V8 (2 * SZ_1M) /* 2MB */ 97 #define MFC_OTHER_DEC_CTX_BUF_SIZE_V8 (20 * SZ_1K) /* 20KB */ 98 #define MFC_H264_ENC_CTX_BUF_SIZE_V8 (100 * SZ_1K) /* 100KB */ 99 #define MFC_OTHER_ENC_CTX_BUF_SIZE_V8 (10 * SZ_1K) /* 10KB */ 100 101 /* Buffer size defines */ 102 #define S5P_FIMV_TMV_BUFFER_SIZE_V8(w, h) (((w) + 1) * ((h) + 1) * 8) 103 104 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(w, h) (((w) * 704) + 2176) 105 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(w, h) \ 106 (((w) * 576 + (h) * 128) + 4128) 107 108 #define S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(w, h) \ 109 (((w) * 592) + 2336) 110 #define S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(w, h) \ 111 (((w) * 576) + 10512 + \ 112 ((((((w) * 16) * ((h) * 16)) * 3) / 2) * 4)) 113 #define S5P_FIMV_ME_BUFFER_SIZE_V8(imw, imh, mbw, mbh) \ 114 ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \ 115 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16)) 116 117 /* BUffer alignment defines */ 118 #define S5P_FIMV_D_ALIGN_PLANE_SIZE_V8 64 119 120 /* MFCv8 variant defines */ 121 #define MAX_FW_SIZE_V8 (SZ_512K) /* 512KB */ 122 #define MAX_CPB_SIZE_V8 (3 * SZ_1M) /* 3MB */ 123 #define MFC_VERSION_V8 0x80 124 #define MFC_NUM_PORTS_V8 1 125 126 #endif /*_REGS_MFC_V8_H*/ 127