1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* linux/drivers/media/platform/samsung/s5p-jpeg/jpeg-regs.h 3 * 4 * Register definition file for Samsung JPEG codec driver 5 * 6 * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. 7 * http://www.samsung.com 8 * 9 * Author: Andrzej Pietrasiewicz <andrzejtp2010@gmail.com> 10 * Author: Jacek Anaszewski <j.anaszewski@samsung.com> 11 */ 12 13 #ifndef JPEG_REGS_H_ 14 #define JPEG_REGS_H_ 15 16 /* Register and bit definitions for S5PC210 */ 17 18 /* JPEG mode register */ 19 #define S5P_JPGMOD 0x00 20 #define S5P_PROC_MODE_MASK (0x1 << 3) 21 #define S5P_PROC_MODE_DECOMPR (0x1 << 3) 22 #define S5P_PROC_MODE_COMPR (0x0 << 3) 23 #define S5P_SUBSAMPLING_MODE_MASK 0x7 24 #define S5P_SUBSAMPLING_MODE_444 (0x0 << 0) 25 #define S5P_SUBSAMPLING_MODE_422 (0x1 << 0) 26 #define S5P_SUBSAMPLING_MODE_420 (0x2 << 0) 27 #define S5P_SUBSAMPLING_MODE_GRAY (0x3 << 0) 28 29 /* JPEG operation status register */ 30 #define S5P_JPGOPR 0x04 31 32 /* Quantization tables*/ 33 #define S5P_JPG_QTBL 0x08 34 #define S5P_QT_NUMt_SHIFT(t) (((t) - 1) << 1) 35 #define S5P_QT_NUMt_MASK(t) (0x3 << S5P_QT_NUMt_SHIFT(t)) 36 37 /* Huffman tables */ 38 #define S5P_JPG_HTBL 0x0c 39 #define S5P_HT_NUMt_AC_SHIFT(t) (((t) << 1) - 1) 40 #define S5P_HT_NUMt_AC_MASK(t) (0x1 << S5P_HT_NUMt_AC_SHIFT(t)) 41 42 #define S5P_HT_NUMt_DC_SHIFT(t) (((t) - 1) << 1) 43 #define S5P_HT_NUMt_DC_MASK(t) (0x1 << S5P_HT_NUMt_DC_SHIFT(t)) 44 45 /* JPEG restart interval register upper byte */ 46 #define S5P_JPGDRI_U 0x10 47 48 /* JPEG restart interval register lower byte */ 49 #define S5P_JPGDRI_L 0x14 50 51 /* JPEG vertical resolution register upper byte */ 52 #define S5P_JPGY_U 0x18 53 54 /* JPEG vertical resolution register lower byte */ 55 #define S5P_JPGY_L 0x1c 56 57 /* JPEG horizontal resolution register upper byte */ 58 #define S5P_JPGX_U 0x20 59 60 /* JPEG horizontal resolution register lower byte */ 61 #define S5P_JPGX_L 0x24 62 63 /* JPEG byte count register upper byte */ 64 #define S5P_JPGCNT_U 0x28 65 66 /* JPEG byte count register middle byte */ 67 #define S5P_JPGCNT_M 0x2c 68 69 /* JPEG byte count register lower byte */ 70 #define S5P_JPGCNT_L 0x30 71 72 /* JPEG interrupt setting register */ 73 #define S5P_JPGINTSE 0x34 74 #define S5P_RSTm_INT_EN_MASK (0x1 << 7) 75 #define S5P_RSTm_INT_EN (0x1 << 7) 76 #define S5P_DATA_NUM_INT_EN_MASK (0x1 << 6) 77 #define S5P_DATA_NUM_INT_EN (0x1 << 6) 78 #define S5P_FINAL_MCU_NUM_INT_EN_MASK (0x1 << 5) 79 #define S5P_FINAL_MCU_NUM_INT_EN (0x1 << 5) 80 81 /* JPEG interrupt status register */ 82 #define S5P_JPGINTST 0x38 83 #define S5P_RESULT_STAT_SHIFT 6 84 #define S5P_RESULT_STAT_MASK (0x1 << S5P_RESULT_STAT_SHIFT) 85 #define S5P_STREAM_STAT_SHIFT 5 86 #define S5P_STREAM_STAT_MASK (0x1 << S5P_STREAM_STAT_SHIFT) 87 88 /* JPEG command register */ 89 #define S5P_JPGCOM 0x4c 90 #define S5P_INT_RELEASE (0x1 << 2) 91 92 /* Raw image data r/w address register */ 93 #define S5P_JPG_IMGADR 0x50 94 95 /* JPEG file r/w address register */ 96 #define S5P_JPG_JPGADR 0x58 97 98 /* Coefficient for RGB-to-YCbCr converter register */ 99 #define S5P_JPG_COEF(n) (0x5c + (((n) - 1) << 2)) 100 #define S5P_COEFn_SHIFT(j) ((3 - (j)) << 3) 101 #define S5P_COEFn_MASK(j) (0xff << S5P_COEFn_SHIFT(j)) 102 103 /* JPEG color mode register */ 104 #define S5P_JPGCMOD 0x68 105 #define S5P_MOD_SEL_MASK (0x7 << 5) 106 #define S5P_MOD_SEL_422 (0x1 << 5) 107 #define S5P_MOD_SEL_565 (0x2 << 5) 108 #define S5P_MODE_Y16_MASK (0x1 << 1) 109 #define S5P_MODE_Y16 (0x1 << 1) 110 111 /* JPEG clock control register */ 112 #define S5P_JPGCLKCON 0x6c 113 #define S5P_CLK_DOWN_READY (0x1 << 1) 114 #define S5P_POWER_ON (0x1 << 0) 115 116 /* JPEG start register */ 117 #define S5P_JSTART 0x70 118 119 /* JPEG SW reset register */ 120 #define S5P_JPG_SW_RESET 0x78 121 122 /* JPEG timer setting register */ 123 #define S5P_JPG_TIMER_SE 0x7c 124 #define S5P_TIMER_INT_EN_MASK (0x1UL << 31) 125 #define S5P_TIMER_INT_EN (0x1UL << 31) 126 #define S5P_TIMER_INIT_MASK 0x7fffffff 127 128 /* JPEG timer status register */ 129 #define S5P_JPG_TIMER_ST 0x80 130 #define S5P_TIMER_INT_STAT_SHIFT 31 131 #define S5P_TIMER_INT_STAT_MASK (0x1UL << S5P_TIMER_INT_STAT_SHIFT) 132 #define S5P_TIMER_CNT_SHIFT 0 133 #define S5P_TIMER_CNT_MASK 0x7fffffff 134 135 /* JPEG decompression output format register */ 136 #define S5P_JPG_OUTFORM 0x88 137 #define S5P_DEC_OUT_FORMAT_MASK (0x1 << 0) 138 #define S5P_DEC_OUT_FORMAT_422 (0x0 << 0) 139 #define S5P_DEC_OUT_FORMAT_420 (0x1 << 0) 140 141 /* JPEG version register */ 142 #define S5P_JPG_VERSION 0x8c 143 144 /* JPEG compressed stream size interrupt setting register */ 145 #define S5P_JPG_ENC_STREAM_INTSE 0x98 146 #define S5P_ENC_STREAM_INT_MASK (0x1 << 24) 147 #define S5P_ENC_STREAM_INT_EN (0x1 << 24) 148 #define S5P_ENC_STREAM_BOUND_MASK 0xffffff 149 150 /* JPEG compressed stream size interrupt status register */ 151 #define S5P_JPG_ENC_STREAM_INTST 0x9c 152 #define S5P_ENC_STREAM_INT_STAT_MASK 0x1 153 154 /* JPEG quantizer table register */ 155 #define S5P_JPG_QTBL_CONTENT(n) (0x400 + (n) * 0x100) 156 157 /* JPEG DC Huffman table register */ 158 #define S5P_JPG_HDCTBL(n) (0x800 + (n) * 0x400) 159 160 /* JPEG DC Huffman table register */ 161 #define S5P_JPG_HDCTBLG(n) (0x840 + (n) * 0x400) 162 163 /* JPEG AC Huffman table register */ 164 #define S5P_JPG_HACTBL(n) (0x880 + (n) * 0x400) 165 166 /* JPEG AC Huffman table register */ 167 #define S5P_JPG_HACTBLG(n) (0x8c0 + (n) * 0x400) 168 169 170 /* Register and bit definitions for Exynos 4x12 */ 171 172 /* JPEG Codec Control Registers */ 173 #define EXYNOS4_JPEG_CNTL_REG 0x00 174 #define EXYNOS4_INT_EN_REG 0x04 175 #define EXYNOS4_INT_TIMER_COUNT_REG 0x08 176 #define EXYNOS4_INT_STATUS_REG 0x0c 177 #define EXYNOS4_OUT_MEM_BASE_REG 0x10 178 #define EXYNOS4_JPEG_IMG_SIZE_REG 0x14 179 #define EXYNOS4_IMG_BA_PLANE_1_REG 0x18 180 #define EXYNOS4_IMG_SO_PLANE_1_REG 0x1c 181 #define EXYNOS4_IMG_PO_PLANE_1_REG 0x20 182 #define EXYNOS4_IMG_BA_PLANE_2_REG 0x24 183 #define EXYNOS4_IMG_SO_PLANE_2_REG 0x28 184 #define EXYNOS4_IMG_PO_PLANE_2_REG 0x2c 185 #define EXYNOS4_IMG_BA_PLANE_3_REG 0x30 186 #define EXYNOS4_IMG_SO_PLANE_3_REG 0x34 187 #define EXYNOS4_IMG_PO_PLANE_3_REG 0x38 188 189 #define EXYNOS4_TBL_SEL_REG 0x3c 190 191 #define EXYNOS4_IMG_FMT_REG 0x40 192 193 #define EXYNOS4_BITSTREAM_SIZE_REG 0x44 194 #define EXYNOS4_PADDING_REG 0x48 195 #define EXYNOS4_HUFF_CNT_REG 0x4c 196 #define EXYNOS4_FIFO_STATUS_REG 0x50 197 #define EXYNOS4_DECODE_XY_SIZE_REG 0x54 198 #define EXYNOS4_DECODE_IMG_FMT_REG 0x58 199 200 #define EXYNOS4_QUAN_TBL_ENTRY_REG 0x100 201 #define EXYNOS4_HUFF_TBL_ENTRY_REG 0x200 202 203 204 /****************************************************************/ 205 /* Bit definition part */ 206 /****************************************************************/ 207 208 /* JPEG CNTL Register bit */ 209 #define EXYNOS4_ENC_DEC_MODE_MASK (0xfffffffc << 0) 210 #define EXYNOS4_DEC_MODE (1 << 0) 211 #define EXYNOS4_ENC_MODE (1 << 1) 212 #define EXYNOS4_AUTO_RST_MARKER (1 << 2) 213 #define EXYNOS4_RST_INTERVAL_SHIFT 3 214 #define EXYNOS4_RST_INTERVAL(x) (((x) & 0xffff) \ 215 << EXYNOS4_RST_INTERVAL_SHIFT) 216 #define EXYNOS4_HUF_TBL_EN (1 << 19) 217 #define EXYNOS4_HOR_SCALING_SHIFT 20 218 #define EXYNOS4_HOR_SCALING_MASK (3 << EXYNOS4_HOR_SCALING_SHIFT) 219 #define EXYNOS4_HOR_SCALING(x) (((x) & 0x3) \ 220 << EXYNOS4_HOR_SCALING_SHIFT) 221 #define EXYNOS4_VER_SCALING_SHIFT 22 222 #define EXYNOS4_VER_SCALING_MASK (3 << EXYNOS4_VER_SCALING_SHIFT) 223 #define EXYNOS4_VER_SCALING(x) (((x) & 0x3) \ 224 << EXYNOS4_VER_SCALING_SHIFT) 225 #define EXYNOS4_PADDING (1 << 27) 226 #define EXYNOS4_SYS_INT_EN (1 << 28) 227 #define EXYNOS4_SOFT_RESET_HI (1 << 29) 228 229 /* JPEG INT Register bit */ 230 #define EXYNOS4_INT_EN_MASK (0x1f << 0) 231 #define EXYNOS5433_INT_EN_MASK (0x1ff << 0) 232 #define EXYNOS4_PROT_ERR_INT_EN (1 << 0) 233 #define EXYNOS4_IMG_COMPLETION_INT_EN (1 << 1) 234 #define EXYNOS4_DEC_INVALID_FORMAT_EN (1 << 2) 235 #define EXYNOS4_MULTI_SCAN_ERROR_EN (1 << 3) 236 #define EXYNOS4_FRAME_ERR_EN (1 << 4) 237 #define EXYNOS4_INT_EN_ALL (0x1f << 0) 238 #define EXYNOS5433_INT_EN_ALL (0x1b6 << 0) 239 240 #define EXYNOS4_MOD_REG_PROC_ENC (0 << 3) 241 #define EXYNOS4_MOD_REG_PROC_DEC (1 << 3) 242 243 #define EXYNOS4_MOD_REG_SUBSAMPLE_444 (0 << 0) 244 #define EXYNOS4_MOD_REG_SUBSAMPLE_422 (1 << 0) 245 #define EXYNOS4_MOD_REG_SUBSAMPLE_420 (2 << 0) 246 #define EXYNOS4_MOD_REG_SUBSAMPLE_GRAY (3 << 0) 247 248 249 /* JPEG IMAGE SIZE Register bit */ 250 #define EXYNOS4_X_SIZE_SHIFT 0 251 #define EXYNOS4_X_SIZE_MASK (0xffff << EXYNOS4_X_SIZE_SHIFT) 252 #define EXYNOS4_X_SIZE(x) (((x) & 0xffff) << EXYNOS4_X_SIZE_SHIFT) 253 #define EXYNOS4_Y_SIZE_SHIFT 16 254 #define EXYNOS4_Y_SIZE_MASK (0xffff << EXYNOS4_Y_SIZE_SHIFT) 255 #define EXYNOS4_Y_SIZE(x) (((x) & 0xffff) << EXYNOS4_Y_SIZE_SHIFT) 256 257 /* JPEG IMAGE FORMAT Register bit */ 258 #define EXYNOS4_ENC_IN_FMT_MASK 0xffff0000 259 #define EXYNOS4_ENC_GRAY_IMG (0 << 0) 260 #define EXYNOS4_ENC_RGB_IMG (1 << 0) 261 #define EXYNOS4_ENC_YUV_444_IMG (2 << 0) 262 #define EXYNOS4_ENC_YUV_422_IMG (3 << 0) 263 #define EXYNOS4_ENC_YUV_440_IMG (4 << 0) 264 265 #define EXYNOS4_DEC_GRAY_IMG (0 << 0) 266 #define EXYNOS4_DEC_RGB_IMG (1 << 0) 267 #define EXYNOS4_DEC_YUV_444_IMG (2 << 0) 268 #define EXYNOS4_DEC_YUV_422_IMG (3 << 0) 269 #define EXYNOS4_DEC_YUV_420_IMG (4 << 0) 270 271 #define EXYNOS4_GRAY_IMG_IP_SHIFT 3 272 #define EXYNOS4_GRAY_IMG_IP_MASK (7 << EXYNOS4_GRAY_IMG_IP_SHIFT) 273 #define EXYNOS4_GRAY_IMG_IP (4 << EXYNOS4_GRAY_IMG_IP_SHIFT) 274 275 #define EXYNOS4_RGB_IP_SHIFT 6 276 #define EXYNOS4_RGB_IP_MASK (7 << EXYNOS4_RGB_IP_SHIFT) 277 #define EXYNOS4_RGB_IP_RGB_16BIT_IMG (4 << EXYNOS4_RGB_IP_SHIFT) 278 #define EXYNOS4_RGB_IP_RGB_32BIT_IMG (5 << EXYNOS4_RGB_IP_SHIFT) 279 280 #define EXYNOS4_YUV_444_IP_SHIFT 9 281 #define EXYNOS4_YUV_444_IP_MASK (7 << EXYNOS4_YUV_444_IP_SHIFT) 282 #define EXYNOS4_YUV_444_IP_YUV_444_2P_IMG (4 << EXYNOS4_YUV_444_IP_SHIFT) 283 #define EXYNOS4_YUV_444_IP_YUV_444_3P_IMG (5 << EXYNOS4_YUV_444_IP_SHIFT) 284 285 #define EXYNOS4_YUV_422_IP_SHIFT 12 286 #define EXYNOS4_YUV_422_IP_MASK (7 << EXYNOS4_YUV_422_IP_SHIFT) 287 #define EXYNOS4_YUV_422_IP_YUV_422_1P_IMG (4 << EXYNOS4_YUV_422_IP_SHIFT) 288 #define EXYNOS4_YUV_422_IP_YUV_422_2P_IMG (5 << EXYNOS4_YUV_422_IP_SHIFT) 289 #define EXYNOS4_YUV_422_IP_YUV_422_3P_IMG (6 << EXYNOS4_YUV_422_IP_SHIFT) 290 291 #define EXYNOS4_YUV_420_IP_SHIFT 15 292 #define EXYNOS4_YUV_420_IP_MASK (7 << EXYNOS4_YUV_420_IP_SHIFT) 293 #define EXYNOS4_YUV_420_IP_YUV_420_2P_IMG (4 << EXYNOS4_YUV_420_IP_SHIFT) 294 #define EXYNOS4_YUV_420_IP_YUV_420_3P_IMG (5 << EXYNOS4_YUV_420_IP_SHIFT) 295 296 #define EXYNOS4_ENC_FMT_SHIFT 24 297 #define EXYNOS4_ENC_FMT_MASK (3 << EXYNOS4_ENC_FMT_SHIFT) 298 #define EXYNOS5433_ENC_FMT_MASK (7 << EXYNOS4_ENC_FMT_SHIFT) 299 300 #define EXYNOS4_ENC_FMT_GRAY (0 << EXYNOS4_ENC_FMT_SHIFT) 301 #define EXYNOS4_ENC_FMT_YUV_444 (1 << EXYNOS4_ENC_FMT_SHIFT) 302 #define EXYNOS4_ENC_FMT_YUV_422 (2 << EXYNOS4_ENC_FMT_SHIFT) 303 #define EXYNOS4_ENC_FMT_YUV_420 (3 << EXYNOS4_ENC_FMT_SHIFT) 304 305 #define EXYNOS4_JPEG_DECODED_IMG_FMT_MASK 0x03 306 307 #define EXYNOS4_SWAP_CHROMA_CRCB (1 << 26) 308 #define EXYNOS4_SWAP_CHROMA_CBCR (0 << 26) 309 #define EXYNOS5433_SWAP_CHROMA_CRCB (1 << 27) 310 #define EXYNOS5433_SWAP_CHROMA_CBCR (0 << 27) 311 312 /* JPEG HUFF count Register bit */ 313 #define EXYNOS4_HUFF_COUNT_MASK 0xffff 314 315 /* JPEG Decoded_img_x_y_size Register bit */ 316 #define EXYNOS4_DECODED_SIZE_MASK 0x0000ffff 317 318 /* JPEG Decoded image format Register bit */ 319 #define EXYNOS4_DECODED_IMG_FMT_MASK 0x3 320 321 /* JPEG TBL SEL Register bit */ 322 #define EXYNOS4_Q_TBL_COMP(c, n) ((n) << (((c) - 1) << 1)) 323 324 #define EXYNOS4_Q_TBL_COMP1_0 EXYNOS4_Q_TBL_COMP(1, 0) 325 #define EXYNOS4_Q_TBL_COMP1_1 EXYNOS4_Q_TBL_COMP(1, 1) 326 #define EXYNOS4_Q_TBL_COMP1_2 EXYNOS4_Q_TBL_COMP(1, 2) 327 #define EXYNOS4_Q_TBL_COMP1_3 EXYNOS4_Q_TBL_COMP(1, 3) 328 329 #define EXYNOS4_Q_TBL_COMP2_0 EXYNOS4_Q_TBL_COMP(2, 0) 330 #define EXYNOS4_Q_TBL_COMP2_1 EXYNOS4_Q_TBL_COMP(2, 1) 331 #define EXYNOS4_Q_TBL_COMP2_2 EXYNOS4_Q_TBL_COMP(2, 2) 332 #define EXYNOS4_Q_TBL_COMP2_3 EXYNOS4_Q_TBL_COMP(2, 3) 333 334 #define EXYNOS4_Q_TBL_COMP3_0 EXYNOS4_Q_TBL_COMP(3, 0) 335 #define EXYNOS4_Q_TBL_COMP3_1 EXYNOS4_Q_TBL_COMP(3, 1) 336 #define EXYNOS4_Q_TBL_COMP3_2 EXYNOS4_Q_TBL_COMP(3, 2) 337 #define EXYNOS4_Q_TBL_COMP3_3 EXYNOS4_Q_TBL_COMP(3, 3) 338 339 #define EXYNOS4_HUFF_TBL_COMP(c, n) ((n) << ((((c) - 1) << 1) + 6)) 340 341 #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_0 \ 342 EXYNOS4_HUFF_TBL_COMP(1, 0) 343 #define EXYNOS4_HUFF_TBL_COMP1_AC_0_DC_1 \ 344 EXYNOS4_HUFF_TBL_COMP(1, 1) 345 #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_0 \ 346 EXYNOS4_HUFF_TBL_COMP(1, 2) 347 #define EXYNOS4_HUFF_TBL_COMP1_AC_1_DC_1 \ 348 EXYNOS4_HUFF_TBL_COMP(1, 3) 349 350 #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_0 \ 351 EXYNOS4_HUFF_TBL_COMP(2, 0) 352 #define EXYNOS4_HUFF_TBL_COMP2_AC_0_DC_1 \ 353 EXYNOS4_HUFF_TBL_COMP(2, 1) 354 #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_0 \ 355 EXYNOS4_HUFF_TBL_COMP(2, 2) 356 #define EXYNOS4_HUFF_TBL_COMP2_AC_1_DC_1 \ 357 EXYNOS4_HUFF_TBL_COMP(2, 3) 358 359 #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_0 \ 360 EXYNOS4_HUFF_TBL_COMP(3, 0) 361 #define EXYNOS4_HUFF_TBL_COMP3_AC_0_DC_1 \ 362 EXYNOS4_HUFF_TBL_COMP(3, 1) 363 #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_0 \ 364 EXYNOS4_HUFF_TBL_COMP(3, 2) 365 #define EXYNOS4_HUFF_TBL_COMP3_AC_1_DC_1 \ 366 EXYNOS4_HUFF_TBL_COMP(3, 3) 367 368 #define EXYNOS4_NF_SHIFT 16 369 #define EXYNOS4_NF_MASK 0xff 370 #define EXYNOS4_NF(x) \ 371 (((x) & EXYNOS4_NF_MASK) << EXYNOS4_NF_SHIFT) 372 373 /* JPEG quantizer table register */ 374 #define EXYNOS4_QTBL_CONTENT(n) (0x100 + (n) * 0x40) 375 376 /* JPEG DC luminance (code length) Huffman table register */ 377 #define EXYNOS4_HUFF_TBL_HDCLL 0x200 378 379 /* JPEG DC luminance (values) Huffman table register */ 380 #define EXYNOS4_HUFF_TBL_HDCLV 0x210 381 382 /* JPEG DC chrominance (code length) Huffman table register */ 383 #define EXYNOS4_HUFF_TBL_HDCCL 0x220 384 385 /* JPEG DC chrominance (values) Huffman table register */ 386 #define EXYNOS4_HUFF_TBL_HDCCV 0x230 387 388 /* JPEG AC luminance (code length) Huffman table register */ 389 #define EXYNOS4_HUFF_TBL_HACLL 0x240 390 391 /* JPEG AC luminance (values) Huffman table register */ 392 #define EXYNOS4_HUFF_TBL_HACLV 0x250 393 394 /* JPEG AC chrominance (code length) Huffman table register */ 395 #define EXYNOS4_HUFF_TBL_HACCL 0x300 396 397 /* JPEG AC chrominance (values) Huffman table register */ 398 #define EXYNOS4_HUFF_TBL_HACCV 0x310 399 400 /* Register and bit definitions for Exynos 3250 */ 401 402 /* JPEG mode register */ 403 #define EXYNOS3250_JPGMOD 0x00 404 #define EXYNOS3250_PROC_MODE_MASK (0x1 << 3) 405 #define EXYNOS3250_PROC_MODE_DECOMPR (0x1 << 3) 406 #define EXYNOS3250_PROC_MODE_COMPR (0x0 << 3) 407 #define EXYNOS3250_SUBSAMPLING_MODE_MASK (0x7 << 0) 408 #define EXYNOS3250_SUBSAMPLING_MODE_444 (0x0 << 0) 409 #define EXYNOS3250_SUBSAMPLING_MODE_422 (0x1 << 0) 410 #define EXYNOS3250_SUBSAMPLING_MODE_420 (0x2 << 0) 411 #define EXYNOS3250_SUBSAMPLING_MODE_411 (0x6 << 0) 412 #define EXYNOS3250_SUBSAMPLING_MODE_GRAY (0x3 << 0) 413 414 /* JPEG operation status register */ 415 #define EXYNOS3250_JPGOPR 0x04 416 #define EXYNOS3250_JPGOPR_MASK 0x01 417 418 /* Quantization and Huffman tables register */ 419 #define EXYNOS3250_QHTBL 0x08 420 #define EXYNOS3250_QT_NUM_SHIFT(t) ((((t) - 1) << 1) + 8) 421 #define EXYNOS3250_QT_NUM_MASK(t) (0x3 << EXYNOS3250_QT_NUM_SHIFT(t)) 422 423 /* Huffman tables */ 424 #define EXYNOS3250_HT_NUM_AC_SHIFT(t) (((t) << 1) - 1) 425 #define EXYNOS3250_HT_NUM_AC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_AC_SHIFT(t)) 426 427 #define EXYNOS3250_HT_NUM_DC_SHIFT(t) (((t) - 1) << 1) 428 #define EXYNOS3250_HT_NUM_DC_MASK(t) (0x1 << EXYNOS3250_HT_NUM_DC_SHIFT(t)) 429 430 /* JPEG restart interval register */ 431 #define EXYNOS3250_JPGDRI 0x0c 432 #define EXYNOS3250_JPGDRI_MASK 0xffff 433 434 /* JPEG vertical resolution register */ 435 #define EXYNOS3250_JPGY 0x10 436 #define EXYNOS3250_JPGY_MASK 0xffff 437 438 /* JPEG horizontal resolution register */ 439 #define EXYNOS3250_JPGX 0x14 440 #define EXYNOS3250_JPGX_MASK 0xffff 441 442 /* JPEG byte count register */ 443 #define EXYNOS3250_JPGCNT 0x18 444 #define EXYNOS3250_JPGCNT_MASK 0xffffff 445 446 /* JPEG interrupt mask register */ 447 #define EXYNOS3250_JPGINTSE 0x1c 448 #define EXYNOS3250_JPEG_DONE_EN (1 << 11) 449 #define EXYNOS3250_WDMA_DONE_EN (1 << 10) 450 #define EXYNOS3250_RDMA_DONE_EN (1 << 9) 451 #define EXYNOS3250_ENC_STREAM_INT_EN (1 << 8) 452 #define EXYNOS3250_CORE_DONE_EN (1 << 5) 453 #define EXYNOS3250_ERR_INT_EN (1 << 4) 454 #define EXYNOS3250_HEAD_INT_EN (1 << 3) 455 456 /* JPEG interrupt status register */ 457 #define EXYNOS3250_JPGINTST 0x20 458 #define EXYNOS3250_JPEG_DONE (1 << 11) 459 #define EXYNOS3250_WDMA_DONE (1 << 10) 460 #define EXYNOS3250_RDMA_DONE (1 << 9) 461 #define EXYNOS3250_ENC_STREAM_STAT (1 << 8) 462 #define EXYNOS3250_RESULT_STAT (1 << 5) 463 #define EXYNOS3250_STREAM_STAT (1 << 4) 464 #define EXYNOS3250_HEADER_STAT (1 << 3) 465 466 /* 467 * Base address of the luma component DMA buffer 468 * of the raw input or output image. 469 */ 470 #define EXYNOS3250_LUMA_BASE 0x100 471 #define EXYNOS3250_SRC_TILE_EN_MASK 0x100 472 473 /* Stride of source or destination luma raw image buffer */ 474 #define EXYNOS3250_LUMA_STRIDE 0x104 475 476 /* Horizontal/vertical offset of active region in luma raw image buffer */ 477 #define EXYNOS3250_LUMA_XY_OFFSET 0x108 478 #define EXYNOS3250_LUMA_YY_OFFSET_SHIFT 18 479 #define EXYNOS3250_LUMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YY_OFFSET_SHIFT) 480 #define EXYNOS3250_LUMA_YX_OFFSET_SHIFT 2 481 #define EXYNOS3250_LUMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_LUMA_YX_OFFSET_SHIFT) 482 483 /* 484 * Base address of the chroma(Cb) component DMA buffer 485 * of the raw input or output image. 486 */ 487 #define EXYNOS3250_CHROMA_BASE 0x10c 488 489 /* Stride of source or destination chroma(Cb) raw image buffer */ 490 #define EXYNOS3250_CHROMA_STRIDE 0x110 491 492 /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ 493 #define EXYNOS3250_CHROMA_XY_OFFSET 0x114 494 #define EXYNOS3250_CHROMA_YY_OFFSET_SHIFT 18 495 #define EXYNOS3250_CHROMA_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YY_OFFSET_SHIFT) 496 #define EXYNOS3250_CHROMA_YX_OFFSET_SHIFT 2 497 #define EXYNOS3250_CHROMA_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_YX_OFFSET_SHIFT) 498 499 /* 500 * Base address of the chroma(Cr) component DMA buffer 501 * of the raw input or output image. 502 */ 503 #define EXYNOS3250_CHROMA_CR_BASE 0x118 504 505 /* Stride of source or destination chroma(Cr) raw image buffer */ 506 #define EXYNOS3250_CHROMA_CR_STRIDE 0x11c 507 508 /* Horizontal/vertical offset of active region in chroma(Cb) raw image buffer */ 509 #define EXYNOS3250_CHROMA_CR_XY_OFFSET 0x120 510 #define EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT 18 511 #define EXYNOS3250_CHROMA_CR_YY_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YY_OFFSET_SHIFT) 512 #define EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT 2 513 #define EXYNOS3250_CHROMA_CR_YX_OFFSET_MASK (0x1fff << EXYNOS3250_CHROMA_CR_YX_OFFSET_SHIFT) 514 515 /* Raw image data r/w address register */ 516 #define EXYNOS3250_JPG_IMGADR 0x50 517 518 /* Source or destination JPEG file DMA buffer address */ 519 #define EXYNOS3250_JPG_JPGADR 0x124 520 521 /* Coefficients for RGB-to-YCbCr converter register */ 522 #define EXYNOS3250_JPG_COEF(n) (0x128 + (((n) - 1) << 2)) 523 #define EXYNOS3250_COEF_SHIFT(j) ((3 - (j)) << 3) 524 #define EXYNOS3250_COEF_MASK(j) (0xff << EXYNOS3250_COEF_SHIFT(j)) 525 526 /* Raw input format setting */ 527 #define EXYNOS3250_JPGCMOD 0x134 528 #define EXYNOS3250_SRC_TILE_EN (0x1 << 10) 529 #define EXYNOS3250_SRC_NV_MASK (0x1 << 9) 530 #define EXYNOS3250_SRC_NV12 (0x0 << 9) 531 #define EXYNOS3250_SRC_NV21 (0x1 << 9) 532 #define EXYNOS3250_SRC_BIG_ENDIAN_MASK (0x1 << 8) 533 #define EXYNOS3250_SRC_BIG_ENDIAN (0x1 << 8) 534 #define EXYNOS3250_MODE_SEL_MASK (0x7 << 5) 535 #define EXYNOS3250_MODE_SEL_420_2P (0x0 << 5) 536 #define EXYNOS3250_MODE_SEL_422_1P_LUM_CHR (0x1 << 5) 537 #define EXYNOS3250_MODE_SEL_RGB565 (0x2 << 5) 538 #define EXYNOS3250_MODE_SEL_422_1P_CHR_LUM (0x3 << 5) 539 #define EXYNOS3250_MODE_SEL_ARGB8888 (0x4 << 5) 540 #define EXYNOS3250_MODE_SEL_420_3P (0x5 << 5) 541 #define EXYNOS3250_SRC_SWAP_RGB (0x1 << 3) 542 #define EXYNOS3250_SRC_SWAP_UV (0x1 << 2) 543 #define EXYNOS3250_MODE_Y16_MASK (0x1 << 1) 544 #define EXYNOS3250_MODE_Y16 (0x1 << 1) 545 #define EXYNOS3250_HALF_EN_MASK (0x1 << 0) 546 #define EXYNOS3250_HALF_EN (0x1 << 0) 547 548 /* Power on/off and clock down control */ 549 #define EXYNOS3250_JPGCLKCON 0x138 550 #define EXYNOS3250_CLK_DOWN_READY (0x1 << 1) 551 #define EXYNOS3250_POWER_ON (0x1 << 0) 552 553 /* Start compression or decompression */ 554 #define EXYNOS3250_JSTART 0x13c 555 556 /* Restart decompression after header analysis */ 557 #define EXYNOS3250_JRSTART 0x140 558 559 /* JPEG SW reset register */ 560 #define EXYNOS3250_SW_RESET 0x144 561 562 /* JPEG timer setting register */ 563 #define EXYNOS3250_TIMER_SE 0x148 564 #define EXYNOS3250_TIMER_INT_EN_SHIFT 31 565 #define EXYNOS3250_TIMER_INT_EN (1UL << EXYNOS3250_TIMER_INT_EN_SHIFT) 566 #define EXYNOS3250_TIMER_INIT_MASK 0x7fffffff 567 568 /* JPEG timer status register */ 569 #define EXYNOS3250_TIMER_ST 0x14c 570 #define EXYNOS3250_TIMER_INT_STAT_SHIFT 31 571 #define EXYNOS3250_TIMER_INT_STAT (1UL << EXYNOS3250_TIMER_INT_STAT_SHIFT) 572 #define EXYNOS3250_TIMER_CNT_SHIFT 0 573 #define EXYNOS3250_TIMER_CNT_MASK 0x7fffffff 574 575 /* Command status register */ 576 #define EXYNOS3250_COMSTAT 0x150 577 #define EXYNOS3250_CUR_PROC_MODE (0x1 << 1) 578 #define EXYNOS3250_CUR_COM_MODE (0x1 << 0) 579 580 /* JPEG decompression output format register */ 581 #define EXYNOS3250_OUTFORM 0x154 582 #define EXYNOS3250_OUT_ALPHA_MASK (0xff << 24) 583 #define EXYNOS3250_OUT_TILE_EN (0x1 << 10) 584 #define EXYNOS3250_OUT_NV_MASK (0x1 << 9) 585 #define EXYNOS3250_OUT_NV12 (0x0 << 9) 586 #define EXYNOS3250_OUT_NV21 (0x1 << 9) 587 #define EXYNOS3250_OUT_BIG_ENDIAN_MASK (0x1 << 8) 588 #define EXYNOS3250_OUT_BIG_ENDIAN (0x1 << 8) 589 #define EXYNOS3250_OUT_SWAP_RGB (0x1 << 7) 590 #define EXYNOS3250_OUT_SWAP_UV (0x1 << 6) 591 #define EXYNOS3250_OUT_FMT_MASK (0x7 << 0) 592 #define EXYNOS3250_OUT_FMT_420_2P (0x0 << 0) 593 #define EXYNOS3250_OUT_FMT_422_1P_LUM_CHR (0x1 << 0) 594 #define EXYNOS3250_OUT_FMT_422_1P_CHR_LUM (0x3 << 0) 595 #define EXYNOS3250_OUT_FMT_420_3P (0x4 << 0) 596 #define EXYNOS3250_OUT_FMT_RGB565 (0x5 << 0) 597 #define EXYNOS3250_OUT_FMT_ARGB8888 (0x6 << 0) 598 599 /* Input JPEG stream byte size for decompression */ 600 #define EXYNOS3250_DEC_STREAM_SIZE 0x158 601 #define EXYNOS3250_DEC_STREAM_MASK 0x1fffffff 602 603 /* The upper bound of the byte size of output compressed stream */ 604 #define EXYNOS3250_ENC_STREAM_BOUND 0x15c 605 #define EXYNOS3250_ENC_STREAM_BOUND_MASK 0xffffc0 606 607 /* Scale-down ratio when decoding */ 608 #define EXYNOS3250_DEC_SCALING_RATIO 0x160 609 #define EXYNOS3250_DEC_SCALE_FACTOR_MASK 0x3 610 #define EXYNOS3250_DEC_SCALE_FACTOR_8_8 0x0 611 #define EXYNOS3250_DEC_SCALE_FACTOR_4_8 0x1 612 #define EXYNOS3250_DEC_SCALE_FACTOR_2_8 0x2 613 #define EXYNOS3250_DEC_SCALE_FACTOR_1_8 0x3 614 615 /* Error check */ 616 #define EXYNOS3250_CRC_RESULT 0x164 617 618 /* RDMA and WDMA operation status register */ 619 #define EXYNOS3250_DMA_OPER_STATUS 0x168 620 #define EXYNOS3250_WDMA_OPER_STATUS (0x1 << 1) 621 #define EXYNOS3250_RDMA_OPER_STATUS (0x1 << 0) 622 623 /* DMA issue gathering number and issue number settings */ 624 #define EXYNOS3250_DMA_ISSUE_NUM 0x16c 625 #define EXYNOS3250_WDMA_ISSUE_NUM_SHIFT 16 626 #define EXYNOS3250_WDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) 627 #define EXYNOS3250_RDMA_ISSUE_NUM_SHIFT 8 628 #define EXYNOS3250_RDMA_ISSUE_NUM_MASK (0x7 << EXYNOS3250_RDMA_ISSUE_NUM_SHIFT) 629 #define EXYNOS3250_ISSUE_GATHER_NUM_SHIFT 0 630 #define EXYNOS3250_ISSUE_GATHER_NUM_MASK (0x7 << EXYNOS3250_ISSUE_GATHER_NUM_SHIFT) 631 #define EXYNOS3250_DMA_MO_COUNT 0x7 632 633 /* Version register */ 634 #define EXYNOS3250_VERSION 0x1fc 635 636 /* RGB <-> YUV conversion coefficients */ 637 #define EXYNOS3250_JPEG_ENC_COEF1 0x01352e1e 638 #define EXYNOS3250_JPEG_ENC_COEF2 0x00b0ae83 639 #define EXYNOS3250_JPEG_ENC_COEF3 0x020cdc13 640 641 #define EXYNOS3250_JPEG_DEC_COEF1 0x04a80199 642 #define EXYNOS3250_JPEG_DEC_COEF2 0x04a9a064 643 #define EXYNOS3250_JPEG_DEC_COEF3 0x04a80102 644 645 #endif /* JPEG_REGS_H_ */ 646 647