1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 4 */ 5 6 #ifndef FIMC_LITE_REG_H_ 7 #define FIMC_LITE_REG_H_ 8 9 #include <linux/bitops.h> 10 11 #include "fimc-lite.h" 12 13 /* Camera Source size */ 14 #define FLITE_REG_CISRCSIZE 0x00 15 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14) 16 #define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14) 17 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14) 18 #define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14) 19 #define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14) 20 #define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff) 21 22 /* Global control */ 23 #define FLITE_REG_CIGCTRL 0x04 24 #define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24) 25 #define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24) 26 #define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24) 27 #define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24) 28 #define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24) 29 /* User defined formats. x = 0...15 */ 30 #define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24) 31 #define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24) 32 #define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE BIT(21) 33 #define FLITE_REG_CIGCTRL_ODMA_DISABLE BIT(20) 34 #define FLITE_REG_CIGCTRL_SWRST_REQ BIT(19) 35 #define FLITE_REG_CIGCTRL_SWRST_RDY BIT(18) 36 #define FLITE_REG_CIGCTRL_SWRST BIT(17) 37 #define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR BIT(15) 38 #define FLITE_REG_CIGCTRL_INVPOLPCLK BIT(14) 39 #define FLITE_REG_CIGCTRL_INVPOLVSYNC BIT(13) 40 #define FLITE_REG_CIGCTRL_INVPOLHREF BIT(12) 41 /* Interrupts mask bits (1 disables an interrupt) */ 42 #define FLITE_REG_CIGCTRL_IRQ_LASTEN BIT(8) 43 #define FLITE_REG_CIGCTRL_IRQ_ENDEN BIT(7) 44 #define FLITE_REG_CIGCTRL_IRQ_STARTEN BIT(6) 45 #define FLITE_REG_CIGCTRL_IRQ_OVFEN BIT(5) 46 #define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5) 47 #define FLITE_REG_CIGCTRL_SELCAM_MIPI BIT(3) 48 49 /* Image Capture Enable */ 50 #define FLITE_REG_CIIMGCPT 0x08 51 #define FLITE_REG_CIIMGCPT_IMGCPTEN BIT(31) 52 #define FLITE_REG_CIIMGCPT_CPT_FREN BIT(25) 53 #define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18) 54 #define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18) 55 56 /* Capture Sequence */ 57 #define FLITE_REG_CICPTSEQ 0x0c 58 59 /* Camera Window Offset */ 60 #define FLITE_REG_CIWDOFST 0x10 61 #define FLITE_REG_CIWDOFST_WINOFSEN BIT(31) 62 #define FLITE_REG_CIWDOFST_CLROVIY BIT(31) 63 #define FLITE_REG_CIWDOFST_CLROVFICB BIT(15) 64 #define FLITE_REG_CIWDOFST_CLROVFICR BIT(14) 65 #define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff) 66 67 /* Camera Window Offset2 */ 68 #define FLITE_REG_CIWDOFST2 0x14 69 70 /* Camera Output DMA Format */ 71 #define FLITE_REG_CIODMAFMT 0x18 72 #define FLITE_REG_CIODMAFMT_RAW_CON BIT(15) 73 #define FLITE_REG_CIODMAFMT_PACK12 BIT(14) 74 #define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4) 75 #define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4) 76 #define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4) 77 #define FLITE_REG_CIODMAFMT_CRYCBY (3 << 4) 78 #define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4) 79 80 /* Camera Output Canvas */ 81 #define FLITE_REG_CIOCAN 0x20 82 #define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff) 83 84 /* Camera Output DMA Offset */ 85 #define FLITE_REG_CIOOFF 0x24 86 #define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff) 87 88 /* Camera Output DMA Start Address */ 89 #define FLITE_REG_CIOSA 0x30 90 91 /* Camera Status */ 92 #define FLITE_REG_CISTATUS 0x40 93 #define FLITE_REG_CISTATUS_MIPI_VVALID BIT(22) 94 #define FLITE_REG_CISTATUS_MIPI_HVALID BIT(21) 95 #define FLITE_REG_CISTATUS_MIPI_DVALID BIT(20) 96 #define FLITE_REG_CISTATUS_ITU_VSYNC BIT(14) 97 #define FLITE_REG_CISTATUS_ITU_HREFF BIT(13) 98 #define FLITE_REG_CISTATUS_OVFIY BIT(10) 99 #define FLITE_REG_CISTATUS_OVFICB BIT(9) 100 #define FLITE_REG_CISTATUS_OVFICR BIT(8) 101 #define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW BIT(7) 102 #define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND BIT(6) 103 #define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART BIT(5) 104 #define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND BIT(4) 105 #define FLITE_REG_CISTATUS_IRQ_CAM BIT(0) 106 #define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4) 107 108 /* Camera Status2 */ 109 #define FLITE_REG_CISTATUS2 0x44 110 #define FLITE_REG_CISTATUS2_LASTCAPEND BIT(1) 111 #define FLITE_REG_CISTATUS2_FRMEND BIT(0) 112 113 /* Qos Threshold */ 114 #define FLITE_REG_CITHOLD 0xf0 115 #define FLITE_REG_CITHOLD_W_QOS_EN BIT(30) 116 117 /* Camera General Purpose */ 118 #define FLITE_REG_CIGENERAL 0xfc 119 /* b0: 1 - camera B, 0 - camera A */ 120 #define FLITE_REG_CIGENERAL_CAM_B BIT(0) 121 122 #define FLITE_REG_CIFCNTSEQ 0x100 123 #define FLITE_REG_CIOSAN(x) (0x200 + (4 * (x))) 124 125 /* ---------------------------------------------------------------------------- 126 * Function declarations 127 */ 128 void flite_hw_reset(struct fimc_lite *dev); 129 void flite_hw_clear_pending_irq(struct fimc_lite *dev); 130 u32 flite_hw_get_interrupt_source(struct fimc_lite *dev); 131 void flite_hw_clear_last_capture_end(struct fimc_lite *dev); 132 void flite_hw_set_interrupt_mask(struct fimc_lite *dev); 133 void flite_hw_capture_start(struct fimc_lite *dev); 134 void flite_hw_capture_stop(struct fimc_lite *dev); 135 void flite_hw_set_camera_bus(struct fimc_lite *dev, 136 struct fimc_source_info *s_info); 137 void flite_hw_set_camera_polarity(struct fimc_lite *dev, 138 struct fimc_source_info *cam); 139 void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f); 140 void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f); 141 142 void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f, 143 bool enable); 144 void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f); 145 void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on); 146 void flite_hw_dump_regs(struct fimc_lite *dev, const char *label); 147 void flite_hw_set_dma_buffer(struct fimc_lite *dev, struct flite_buffer *buf); 148 void flite_hw_mask_dma_buffer(struct fimc_lite *dev, u32 index); 149 150 static inline void flite_hw_set_dma_buf_mask(struct fimc_lite *dev, u32 mask) 151 { 152 writel(mask, dev->regs + FLITE_REG_CIFCNTSEQ); 153 } 154 155 #endif /* FIMC_LITE_REG_H */ 156