1*238c84f7SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */ 2*238c84f7SMauro Carvalho Chehab /* 3*238c84f7SMauro Carvalho Chehab * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver 4*238c84f7SMauro Carvalho Chehab * 5*238c84f7SMauro Carvalho Chehab * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6*238c84f7SMauro Carvalho Chehab * 7*238c84f7SMauro Carvalho Chehab * Authors: Younghwan Joo <yhwan.joo@samsung.com> 8*238c84f7SMauro Carvalho Chehab * Sylwester Nawrocki <s.nawrocki@samsung.com> 9*238c84f7SMauro Carvalho Chehab */ 10*238c84f7SMauro Carvalho Chehab #ifndef FIMC_IS_H_ 11*238c84f7SMauro Carvalho Chehab #define FIMC_IS_H_ 12*238c84f7SMauro Carvalho Chehab 13*238c84f7SMauro Carvalho Chehab #include <asm/barrier.h> 14*238c84f7SMauro Carvalho Chehab #include <linux/clk.h> 15*238c84f7SMauro Carvalho Chehab #include <linux/device.h> 16*238c84f7SMauro Carvalho Chehab #include <linux/kernel.h> 17*238c84f7SMauro Carvalho Chehab #include <linux/pinctrl/consumer.h> 18*238c84f7SMauro Carvalho Chehab #include <linux/platform_device.h> 19*238c84f7SMauro Carvalho Chehab #include <linux/sizes.h> 20*238c84f7SMauro Carvalho Chehab #include <linux/spinlock.h> 21*238c84f7SMauro Carvalho Chehab #include <linux/types.h> 22*238c84f7SMauro Carvalho Chehab #include <media/videobuf2-v4l2.h> 23*238c84f7SMauro Carvalho Chehab #include <media/v4l2-ctrls.h> 24*238c84f7SMauro Carvalho Chehab 25*238c84f7SMauro Carvalho Chehab #include "fimc-isp.h" 26*238c84f7SMauro Carvalho Chehab #include "fimc-is-command.h" 27*238c84f7SMauro Carvalho Chehab #include "fimc-is-sensor.h" 28*238c84f7SMauro Carvalho Chehab #include "fimc-is-param.h" 29*238c84f7SMauro Carvalho Chehab #include "fimc-is-regs.h" 30*238c84f7SMauro Carvalho Chehab 31*238c84f7SMauro Carvalho Chehab #define FIMC_IS_DRV_NAME "exynos4-fimc-is" 32*238c84f7SMauro Carvalho Chehab 33*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_FILENAME "exynos4_fimc_is_fw.bin" 34*238c84f7SMauro Carvalho Chehab #define FIMC_IS_SETFILE_6A3 "exynos4_s5k6a3_setfile.bin" 35*238c84f7SMauro Carvalho Chehab 36*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_LOAD_TIMEOUT 1000 /* ms */ 37*238c84f7SMauro Carvalho Chehab #define FIMC_IS_POWER_ON_TIMEOUT 1000 /* us */ 38*238c84f7SMauro Carvalho Chehab 39*238c84f7SMauro Carvalho Chehab #define FIMC_IS_SENSORS_NUM 2 40*238c84f7SMauro Carvalho Chehab 41*238c84f7SMauro Carvalho Chehab /* Memory definitions */ 42*238c84f7SMauro Carvalho Chehab #define FIMC_IS_CPU_MEM_SIZE (0xa00000) 43*238c84f7SMauro Carvalho Chehab #define FIMC_IS_CPU_BASE_MASK ((1 << 26) - 1) 44*238c84f7SMauro Carvalho Chehab #define FIMC_IS_REGION_SIZE 0x5000 45*238c84f7SMauro Carvalho Chehab 46*238c84f7SMauro Carvalho Chehab #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000 47*238c84f7SMauro Carvalho Chehab #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000 48*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_INFO_LEN 31 49*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_VER_LEN 7 50*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_DESC_LEN (FIMC_IS_FW_INFO_LEN + \ 51*238c84f7SMauro Carvalho Chehab FIMC_IS_FW_VER_LEN) 52*238c84f7SMauro Carvalho Chehab #define FIMC_IS_SETFILE_INFO_LEN 39 53*238c84f7SMauro Carvalho Chehab 54*238c84f7SMauro Carvalho Chehab #define FIMC_IS_EXTRA_MEM_SIZE (FIMC_IS_EXTRA_FW_SIZE + \ 55*238c84f7SMauro Carvalho Chehab FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000) 56*238c84f7SMauro Carvalho Chehab #define FIMC_IS_EXTRA_FW_SIZE 0x180000 57*238c84f7SMauro Carvalho Chehab #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000 58*238c84f7SMauro Carvalho Chehab 59*238c84f7SMauro Carvalho Chehab /* TODO: revisit */ 60*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_ADDR_MASK ((1 << 26) - 1) 61*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_SIZE_MAX (SZ_4M) 62*238c84f7SMauro Carvalho Chehab #define FIMC_IS_FW_SIZE_MIN (SZ_32K) 63*238c84f7SMauro Carvalho Chehab 64*238c84f7SMauro Carvalho Chehab #define ATCLK_MCUISP_FREQUENCY 100000000UL 65*238c84f7SMauro Carvalho Chehab #define ACLK_AXI_FREQUENCY 100000000UL 66*238c84f7SMauro Carvalho Chehab 67*238c84f7SMauro Carvalho Chehab enum { 68*238c84f7SMauro Carvalho Chehab ISS_CLK_PPMUISPX, 69*238c84f7SMauro Carvalho Chehab ISS_CLK_PPMUISPMX, 70*238c84f7SMauro Carvalho Chehab ISS_CLK_LITE0, 71*238c84f7SMauro Carvalho Chehab ISS_CLK_LITE1, 72*238c84f7SMauro Carvalho Chehab ISS_CLK_MPLL, 73*238c84f7SMauro Carvalho Chehab ISS_CLK_ISP, 74*238c84f7SMauro Carvalho Chehab ISS_CLK_DRC, 75*238c84f7SMauro Carvalho Chehab ISS_CLK_FD, 76*238c84f7SMauro Carvalho Chehab ISS_CLK_MCUISP, 77*238c84f7SMauro Carvalho Chehab ISS_CLK_GICISP, 78*238c84f7SMauro Carvalho Chehab ISS_CLK_PWM_ISP, 79*238c84f7SMauro Carvalho Chehab ISS_CLK_MCUCTL_ISP, 80*238c84f7SMauro Carvalho Chehab ISS_CLK_UART, 81*238c84f7SMauro Carvalho Chehab ISS_GATE_CLKS_MAX, 82*238c84f7SMauro Carvalho Chehab ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX, 83*238c84f7SMauro Carvalho Chehab ISS_CLK_ISP_DIV1, 84*238c84f7SMauro Carvalho Chehab ISS_CLK_MCUISP_DIV0, 85*238c84f7SMauro Carvalho Chehab ISS_CLK_MCUISP_DIV1, 86*238c84f7SMauro Carvalho Chehab ISS_CLK_ACLK200, 87*238c84f7SMauro Carvalho Chehab ISS_CLK_ACLK200_DIV, 88*238c84f7SMauro Carvalho Chehab ISS_CLK_ACLK400MCUISP, 89*238c84f7SMauro Carvalho Chehab ISS_CLK_ACLK400MCUISP_DIV, 90*238c84f7SMauro Carvalho Chehab ISS_CLKS_MAX 91*238c84f7SMauro Carvalho Chehab }; 92*238c84f7SMauro Carvalho Chehab 93*238c84f7SMauro Carvalho Chehab /* The driver's internal state flags */ 94*238c84f7SMauro Carvalho Chehab enum { 95*238c84f7SMauro Carvalho Chehab IS_ST_IDLE, 96*238c84f7SMauro Carvalho Chehab IS_ST_PWR_ON, 97*238c84f7SMauro Carvalho Chehab IS_ST_A5_PWR_ON, 98*238c84f7SMauro Carvalho Chehab IS_ST_FW_LOADED, 99*238c84f7SMauro Carvalho Chehab IS_ST_OPEN_SENSOR, 100*238c84f7SMauro Carvalho Chehab IS_ST_SETFILE_LOADED, 101*238c84f7SMauro Carvalho Chehab IS_ST_INIT_DONE, 102*238c84f7SMauro Carvalho Chehab IS_ST_STREAM_ON, 103*238c84f7SMauro Carvalho Chehab IS_ST_STREAM_OFF, 104*238c84f7SMauro Carvalho Chehab IS_ST_CHANGE_MODE, 105*238c84f7SMauro Carvalho Chehab IS_ST_BLOCK_CMD_CLEARED, 106*238c84f7SMauro Carvalho Chehab IS_ST_SET_ZOOM, 107*238c84f7SMauro Carvalho Chehab IS_ST_PWR_SUBIP_ON, 108*238c84f7SMauro Carvalho Chehab IS_ST_END, 109*238c84f7SMauro Carvalho Chehab }; 110*238c84f7SMauro Carvalho Chehab 111*238c84f7SMauro Carvalho Chehab enum af_state { 112*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_IDLE = 0, 113*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_SETCONFIG = 1, 114*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_RUNNING = 2, 115*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_LOCK = 3, 116*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_ABORT = 4, 117*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_FAILED = 5, 118*238c84f7SMauro Carvalho Chehab }; 119*238c84f7SMauro Carvalho Chehab 120*238c84f7SMauro Carvalho Chehab enum af_lock_state { 121*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_UNLOCKED = 0, 122*238c84f7SMauro Carvalho Chehab FIMC_IS_AF_LOCKED = 2 123*238c84f7SMauro Carvalho Chehab }; 124*238c84f7SMauro Carvalho Chehab 125*238c84f7SMauro Carvalho Chehab enum ae_lock_state { 126*238c84f7SMauro Carvalho Chehab FIMC_IS_AE_UNLOCKED = 0, 127*238c84f7SMauro Carvalho Chehab FIMC_IS_AE_LOCKED = 1 128*238c84f7SMauro Carvalho Chehab }; 129*238c84f7SMauro Carvalho Chehab 130*238c84f7SMauro Carvalho Chehab enum awb_lock_state { 131*238c84f7SMauro Carvalho Chehab FIMC_IS_AWB_UNLOCKED = 0, 132*238c84f7SMauro Carvalho Chehab FIMC_IS_AWB_LOCKED = 1 133*238c84f7SMauro Carvalho Chehab }; 134*238c84f7SMauro Carvalho Chehab 135*238c84f7SMauro Carvalho Chehab enum { 136*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_CMD, 137*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_WIN_POS_X, 138*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_WIN_POS_Y, 139*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_WIN_WIDTH, 140*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_WIN_HEIGHT, 141*238c84f7SMauro Carvalho Chehab IS_METERING_CONFIG_MAX 142*238c84f7SMauro Carvalho Chehab }; 143*238c84f7SMauro Carvalho Chehab 144*238c84f7SMauro Carvalho Chehab struct is_setfile { 145*238c84f7SMauro Carvalho Chehab const struct firmware *info; 146*238c84f7SMauro Carvalho Chehab int state; 147*238c84f7SMauro Carvalho Chehab u32 sub_index; 148*238c84f7SMauro Carvalho Chehab u32 base; 149*238c84f7SMauro Carvalho Chehab size_t size; 150*238c84f7SMauro Carvalho Chehab }; 151*238c84f7SMauro Carvalho Chehab 152*238c84f7SMauro Carvalho Chehab struct is_fd_result_header { 153*238c84f7SMauro Carvalho Chehab u32 offset; 154*238c84f7SMauro Carvalho Chehab u32 count; 155*238c84f7SMauro Carvalho Chehab u32 index; 156*238c84f7SMauro Carvalho Chehab u32 curr_index; 157*238c84f7SMauro Carvalho Chehab u32 width; 158*238c84f7SMauro Carvalho Chehab u32 height; 159*238c84f7SMauro Carvalho Chehab }; 160*238c84f7SMauro Carvalho Chehab 161*238c84f7SMauro Carvalho Chehab struct is_af_info { 162*238c84f7SMauro Carvalho Chehab u16 mode; 163*238c84f7SMauro Carvalho Chehab u32 af_state; 164*238c84f7SMauro Carvalho Chehab u32 af_lock_state; 165*238c84f7SMauro Carvalho Chehab u32 ae_lock_state; 166*238c84f7SMauro Carvalho Chehab u32 awb_lock_state; 167*238c84f7SMauro Carvalho Chehab u16 pos_x; 168*238c84f7SMauro Carvalho Chehab u16 pos_y; 169*238c84f7SMauro Carvalho Chehab u16 prev_pos_x; 170*238c84f7SMauro Carvalho Chehab u16 prev_pos_y; 171*238c84f7SMauro Carvalho Chehab u16 use_af; 172*238c84f7SMauro Carvalho Chehab }; 173*238c84f7SMauro Carvalho Chehab 174*238c84f7SMauro Carvalho Chehab struct fimc_is_firmware { 175*238c84f7SMauro Carvalho Chehab const struct firmware *f_w; 176*238c84f7SMauro Carvalho Chehab 177*238c84f7SMauro Carvalho Chehab dma_addr_t addr; 178*238c84f7SMauro Carvalho Chehab void *vaddr; 179*238c84f7SMauro Carvalho Chehab unsigned int size; 180*238c84f7SMauro Carvalho Chehab 181*238c84f7SMauro Carvalho Chehab char info[FIMC_IS_FW_INFO_LEN + 1]; 182*238c84f7SMauro Carvalho Chehab char version[FIMC_IS_FW_VER_LEN + 1]; 183*238c84f7SMauro Carvalho Chehab char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1]; 184*238c84f7SMauro Carvalho Chehab u8 state; 185*238c84f7SMauro Carvalho Chehab }; 186*238c84f7SMauro Carvalho Chehab 187*238c84f7SMauro Carvalho Chehab struct fimc_is_memory { 188*238c84f7SMauro Carvalho Chehab /* DMA base address */ 189*238c84f7SMauro Carvalho Chehab dma_addr_t addr; 190*238c84f7SMauro Carvalho Chehab /* virtual base address */ 191*238c84f7SMauro Carvalho Chehab void *vaddr; 192*238c84f7SMauro Carvalho Chehab /* total length */ 193*238c84f7SMauro Carvalho Chehab unsigned int size; 194*238c84f7SMauro Carvalho Chehab }; 195*238c84f7SMauro Carvalho Chehab 196*238c84f7SMauro Carvalho Chehab #define FIMC_IS_I2H_MAX_ARGS 12 197*238c84f7SMauro Carvalho Chehab 198*238c84f7SMauro Carvalho Chehab struct i2h_cmd { 199*238c84f7SMauro Carvalho Chehab u32 cmd; 200*238c84f7SMauro Carvalho Chehab u32 sensor_id; 201*238c84f7SMauro Carvalho Chehab u16 num_args; 202*238c84f7SMauro Carvalho Chehab u32 args[FIMC_IS_I2H_MAX_ARGS]; 203*238c84f7SMauro Carvalho Chehab }; 204*238c84f7SMauro Carvalho Chehab 205*238c84f7SMauro Carvalho Chehab struct h2i_cmd { 206*238c84f7SMauro Carvalho Chehab u16 cmd_type; 207*238c84f7SMauro Carvalho Chehab u32 entry_id; 208*238c84f7SMauro Carvalho Chehab }; 209*238c84f7SMauro Carvalho Chehab 210*238c84f7SMauro Carvalho Chehab #define FIMC_IS_DEBUG_MSG 0x3f 211*238c84f7SMauro Carvalho Chehab #define FIMC_IS_DEBUG_LEVEL 3 212*238c84f7SMauro Carvalho Chehab 213*238c84f7SMauro Carvalho Chehab struct fimc_is_setfile { 214*238c84f7SMauro Carvalho Chehab const struct firmware *info; 215*238c84f7SMauro Carvalho Chehab unsigned int state; 216*238c84f7SMauro Carvalho Chehab unsigned int size; 217*238c84f7SMauro Carvalho Chehab u32 sub_index; 218*238c84f7SMauro Carvalho Chehab u32 base; 219*238c84f7SMauro Carvalho Chehab }; 220*238c84f7SMauro Carvalho Chehab 221*238c84f7SMauro Carvalho Chehab struct chain_config { 222*238c84f7SMauro Carvalho Chehab struct global_param global; 223*238c84f7SMauro Carvalho Chehab struct sensor_param sensor; 224*238c84f7SMauro Carvalho Chehab struct isp_param isp; 225*238c84f7SMauro Carvalho Chehab struct drc_param drc; 226*238c84f7SMauro Carvalho Chehab struct fd_param fd; 227*238c84f7SMauro Carvalho Chehab 228*238c84f7SMauro Carvalho Chehab unsigned long p_region_index[2]; 229*238c84f7SMauro Carvalho Chehab }; 230*238c84f7SMauro Carvalho Chehab 231*238c84f7SMauro Carvalho Chehab /** 232*238c84f7SMauro Carvalho Chehab * struct fimc_is - fimc-is data structure 233*238c84f7SMauro Carvalho Chehab * @pdev: pointer to FIMC-IS platform device 234*238c84f7SMauro Carvalho Chehab * @pctrl: pointer to pinctrl structure for this device 235*238c84f7SMauro Carvalho Chehab * @v4l2_dev: pointer to the top level v4l2_device 236*238c84f7SMauro Carvalho Chehab * @fw: data structure describing the FIMC-IS firmware binary 237*238c84f7SMauro Carvalho Chehab * @memory: memory region assigned for the FIMC-IS (firmware) 238*238c84f7SMauro Carvalho Chehab * @isp: the ISP block data structure 239*238c84f7SMauro Carvalho Chehab * @sensor: fimc-is sensor subdevice array 240*238c84f7SMauro Carvalho Chehab * @setfile: descriptor of the imaging pipeline calibration data 241*238c84f7SMauro Carvalho Chehab * @ctrl_handler: the v4l2 controls handler 242*238c84f7SMauro Carvalho Chehab * @lock: mutex serializing video device and the subdev operations 243*238c84f7SMauro Carvalho Chehab * @slock: spinlock protecting this data structure and the hw registers 244*238c84f7SMauro Carvalho Chehab * @clocks: FIMC-LITE gate clock 245*238c84f7SMauro Carvalho Chehab * @regs: MCUCTL mmapped registers region 246*238c84f7SMauro Carvalho Chehab * @pmu_regs: PMU ISP mmapped registers region 247*238c84f7SMauro Carvalho Chehab * @irq: FIMC-IS interrupt 248*238c84f7SMauro Carvalho Chehab * @irq_queue: interrupt handling waitqueue 249*238c84f7SMauro Carvalho Chehab * @lpm: low power mode flag 250*238c84f7SMauro Carvalho Chehab * @state: internal driver's state flags 251*238c84f7SMauro Carvalho Chehab * @sensor_index: image sensor index for the firmware 252*238c84f7SMauro Carvalho Chehab * @i2h_cmd: FIMC-IS to the host (CPU) mailbox command data structure 253*238c84f7SMauro Carvalho Chehab * @h2i_cmd: the host (CPU) to FIMC-IS mailbox command data structure 254*238c84f7SMauro Carvalho Chehab * @fd_header: the face detection result data structure 255*238c84f7SMauro Carvalho Chehab * @config: shared HW pipeline configuration data 256*238c84f7SMauro Carvalho Chehab * @config_index: index to the @config entry currently in use 257*238c84f7SMauro Carvalho Chehab * @is_p_region: pointer to the shared parameter memory region 258*238c84f7SMauro Carvalho Chehab * @is_dma_p_region: DMA address of the shared parameter memory region 259*238c84f7SMauro Carvalho Chehab * @is_shared_region: pointer to the IS shared region data structure 260*238c84f7SMauro Carvalho Chehab * @af: auto focus data 261*238c84f7SMauro Carvalho Chehab * @debugfs_entry: debugfs entry for the firmware log 262*238c84f7SMauro Carvalho Chehab */ 263*238c84f7SMauro Carvalho Chehab struct fimc_is { 264*238c84f7SMauro Carvalho Chehab struct platform_device *pdev; 265*238c84f7SMauro Carvalho Chehab struct pinctrl *pctrl; 266*238c84f7SMauro Carvalho Chehab struct v4l2_device *v4l2_dev; 267*238c84f7SMauro Carvalho Chehab 268*238c84f7SMauro Carvalho Chehab struct fimc_is_firmware fw; 269*238c84f7SMauro Carvalho Chehab struct fimc_is_memory memory; 270*238c84f7SMauro Carvalho Chehab 271*238c84f7SMauro Carvalho Chehab struct fimc_isp isp; 272*238c84f7SMauro Carvalho Chehab struct fimc_is_sensor sensor[FIMC_IS_SENSORS_NUM]; 273*238c84f7SMauro Carvalho Chehab struct fimc_is_setfile setfile; 274*238c84f7SMauro Carvalho Chehab 275*238c84f7SMauro Carvalho Chehab struct v4l2_ctrl_handler ctrl_handler; 276*238c84f7SMauro Carvalho Chehab 277*238c84f7SMauro Carvalho Chehab struct mutex lock; 278*238c84f7SMauro Carvalho Chehab spinlock_t slock; 279*238c84f7SMauro Carvalho Chehab 280*238c84f7SMauro Carvalho Chehab struct clk *clocks[ISS_CLKS_MAX]; 281*238c84f7SMauro Carvalho Chehab void __iomem *regs; 282*238c84f7SMauro Carvalho Chehab void __iomem *pmu_regs; 283*238c84f7SMauro Carvalho Chehab int irq; 284*238c84f7SMauro Carvalho Chehab wait_queue_head_t irq_queue; 285*238c84f7SMauro Carvalho Chehab u8 lpm; 286*238c84f7SMauro Carvalho Chehab 287*238c84f7SMauro Carvalho Chehab unsigned long state; 288*238c84f7SMauro Carvalho Chehab unsigned int sensor_index; 289*238c84f7SMauro Carvalho Chehab 290*238c84f7SMauro Carvalho Chehab struct i2h_cmd i2h_cmd; 291*238c84f7SMauro Carvalho Chehab struct h2i_cmd h2i_cmd; 292*238c84f7SMauro Carvalho Chehab struct is_fd_result_header fd_header; 293*238c84f7SMauro Carvalho Chehab 294*238c84f7SMauro Carvalho Chehab struct chain_config config[IS_SC_MAX]; 295*238c84f7SMauro Carvalho Chehab unsigned config_index; 296*238c84f7SMauro Carvalho Chehab 297*238c84f7SMauro Carvalho Chehab struct is_region *is_p_region; 298*238c84f7SMauro Carvalho Chehab dma_addr_t is_dma_p_region; 299*238c84f7SMauro Carvalho Chehab struct is_share_region *is_shared_region; 300*238c84f7SMauro Carvalho Chehab struct is_af_info af; 301*238c84f7SMauro Carvalho Chehab 302*238c84f7SMauro Carvalho Chehab struct dentry *debugfs_entry; 303*238c84f7SMauro Carvalho Chehab }; 304*238c84f7SMauro Carvalho Chehab 305*238c84f7SMauro Carvalho Chehab static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp) 306*238c84f7SMauro Carvalho Chehab { 307*238c84f7SMauro Carvalho Chehab return container_of(isp, struct fimc_is, isp); 308*238c84f7SMauro Carvalho Chehab } 309*238c84f7SMauro Carvalho Chehab 310*238c84f7SMauro Carvalho Chehab static inline struct chain_config *__get_curr_is_config(struct fimc_is *is) 311*238c84f7SMauro Carvalho Chehab { 312*238c84f7SMauro Carvalho Chehab return &is->config[is->config_index]; 313*238c84f7SMauro Carvalho Chehab } 314*238c84f7SMauro Carvalho Chehab 315*238c84f7SMauro Carvalho Chehab static inline void fimc_is_mem_barrier(void) 316*238c84f7SMauro Carvalho Chehab { 317*238c84f7SMauro Carvalho Chehab mb(); 318*238c84f7SMauro Carvalho Chehab } 319*238c84f7SMauro Carvalho Chehab 320*238c84f7SMauro Carvalho Chehab static inline void fimc_is_set_param_bit(struct fimc_is *is, int num) 321*238c84f7SMauro Carvalho Chehab { 322*238c84f7SMauro Carvalho Chehab struct chain_config *cfg = &is->config[is->config_index]; 323*238c84f7SMauro Carvalho Chehab 324*238c84f7SMauro Carvalho Chehab set_bit(num, &cfg->p_region_index[0]); 325*238c84f7SMauro Carvalho Chehab } 326*238c84f7SMauro Carvalho Chehab 327*238c84f7SMauro Carvalho Chehab static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd) 328*238c84f7SMauro Carvalho Chehab { 329*238c84f7SMauro Carvalho Chehab is->is_p_region->parameter.isp.control.cmd = cmd; 330*238c84f7SMauro Carvalho Chehab } 331*238c84f7SMauro Carvalho Chehab 332*238c84f7SMauro Carvalho Chehab static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset) 333*238c84f7SMauro Carvalho Chehab { 334*238c84f7SMauro Carvalho Chehab writel(v, is->regs + offset); 335*238c84f7SMauro Carvalho Chehab } 336*238c84f7SMauro Carvalho Chehab 337*238c84f7SMauro Carvalho Chehab static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset) 338*238c84f7SMauro Carvalho Chehab { 339*238c84f7SMauro Carvalho Chehab return readl(is->regs + offset); 340*238c84f7SMauro Carvalho Chehab } 341*238c84f7SMauro Carvalho Chehab 342*238c84f7SMauro Carvalho Chehab static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset) 343*238c84f7SMauro Carvalho Chehab { 344*238c84f7SMauro Carvalho Chehab writel(v, is->pmu_regs + offset); 345*238c84f7SMauro Carvalho Chehab } 346*238c84f7SMauro Carvalho Chehab 347*238c84f7SMauro Carvalho Chehab static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset) 348*238c84f7SMauro Carvalho Chehab { 349*238c84f7SMauro Carvalho Chehab return readl(is->pmu_regs + offset); 350*238c84f7SMauro Carvalho Chehab } 351*238c84f7SMauro Carvalho Chehab 352*238c84f7SMauro Carvalho Chehab int fimc_is_wait_event(struct fimc_is *is, unsigned long bit, 353*238c84f7SMauro Carvalho Chehab unsigned int state, unsigned int timeout); 354*238c84f7SMauro Carvalho Chehab int fimc_is_cpu_set_power(struct fimc_is *is, int on); 355*238c84f7SMauro Carvalho Chehab int fimc_is_start_firmware(struct fimc_is *is); 356*238c84f7SMauro Carvalho Chehab int fimc_is_hw_initialize(struct fimc_is *is); 357*238c84f7SMauro Carvalho Chehab void fimc_is_log_dump(const char *level, const void *buf, size_t len); 358*238c84f7SMauro Carvalho Chehab 359*238c84f7SMauro Carvalho Chehab #endif /* FIMC_IS_H_ */ 360