1*238c84f7SMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0-only 2*238c84f7SMauro Carvalho Chehab /* 3*238c84f7SMauro Carvalho Chehab * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver 4*238c84f7SMauro Carvalho Chehab * 5*238c84f7SMauro Carvalho Chehab * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd. 6*238c84f7SMauro Carvalho Chehab * 7*238c84f7SMauro Carvalho Chehab * Authors: Younghwan Joo <yhwan.joo@samsung.com> 8*238c84f7SMauro Carvalho Chehab * Sylwester Nawrocki <s.nawrocki@samsung.com> 9*238c84f7SMauro Carvalho Chehab */ 10*238c84f7SMauro Carvalho Chehab #include <linux/delay.h> 11*238c84f7SMauro Carvalho Chehab 12*238c84f7SMauro Carvalho Chehab #include "fimc-is.h" 13*238c84f7SMauro Carvalho Chehab #include "fimc-is-command.h" 14*238c84f7SMauro Carvalho Chehab #include "fimc-is-regs.h" 15*238c84f7SMauro Carvalho Chehab #include "fimc-is-sensor.h" 16*238c84f7SMauro Carvalho Chehab 17*238c84f7SMauro Carvalho Chehab void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr) 18*238c84f7SMauro Carvalho Chehab { 19*238c84f7SMauro Carvalho Chehab mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1); 20*238c84f7SMauro Carvalho Chehab } 21*238c84f7SMauro Carvalho Chehab 22*238c84f7SMauro Carvalho Chehab void fimc_is_fw_clear_irq2(struct fimc_is *is) 23*238c84f7SMauro Carvalho Chehab { 24*238c84f7SMauro Carvalho Chehab u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2); 25*238c84f7SMauro Carvalho Chehab mcuctl_write(cfg, is, MCUCTL_REG_INTCR2); 26*238c84f7SMauro Carvalho Chehab } 27*238c84f7SMauro Carvalho Chehab 28*238c84f7SMauro Carvalho Chehab void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is) 29*238c84f7SMauro Carvalho Chehab { 30*238c84f7SMauro Carvalho Chehab mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0); 31*238c84f7SMauro Carvalho Chehab } 32*238c84f7SMauro Carvalho Chehab 33*238c84f7SMauro Carvalho Chehab int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is) 34*238c84f7SMauro Carvalho Chehab { 35*238c84f7SMauro Carvalho Chehab unsigned int timeout = 2000; 36*238c84f7SMauro Carvalho Chehab u32 cfg, status; 37*238c84f7SMauro Carvalho Chehab 38*238c84f7SMauro Carvalho Chehab do { 39*238c84f7SMauro Carvalho Chehab cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0); 40*238c84f7SMauro Carvalho Chehab status = INTMSR0_GET_INTMSD(0, cfg); 41*238c84f7SMauro Carvalho Chehab 42*238c84f7SMauro Carvalho Chehab if (--timeout == 0) { 43*238c84f7SMauro Carvalho Chehab dev_warn(&is->pdev->dev, "%s timeout\n", 44*238c84f7SMauro Carvalho Chehab __func__); 45*238c84f7SMauro Carvalho Chehab return -ETIMEDOUT; 46*238c84f7SMauro Carvalho Chehab } 47*238c84f7SMauro Carvalho Chehab udelay(1); 48*238c84f7SMauro Carvalho Chehab } while (status != 0); 49*238c84f7SMauro Carvalho Chehab 50*238c84f7SMauro Carvalho Chehab return 0; 51*238c84f7SMauro Carvalho Chehab } 52*238c84f7SMauro Carvalho Chehab 53*238c84f7SMauro Carvalho Chehab int fimc_is_hw_set_param(struct fimc_is *is) 54*238c84f7SMauro Carvalho Chehab { 55*238c84f7SMauro Carvalho Chehab struct chain_config *config = &is->config[is->config_index]; 56*238c84f7SMauro Carvalho Chehab unsigned int param_count = __get_pending_param_count(is); 57*238c84f7SMauro Carvalho Chehab 58*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 59*238c84f7SMauro Carvalho Chehab 60*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0)); 61*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 62*238c84f7SMauro Carvalho Chehab mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2)); 63*238c84f7SMauro Carvalho Chehab 64*238c84f7SMauro Carvalho Chehab mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3)); 65*238c84f7SMauro Carvalho Chehab mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4)); 66*238c84f7SMauro Carvalho Chehab mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5)); 67*238c84f7SMauro Carvalho Chehab 68*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 69*238c84f7SMauro Carvalho Chehab return 0; 70*238c84f7SMauro Carvalho Chehab } 71*238c84f7SMauro Carvalho Chehab 72*238c84f7SMauro Carvalho Chehab static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is) 73*238c84f7SMauro Carvalho Chehab { 74*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 75*238c84f7SMauro Carvalho Chehab 76*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0)); 77*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 78*238c84f7SMauro Carvalho Chehab mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2)); 79*238c84f7SMauro Carvalho Chehab 80*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 81*238c84f7SMauro Carvalho Chehab return 0; 82*238c84f7SMauro Carvalho Chehab } 83*238c84f7SMauro Carvalho Chehab 84*238c84f7SMauro Carvalho Chehab #define FIMC_IS_MAX_PARAMS 4 85*238c84f7SMauro Carvalho Chehab 86*238c84f7SMauro Carvalho Chehab int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args) 87*238c84f7SMauro Carvalho Chehab { 88*238c84f7SMauro Carvalho Chehab int i; 89*238c84f7SMauro Carvalho Chehab 90*238c84f7SMauro Carvalho Chehab if (num_args > FIMC_IS_MAX_PARAMS) 91*238c84f7SMauro Carvalho Chehab return -EINVAL; 92*238c84f7SMauro Carvalho Chehab 93*238c84f7SMauro Carvalho Chehab is->i2h_cmd.num_args = num_args; 94*238c84f7SMauro Carvalho Chehab 95*238c84f7SMauro Carvalho Chehab for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) { 96*238c84f7SMauro Carvalho Chehab if (i < num_args) 97*238c84f7SMauro Carvalho Chehab is->i2h_cmd.args[i] = mcuctl_read(is, 98*238c84f7SMauro Carvalho Chehab MCUCTL_REG_ISSR(12 + i)); 99*238c84f7SMauro Carvalho Chehab else 100*238c84f7SMauro Carvalho Chehab is->i2h_cmd.args[i] = 0; 101*238c84f7SMauro Carvalho Chehab } 102*238c84f7SMauro Carvalho Chehab return 0; 103*238c84f7SMauro Carvalho Chehab } 104*238c84f7SMauro Carvalho Chehab 105*238c84f7SMauro Carvalho Chehab void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask) 106*238c84f7SMauro Carvalho Chehab { 107*238c84f7SMauro Carvalho Chehab if (hweight32(mask) == 1) { 108*238c84f7SMauro Carvalho Chehab dev_err(&is->pdev->dev, "%s(): not enough buffers (mask %#x)\n", 109*238c84f7SMauro Carvalho Chehab __func__, mask); 110*238c84f7SMauro Carvalho Chehab return; 111*238c84f7SMauro Carvalho Chehab } 112*238c84f7SMauro Carvalho Chehab 113*238c84f7SMauro Carvalho Chehab if (mcuctl_read(is, MCUCTL_REG_ISSR(23)) != 0) 114*238c84f7SMauro Carvalho Chehab dev_dbg(&is->pdev->dev, "non-zero DMA buffer mask\n"); 115*238c84f7SMauro Carvalho Chehab 116*238c84f7SMauro Carvalho Chehab mcuctl_write(mask, is, MCUCTL_REG_ISSR(23)); 117*238c84f7SMauro Carvalho Chehab } 118*238c84f7SMauro Carvalho Chehab 119*238c84f7SMauro Carvalho Chehab void fimc_is_hw_set_sensor_num(struct fimc_is *is) 120*238c84f7SMauro Carvalho Chehab { 121*238c84f7SMauro Carvalho Chehab pr_debug("setting sensor index to: %d\n", is->sensor_index); 122*238c84f7SMauro Carvalho Chehab 123*238c84f7SMauro Carvalho Chehab mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0)); 124*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 125*238c84f7SMauro Carvalho Chehab mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2)); 126*238c84f7SMauro Carvalho Chehab mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3)); 127*238c84f7SMauro Carvalho Chehab } 128*238c84f7SMauro Carvalho Chehab 129*238c84f7SMauro Carvalho Chehab void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index) 130*238c84f7SMauro Carvalho Chehab { 131*238c84f7SMauro Carvalho Chehab if (is->sensor_index != index) 132*238c84f7SMauro Carvalho Chehab return; 133*238c84f7SMauro Carvalho Chehab 134*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 135*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0)); 136*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 137*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2)); 138*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 139*238c84f7SMauro Carvalho Chehab } 140*238c84f7SMauro Carvalho Chehab 141*238c84f7SMauro Carvalho Chehab void fimc_is_hw_get_setfile_addr(struct fimc_is *is) 142*238c84f7SMauro Carvalho Chehab { 143*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 144*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0)); 145*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 146*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 147*238c84f7SMauro Carvalho Chehab } 148*238c84f7SMauro Carvalho Chehab 149*238c84f7SMauro Carvalho Chehab void fimc_is_hw_load_setfile(struct fimc_is *is) 150*238c84f7SMauro Carvalho Chehab { 151*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 152*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0)); 153*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 154*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 155*238c84f7SMauro Carvalho Chehab } 156*238c84f7SMauro Carvalho Chehab 157*238c84f7SMauro Carvalho Chehab int fimc_is_hw_change_mode(struct fimc_is *is) 158*238c84f7SMauro Carvalho Chehab { 159*238c84f7SMauro Carvalho Chehab static const u8 cmd[] = { 160*238c84f7SMauro Carvalho Chehab HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO, 161*238c84f7SMauro Carvalho Chehab HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO, 162*238c84f7SMauro Carvalho Chehab }; 163*238c84f7SMauro Carvalho Chehab 164*238c84f7SMauro Carvalho Chehab if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd))) 165*238c84f7SMauro Carvalho Chehab return -EINVAL; 166*238c84f7SMauro Carvalho Chehab 167*238c84f7SMauro Carvalho Chehab mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0)); 168*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 169*238c84f7SMauro Carvalho Chehab mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2)); 170*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 171*238c84f7SMauro Carvalho Chehab return 0; 172*238c84f7SMauro Carvalho Chehab } 173*238c84f7SMauro Carvalho Chehab 174*238c84f7SMauro Carvalho Chehab void fimc_is_hw_stream_on(struct fimc_is *is) 175*238c84f7SMauro Carvalho Chehab { 176*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 177*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0)); 178*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 179*238c84f7SMauro Carvalho Chehab mcuctl_write(0, is, MCUCTL_REG_ISSR(2)); 180*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 181*238c84f7SMauro Carvalho Chehab } 182*238c84f7SMauro Carvalho Chehab 183*238c84f7SMauro Carvalho Chehab void fimc_is_hw_stream_off(struct fimc_is *is) 184*238c84f7SMauro Carvalho Chehab { 185*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 186*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0)); 187*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 188*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 189*238c84f7SMauro Carvalho Chehab } 190*238c84f7SMauro Carvalho Chehab 191*238c84f7SMauro Carvalho Chehab void fimc_is_hw_subip_power_off(struct fimc_is *is) 192*238c84f7SMauro Carvalho Chehab { 193*238c84f7SMauro Carvalho Chehab fimc_is_hw_wait_intmsr0_intmsd0(is); 194*238c84f7SMauro Carvalho Chehab mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0)); 195*238c84f7SMauro Carvalho Chehab mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); 196*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_intgr0_gd0(is); 197*238c84f7SMauro Carvalho Chehab } 198*238c84f7SMauro Carvalho Chehab 199*238c84f7SMauro Carvalho Chehab int fimc_is_itf_s_param(struct fimc_is *is, bool update) 200*238c84f7SMauro Carvalho Chehab { 201*238c84f7SMauro Carvalho Chehab int ret; 202*238c84f7SMauro Carvalho Chehab 203*238c84f7SMauro Carvalho Chehab if (update) 204*238c84f7SMauro Carvalho Chehab __is_hw_update_params(is); 205*238c84f7SMauro Carvalho Chehab 206*238c84f7SMauro Carvalho Chehab fimc_is_mem_barrier(); 207*238c84f7SMauro Carvalho Chehab 208*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); 209*238c84f7SMauro Carvalho Chehab fimc_is_hw_set_param(is); 210*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1, 211*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT); 212*238c84f7SMauro Carvalho Chehab if (ret < 0) 213*238c84f7SMauro Carvalho Chehab dev_err(&is->pdev->dev, "%s() timeout\n", __func__); 214*238c84f7SMauro Carvalho Chehab 215*238c84f7SMauro Carvalho Chehab return ret; 216*238c84f7SMauro Carvalho Chehab } 217*238c84f7SMauro Carvalho Chehab 218*238c84f7SMauro Carvalho Chehab int fimc_is_itf_mode_change(struct fimc_is *is) 219*238c84f7SMauro Carvalho Chehab { 220*238c84f7SMauro Carvalho Chehab int ret; 221*238c84f7SMauro Carvalho Chehab 222*238c84f7SMauro Carvalho Chehab clear_bit(IS_ST_CHANGE_MODE, &is->state); 223*238c84f7SMauro Carvalho Chehab fimc_is_hw_change_mode(is); 224*238c84f7SMauro Carvalho Chehab ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1, 225*238c84f7SMauro Carvalho Chehab FIMC_IS_CONFIG_TIMEOUT); 226*238c84f7SMauro Carvalho Chehab if (ret < 0) 227*238c84f7SMauro Carvalho Chehab dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n", 228*238c84f7SMauro Carvalho Chehab __func__, is->config_index); 229*238c84f7SMauro Carvalho Chehab return ret; 230*238c84f7SMauro Carvalho Chehab } 231