1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - CSI-2 Receiver 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * Copyright (C) 2022 Ideas on Board 7 * 8 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 9 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/lockdep.h> 15 #include <linux/phy/phy.h> 16 #include <linux/phy/phy-mipi-dphy.h> 17 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-fwnode.h> 20 21 #include "rkisp1-common.h" 22 #include "rkisp1-csi.h" 23 24 #define RKISP1_CSI_DEV_NAME RKISP1_DRIVER_NAME "_csi" 25 26 #define RKISP1_CSI_DEF_FMT MEDIA_BUS_FMT_SRGGB10_1X10 27 28 static inline struct rkisp1_csi *to_rkisp1_csi(struct v4l2_subdev *sd) 29 { 30 return container_of(sd, struct rkisp1_csi, sd); 31 } 32 33 int rkisp1_csi_link_sensor(struct rkisp1_device *rkisp1, struct v4l2_subdev *sd, 34 struct rkisp1_sensor_async *s_asd, 35 unsigned int source_pad) 36 { 37 struct rkisp1_csi *csi = &rkisp1->csi; 38 int ret; 39 40 s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler, 41 V4L2_CID_PIXEL_RATE); 42 if (!s_asd->pixel_rate_ctrl) { 43 dev_err(rkisp1->dev, "No pixel rate control in subdev %s\n", 44 sd->name); 45 return -EINVAL; 46 } 47 48 /* Create the link from the sensor to the CSI receiver. */ 49 ret = media_create_pad_link(&sd->entity, source_pad, 50 &csi->sd.entity, RKISP1_CSI_PAD_SINK, 51 !s_asd->index ? MEDIA_LNK_FL_ENABLED : 0); 52 if (ret) { 53 dev_err(csi->rkisp1->dev, "failed to link src pad of %s\n", 54 sd->name); 55 return ret; 56 } 57 58 return 0; 59 } 60 61 static int rkisp1_csi_config(struct rkisp1_csi *csi, 62 const struct rkisp1_sensor_async *sensor, 63 const struct rkisp1_mbus_info *format) 64 { 65 struct rkisp1_device *rkisp1 = csi->rkisp1; 66 unsigned int lanes = sensor->lanes; 67 u32 mipi_ctrl; 68 69 if (lanes < 1 || lanes > 4) 70 return -EINVAL; 71 72 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | 73 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | 74 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | 75 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA; 76 77 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, mipi_ctrl); 78 79 /* V12 could also use a newer csi2-host, but we don't want that yet */ 80 if (rkisp1->info->isp_ver == RKISP1_V12) 81 rkisp1_write(rkisp1, RKISP1_CIF_ISP_CSI0_CTRL0, 0); 82 83 /* Configure Data Type and Virtual Channel */ 84 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL, 85 RKISP1_CIF_MIPI_DATA_SEL_DT(format->mipi_dt) | 86 RKISP1_CIF_MIPI_DATA_SEL_VC(0)); 87 88 /* Clear MIPI interrupts */ 89 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 90 91 /* 92 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for 93 * isp bus may be dead when switch isp. 94 */ 95 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 96 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI | 97 RKISP1_CIF_MIPI_ERR_DPHY | 98 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | 99 RKISP1_CIF_MIPI_ADD_DATA_OVFLW); 100 101 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n" 102 " MIPI_IMG_DATA_SEL 0x%08x\n" 103 " MIPI_STATUS 0x%08x\n" 104 " MIPI_IMSC 0x%08x\n", 105 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL), 106 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL), 107 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS), 108 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC)); 109 110 return 0; 111 } 112 113 static void rkisp1_csi_enable(struct rkisp1_csi *csi) 114 { 115 struct rkisp1_device *rkisp1 = csi->rkisp1; 116 u32 val; 117 118 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 119 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 120 val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA); 121 } 122 123 static void rkisp1_csi_disable(struct rkisp1_csi *csi) 124 { 125 struct rkisp1_device *rkisp1 = csi->rkisp1; 126 u32 val; 127 128 /* Mask and clear interrupts. */ 129 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0); 130 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 131 132 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 133 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 134 val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA)); 135 } 136 137 static int rkisp1_csi_start(struct rkisp1_csi *csi, 138 const struct rkisp1_sensor_async *sensor, 139 const struct rkisp1_mbus_info *format) 140 { 141 struct rkisp1_device *rkisp1 = csi->rkisp1; 142 union phy_configure_opts opts; 143 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 144 s64 pixel_clock; 145 int ret; 146 147 ret = rkisp1_csi_config(csi, sensor, format); 148 if (ret) 149 return ret; 150 151 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl); 152 if (!pixel_clock) { 153 dev_err(rkisp1->dev, "Invalid pixel rate value\n"); 154 return -EINVAL; 155 } 156 157 phy_mipi_dphy_get_default_config(pixel_clock, format->bus_width, 158 sensor->lanes, cfg); 159 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); 160 phy_configure(csi->dphy, &opts); 161 phy_power_on(csi->dphy); 162 163 rkisp1_csi_enable(csi); 164 165 /* 166 * CIF spec says to wait for sufficient time after enabling 167 * the MIPI interface and before starting the sensor output. 168 */ 169 usleep_range(1000, 1200); 170 171 return 0; 172 } 173 174 static void rkisp1_csi_stop(struct rkisp1_csi *csi) 175 { 176 rkisp1_csi_disable(csi); 177 178 phy_power_off(csi->dphy); 179 } 180 181 irqreturn_t rkisp1_csi_isr(int irq, void *ctx) 182 { 183 struct device *dev = ctx; 184 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 185 u32 val, status; 186 187 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS); 188 if (!status) 189 return IRQ_NONE; 190 191 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, status); 192 193 /* 194 * Disable DPHY errctrl interrupt, because this dphy 195 * erctrl signal is asserted until the next changes 196 * of line state. This time is may be too long and cpu 197 * is hold in this interrupt. 198 */ 199 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) { 200 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 201 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 202 val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f)); 203 rkisp1->csi.is_dphy_errctrl_disabled = true; 204 } 205 206 /* 207 * Enable DPHY errctrl interrupt again, if mipi have receive 208 * the whole frame without any error. 209 */ 210 if (status == RKISP1_CIF_MIPI_FRAME_END) { 211 /* 212 * Enable DPHY errctrl interrupt again, if mipi have receive 213 * the whole frame without any error. 214 */ 215 if (rkisp1->csi.is_dphy_errctrl_disabled) { 216 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 217 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f); 218 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, val); 219 rkisp1->csi.is_dphy_errctrl_disabled = false; 220 } 221 } else { 222 rkisp1->debug.mipi_error++; 223 } 224 225 return IRQ_HANDLED; 226 } 227 228 /* ---------------------------------------------------------------------------- 229 * Subdev pad operations 230 */ 231 232 static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd, 233 struct v4l2_subdev_state *sd_state, 234 struct v4l2_subdev_mbus_code_enum *code) 235 { 236 unsigned int i; 237 int pos = 0; 238 239 if (code->pad == RKISP1_CSI_PAD_SRC) { 240 const struct v4l2_mbus_framefmt *sink_fmt; 241 242 if (code->index) 243 return -EINVAL; 244 245 sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, 246 RKISP1_CSI_PAD_SINK); 247 code->code = sink_fmt->code; 248 249 return 0; 250 } 251 252 for (i = 0; ; i++) { 253 const struct rkisp1_mbus_info *fmt = 254 rkisp1_mbus_info_get_by_index(i); 255 256 if (!fmt) 257 return -EINVAL; 258 259 if (!(fmt->direction & RKISP1_ISP_SD_SINK)) 260 continue; 261 262 if (code->index == pos) { 263 code->code = fmt->mbus_code; 264 return 0; 265 } 266 267 pos++; 268 } 269 270 return -EINVAL; 271 } 272 273 static int rkisp1_csi_init_config(struct v4l2_subdev *sd, 274 struct v4l2_subdev_state *sd_state) 275 { 276 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 277 278 sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, 279 RKISP1_CSI_PAD_SINK); 280 src_fmt = v4l2_subdev_get_pad_format(sd, sd_state, 281 RKISP1_CSI_PAD_SRC); 282 283 sink_fmt->width = RKISP1_DEFAULT_WIDTH; 284 sink_fmt->height = RKISP1_DEFAULT_HEIGHT; 285 sink_fmt->field = V4L2_FIELD_NONE; 286 sink_fmt->code = RKISP1_CSI_DEF_FMT; 287 288 *src_fmt = *sink_fmt; 289 290 return 0; 291 } 292 293 static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd, 294 struct v4l2_subdev_state *sd_state, 295 struct v4l2_subdev_format *fmt) 296 { 297 const struct rkisp1_mbus_info *mbus_info; 298 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 299 300 /* The format on the source pad always matches the sink pad. */ 301 if (fmt->pad == RKISP1_CSI_PAD_SRC) 302 return v4l2_subdev_get_fmt(sd, sd_state, fmt); 303 304 sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SINK); 305 306 sink_fmt->code = fmt->format.code; 307 308 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 309 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) { 310 sink_fmt->code = RKISP1_CSI_DEF_FMT; 311 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 312 } 313 314 sink_fmt->width = clamp_t(u32, fmt->format.width, 315 RKISP1_ISP_MIN_WIDTH, 316 RKISP1_ISP_MAX_WIDTH); 317 sink_fmt->height = clamp_t(u32, fmt->format.height, 318 RKISP1_ISP_MIN_HEIGHT, 319 RKISP1_ISP_MAX_HEIGHT); 320 321 fmt->format = *sink_fmt; 322 323 /* Propagate the format to the source pad. */ 324 src_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SRC); 325 *src_fmt = *sink_fmt; 326 327 return 0; 328 } 329 330 /* ---------------------------------------------------------------------------- 331 * Subdev video operations 332 */ 333 334 static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable) 335 { 336 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 337 struct rkisp1_device *rkisp1 = csi->rkisp1; 338 const struct v4l2_mbus_framefmt *sink_fmt; 339 const struct rkisp1_mbus_info *format; 340 struct rkisp1_sensor_async *source_asd; 341 struct v4l2_async_connection *asc; 342 struct v4l2_subdev_state *sd_state; 343 struct media_pad *source_pad; 344 struct v4l2_subdev *source; 345 int ret; 346 347 if (!enable) { 348 v4l2_subdev_call(csi->source, video, s_stream, false); 349 350 rkisp1_csi_stop(csi); 351 352 return 0; 353 } 354 355 source_pad = media_entity_remote_source_pad_unique(&sd->entity); 356 if (IS_ERR(source_pad)) { 357 dev_dbg(rkisp1->dev, "Failed to get source for CSI: %ld\n", 358 PTR_ERR(source_pad)); 359 return -EPIPE; 360 } 361 362 source = media_entity_to_v4l2_subdev(source_pad->entity); 363 if (!source) { 364 /* This should really not happen, so is not worth a message. */ 365 return -EPIPE; 366 } 367 368 asc = v4l2_async_connection_unique(source); 369 if (!asc) 370 return -EPIPE; 371 372 source_asd = container_of(asc, struct rkisp1_sensor_async, asd); 373 if (source_asd->mbus_type != V4L2_MBUS_CSI2_DPHY) 374 return -EINVAL; 375 376 sd_state = v4l2_subdev_lock_and_get_active_state(sd); 377 sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, RKISP1_CSI_PAD_SINK); 378 format = rkisp1_mbus_info_get_by_code(sink_fmt->code); 379 v4l2_subdev_unlock_state(sd_state); 380 381 ret = rkisp1_csi_start(csi, source_asd, format); 382 if (ret) 383 return ret; 384 385 ret = v4l2_subdev_call(source, video, s_stream, true); 386 if (ret) { 387 rkisp1_csi_stop(csi); 388 return ret; 389 } 390 391 csi->source = source; 392 393 return 0; 394 } 395 396 /* ---------------------------------------------------------------------------- 397 * Registration 398 */ 399 400 static const struct media_entity_operations rkisp1_csi_media_ops = { 401 .link_validate = v4l2_subdev_link_validate, 402 }; 403 404 static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = { 405 .s_stream = rkisp1_csi_s_stream, 406 }; 407 408 static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = { 409 .enum_mbus_code = rkisp1_csi_enum_mbus_code, 410 .init_cfg = rkisp1_csi_init_config, 411 .get_fmt = v4l2_subdev_get_fmt, 412 .set_fmt = rkisp1_csi_set_fmt, 413 }; 414 415 static const struct v4l2_subdev_ops rkisp1_csi_ops = { 416 .video = &rkisp1_csi_video_ops, 417 .pad = &rkisp1_csi_pad_ops, 418 }; 419 420 int rkisp1_csi_register(struct rkisp1_device *rkisp1) 421 { 422 struct rkisp1_csi *csi = &rkisp1->csi; 423 struct media_pad *pads; 424 struct v4l2_subdev *sd; 425 int ret; 426 427 csi->rkisp1 = rkisp1; 428 429 sd = &csi->sd; 430 v4l2_subdev_init(sd, &rkisp1_csi_ops); 431 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 432 sd->entity.ops = &rkisp1_csi_media_ops; 433 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 434 sd->owner = THIS_MODULE; 435 strscpy(sd->name, RKISP1_CSI_DEV_NAME, sizeof(sd->name)); 436 437 pads = csi->pads; 438 pads[RKISP1_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK | 439 MEDIA_PAD_FL_MUST_CONNECT; 440 pads[RKISP1_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE | 441 MEDIA_PAD_FL_MUST_CONNECT; 442 443 ret = media_entity_pads_init(&sd->entity, RKISP1_CSI_PAD_NUM, pads); 444 if (ret) 445 goto err_entity_cleanup; 446 447 ret = v4l2_subdev_init_finalize(sd); 448 if (ret) 449 goto err_entity_cleanup; 450 451 ret = v4l2_device_register_subdev(&csi->rkisp1->v4l2_dev, sd); 452 if (ret) { 453 dev_err(sd->dev, "Failed to register csi receiver subdev\n"); 454 goto err_subdev_cleanup; 455 } 456 457 return 0; 458 459 err_subdev_cleanup: 460 v4l2_subdev_cleanup(sd); 461 err_entity_cleanup: 462 media_entity_cleanup(&sd->entity); 463 csi->rkisp1 = NULL; 464 return ret; 465 } 466 467 void rkisp1_csi_unregister(struct rkisp1_device *rkisp1) 468 { 469 struct rkisp1_csi *csi = &rkisp1->csi; 470 471 if (!csi->rkisp1) 472 return; 473 474 v4l2_device_unregister_subdev(&csi->sd); 475 v4l2_subdev_cleanup(&csi->sd); 476 media_entity_cleanup(&csi->sd.entity); 477 } 478 479 int rkisp1_csi_init(struct rkisp1_device *rkisp1) 480 { 481 struct rkisp1_csi *csi = &rkisp1->csi; 482 483 csi->rkisp1 = rkisp1; 484 485 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); 486 if (IS_ERR(csi->dphy)) 487 return dev_err_probe(rkisp1->dev, PTR_ERR(csi->dphy), 488 "Couldn't get the MIPI D-PHY\n"); 489 490 phy_init(csi->dphy); 491 492 return 0; 493 } 494 495 void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1) 496 { 497 struct rkisp1_csi *csi = &rkisp1->csi; 498 499 phy_exit(csi->dphy); 500 } 501