1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - V4l capture device 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/pm_runtime.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-event.h> 15 #include <media/v4l2-fh.h> 16 #include <media/v4l2-ioctl.h> 17 #include <media/v4l2-mc.h> 18 #include <media/v4l2-subdev.h> 19 #include <media/videobuf2-dma-contig.h> 20 21 #include "rkisp1-common.h" 22 23 /* 24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath. 25 * 26 * differences between selfpath and mainpath 27 * available mp sink input: isp 28 * available sp sink input : isp, dma(TODO) 29 * available mp sink pad fmts: yuv422, raw 30 * available sp sink pad fmts: yuv422, yuv420...... 31 * available mp source fmts: yuv, raw, jpeg(TODO) 32 * available sp source fmts: yuv, rgb 33 */ 34 35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath" 36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath" 37 38 #define RKISP1_MIN_BUFFERS_NEEDED 3 39 40 enum rkisp1_plane { 41 RKISP1_PLANE_Y = 0, 42 RKISP1_PLANE_CB = 1, 43 RKISP1_PLANE_CR = 2 44 }; 45 46 /* 47 * @fourcc: pixel format 48 * @fmt_type: helper filed for pixel format 49 * @uv_swap: if cb cr swapped, for yuv 50 * @yc_swap: if y and cb/cr swapped, for yuv 51 * @byte_swap: if byte pairs are swapped, for raw 52 * @write_format: defines how YCbCr self picture data is written to memory 53 * @output_format: defines the output format (RKISP1_CIF_MI_INIT_MP_OUTPUT_* for 54 * the main path and RKISP1_MI_CTRL_SP_OUTPUT_* for the self path) 55 * @mbus: the mbus code on the src resizer pad that matches the pixel format 56 */ 57 struct rkisp1_capture_fmt_cfg { 58 u32 fourcc; 59 u32 uv_swap : 1; 60 u32 yc_swap : 1; 61 u32 byte_swap : 1; 62 u32 write_format; 63 u32 output_format; 64 u32 mbus; 65 }; 66 67 struct rkisp1_capture_ops { 68 void (*config)(struct rkisp1_capture *cap); 69 void (*stop)(struct rkisp1_capture *cap); 70 void (*enable)(struct rkisp1_capture *cap); 71 void (*disable)(struct rkisp1_capture *cap); 72 void (*set_data_path)(struct rkisp1_capture *cap); 73 bool (*is_stopped)(struct rkisp1_capture *cap); 74 }; 75 76 struct rkisp1_capture_config { 77 const struct rkisp1_capture_fmt_cfg *fmts; 78 int fmt_size; 79 struct { 80 u32 y_size_init; 81 u32 cb_size_init; 82 u32 cr_size_init; 83 u32 y_base_ad_init; 84 u32 cb_base_ad_init; 85 u32 cr_base_ad_init; 86 u32 y_offs_cnt_init; 87 u32 cb_offs_cnt_init; 88 u32 cr_offs_cnt_init; 89 } mi; 90 }; 91 92 /* 93 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus' 94 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 95 */ 96 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { 97 /* yuv422 */ 98 { 99 .fourcc = V4L2_PIX_FMT_YUYV, 100 .uv_swap = 0, 101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 102 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 103 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 104 }, { 105 .fourcc = V4L2_PIX_FMT_UYVY, 106 .uv_swap = 0, 107 .yc_swap = 1, 108 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 109 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 110 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 111 }, { 112 .fourcc = V4L2_PIX_FMT_YUV422P, 113 .uv_swap = 0, 114 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 115 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 116 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 117 }, { 118 .fourcc = V4L2_PIX_FMT_NV16, 119 .uv_swap = 0, 120 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 121 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 122 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 123 }, { 124 .fourcc = V4L2_PIX_FMT_NV61, 125 .uv_swap = 1, 126 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 127 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 128 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 129 }, { 130 .fourcc = V4L2_PIX_FMT_NV16M, 131 .uv_swap = 0, 132 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 133 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 134 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 135 }, { 136 .fourcc = V4L2_PIX_FMT_NV61M, 137 .uv_swap = 1, 138 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 139 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 140 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 141 }, { 142 .fourcc = V4L2_PIX_FMT_YVU422M, 143 .uv_swap = 1, 144 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 145 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV422, 146 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 147 }, 148 /* yuv400 */ 149 { 150 .fourcc = V4L2_PIX_FMT_GREY, 151 .uv_swap = 0, 152 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 153 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV400, 154 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 155 }, 156 /* yuv420 */ 157 { 158 .fourcc = V4L2_PIX_FMT_NV21, 159 .uv_swap = 1, 160 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 161 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 162 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 163 }, { 164 .fourcc = V4L2_PIX_FMT_NV12, 165 .uv_swap = 0, 166 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 167 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 168 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 169 }, { 170 .fourcc = V4L2_PIX_FMT_NV21M, 171 .uv_swap = 1, 172 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 173 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 174 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 175 }, { 176 .fourcc = V4L2_PIX_FMT_NV12M, 177 .uv_swap = 0, 178 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 179 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 180 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 181 }, { 182 .fourcc = V4L2_PIX_FMT_YUV420, 183 .uv_swap = 0, 184 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 185 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 186 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 187 }, { 188 .fourcc = V4L2_PIX_FMT_YVU420, 189 .uv_swap = 1, 190 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 191 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_YUV420, 192 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 193 }, 194 /* raw */ 195 { 196 .fourcc = V4L2_PIX_FMT_SRGGB8, 197 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 198 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, 199 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, 200 }, { 201 .fourcc = V4L2_PIX_FMT_SGRBG8, 202 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 203 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, 204 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, 205 }, { 206 .fourcc = V4L2_PIX_FMT_SGBRG8, 207 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 208 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, 209 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, 210 }, { 211 .fourcc = V4L2_PIX_FMT_SBGGR8, 212 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 213 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW8, 214 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, 215 }, { 216 .fourcc = V4L2_PIX_FMT_SRGGB10, 217 .byte_swap = 1, 218 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 219 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, 220 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, 221 }, { 222 .fourcc = V4L2_PIX_FMT_SGRBG10, 223 .byte_swap = 1, 224 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 225 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, 226 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, 227 }, { 228 .fourcc = V4L2_PIX_FMT_SGBRG10, 229 .byte_swap = 1, 230 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 231 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, 232 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, 233 }, { 234 .fourcc = V4L2_PIX_FMT_SBGGR10, 235 .byte_swap = 1, 236 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 237 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW10, 238 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, 239 }, { 240 .fourcc = V4L2_PIX_FMT_SRGGB12, 241 .byte_swap = 1, 242 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 243 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, 244 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, 245 }, { 246 .fourcc = V4L2_PIX_FMT_SGRBG12, 247 .byte_swap = 1, 248 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 249 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, 250 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, 251 }, { 252 .fourcc = V4L2_PIX_FMT_SGBRG12, 253 .byte_swap = 1, 254 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 255 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, 256 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, 257 }, { 258 .fourcc = V4L2_PIX_FMT_SBGGR12, 259 .byte_swap = 1, 260 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 261 .output_format = RKISP1_CIF_MI_INIT_MP_OUTPUT_RAW12, 262 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, 263 }, 264 }; 265 266 /* 267 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus' 268 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 269 */ 270 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = { 271 /* yuv422 */ 272 { 273 .fourcc = V4L2_PIX_FMT_YUYV, 274 .uv_swap = 0, 275 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 276 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 277 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 278 }, { 279 .fourcc = V4L2_PIX_FMT_UYVY, 280 .uv_swap = 0, 281 .yc_swap = 1, 282 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 283 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 284 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 285 }, { 286 .fourcc = V4L2_PIX_FMT_YUV422P, 287 .uv_swap = 0, 288 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 289 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 290 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 291 }, { 292 .fourcc = V4L2_PIX_FMT_NV16, 293 .uv_swap = 0, 294 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 295 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 296 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 297 }, { 298 .fourcc = V4L2_PIX_FMT_NV61, 299 .uv_swap = 1, 300 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 301 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 302 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 303 }, { 304 .fourcc = V4L2_PIX_FMT_NV16M, 305 .uv_swap = 0, 306 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 307 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 308 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 309 }, { 310 .fourcc = V4L2_PIX_FMT_NV61M, 311 .uv_swap = 1, 312 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 313 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 314 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 315 }, { 316 .fourcc = V4L2_PIX_FMT_YVU422M, 317 .uv_swap = 1, 318 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 319 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 320 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 321 }, 322 /* yuv400 */ 323 { 324 .fourcc = V4L2_PIX_FMT_GREY, 325 .uv_swap = 0, 326 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 327 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 328 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 329 }, 330 /* rgb */ 331 { 332 .fourcc = V4L2_PIX_FMT_XBGR32, 333 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 334 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888, 335 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 336 }, { 337 .fourcc = V4L2_PIX_FMT_RGB565, 338 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 339 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565, 340 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 341 }, 342 /* yuv420 */ 343 { 344 .fourcc = V4L2_PIX_FMT_NV21, 345 .uv_swap = 1, 346 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 347 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 348 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 349 }, { 350 .fourcc = V4L2_PIX_FMT_NV12, 351 .uv_swap = 0, 352 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 353 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 354 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 355 }, { 356 .fourcc = V4L2_PIX_FMT_NV21M, 357 .uv_swap = 1, 358 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 359 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 360 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 361 }, { 362 .fourcc = V4L2_PIX_FMT_NV12M, 363 .uv_swap = 0, 364 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 365 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 366 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 367 }, { 368 .fourcc = V4L2_PIX_FMT_YUV420, 369 .uv_swap = 0, 370 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 371 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 372 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 373 }, { 374 .fourcc = V4L2_PIX_FMT_YVU420, 375 .uv_swap = 1, 376 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 377 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 378 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 379 }, 380 }; 381 382 static const struct rkisp1_capture_config rkisp1_capture_config_mp = { 383 .fmts = rkisp1_mp_fmts, 384 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts), 385 .mi = { 386 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT, 387 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT, 388 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT, 389 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT, 390 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT, 391 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT, 392 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT, 393 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT, 394 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT, 395 }, 396 }; 397 398 static const struct rkisp1_capture_config rkisp1_capture_config_sp = { 399 .fmts = rkisp1_sp_fmts, 400 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts), 401 .mi = { 402 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT, 403 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT, 404 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT, 405 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT, 406 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT, 407 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT, 408 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT, 409 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT, 410 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT, 411 }, 412 }; 413 414 static inline struct rkisp1_vdev_node * 415 rkisp1_vdev_to_node(struct video_device *vdev) 416 { 417 return container_of(vdev, struct rkisp1_vdev_node, vdev); 418 } 419 420 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap, 421 struct v4l2_subdev_mbus_code_enum *code) 422 { 423 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts; 424 /* 425 * initialize curr_mbus to non existing mbus code 0 to ensure it is 426 * different from fmts[0].mbus 427 */ 428 u32 curr_mbus = 0; 429 int i, n = 0; 430 431 for (i = 0; i < cap->config->fmt_size; i++) { 432 if (fmts[i].mbus == curr_mbus) 433 continue; 434 435 curr_mbus = fmts[i].mbus; 436 if (n++ == code->index) { 437 code->code = curr_mbus; 438 return 0; 439 } 440 } 441 return -EINVAL; 442 } 443 444 /* ---------------------------------------------------------------------------- 445 * Stream operations for self-picture path (sp) and main-picture path (mp) 446 */ 447 448 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap) 449 { 450 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 451 452 mi_ctrl &= ~GENMASK(17, 16); 453 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64; 454 455 mi_ctrl &= ~GENMASK(19, 18); 456 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64; 457 458 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN | 459 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN; 460 461 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 462 } 463 464 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm, 465 unsigned int component) 466 { 467 /* 468 * If packed format, then plane_fmt[0].sizeimage is the sum of all 469 * components, so we need to calculate just the size of Y component. 470 * See rkisp1_fill_pixfmt(). 471 */ 472 if (!component && pixm->num_planes == 1) 473 return pixm->plane_fmt[0].bytesperline * pixm->height; 474 return pixm->plane_fmt[component].sizeimage; 475 } 476 477 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap) 478 { 479 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC); 480 481 mi_imsc |= RKISP1_CIF_MI_FRAME(cap); 482 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_IMSC, mi_imsc); 483 } 484 485 static void rkisp1_mp_config(struct rkisp1_capture *cap) 486 { 487 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 488 struct rkisp1_device *rkisp1 = cap->rkisp1; 489 u32 reg; 490 491 rkisp1_write(rkisp1, cap->config->mi.y_size_init, 492 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y)); 493 rkisp1_write(rkisp1, cap->config->mi.cb_size_init, 494 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB)); 495 rkisp1_write(rkisp1, cap->config->mi.cr_size_init, 496 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 497 498 if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) { 499 rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_LLENGTH, cap->stride); 500 rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_WIDTH, pixm->width); 501 rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_HEIGHT, pixm->height); 502 rkisp1_write(rkisp1, RKISP1_CIF_MI_MP_Y_PIC_SIZE, 503 cap->stride * pixm->height); 504 } 505 506 rkisp1_irq_frame_end_enable(cap); 507 508 /* set uv swapping for semiplanar formats */ 509 if (cap->pix.info->comp_planes == 2) { 510 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 511 if (cap->pix.cfg->uv_swap) 512 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 513 else 514 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 515 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg); 516 } 517 518 /* 519 * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for 520 * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY. 521 * YVYU and VYUY cannot be supported with this method. 522 */ 523 if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) { 524 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT); 525 if (cap->pix.cfg->yc_swap || cap->pix.cfg->byte_swap) 526 reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES; 527 else 528 reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_BYTE_SWAP_BYTES; 529 530 reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_MP_LSB_ALIGNMENT; 531 rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg); 532 533 rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, 534 cap->pix.cfg->output_format); 535 } 536 537 rkisp1_mi_config_ctrl(cap); 538 539 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 540 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK; 541 reg |= cap->pix.cfg->write_format; 542 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg); 543 544 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 545 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE; 546 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, reg); 547 } 548 549 static void rkisp1_sp_config(struct rkisp1_capture *cap) 550 { 551 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 552 struct rkisp1_device *rkisp1 = cap->rkisp1; 553 u32 mi_ctrl, reg; 554 555 rkisp1_write(rkisp1, cap->config->mi.y_size_init, 556 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y)); 557 rkisp1_write(rkisp1, cap->config->mi.cb_size_init, 558 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB)); 559 rkisp1_write(rkisp1, cap->config->mi.cr_size_init, 560 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 561 562 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_LLENGTH, cap->stride); 563 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_WIDTH, pixm->width); 564 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT, pixm->height); 565 rkisp1_write(rkisp1, RKISP1_CIF_MI_SP_Y_PIC_SIZE, 566 cap->stride * pixm->height); 567 568 rkisp1_irq_frame_end_enable(cap); 569 570 /* set uv swapping for semiplanar formats */ 571 if (cap->pix.info->comp_planes == 2) { 572 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 573 if (cap->pix.cfg->uv_swap) 574 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 575 else 576 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 577 rkisp1_write(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL, reg); 578 } 579 580 /* 581 * U/V swapping with the MI_XTD_FORMAT_CTRL register only works for 582 * NV12/NV21 and NV16/NV61, so instead use byte swap to support UYVY. 583 * YVYU and VYUY cannot be supported with this method. 584 */ 585 if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) { 586 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT); 587 if (cap->pix.cfg->yc_swap) 588 reg |= RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES; 589 else 590 reg &= ~RKISP1_CIF_OUTPUT_ALIGN_FORMAT_SP_BYTE_SWAP_BYTES; 591 rkisp1_write(rkisp1, RKISP1_CIF_MI_OUTPUT_ALIGN_FORMAT, reg); 592 } 593 594 rkisp1_mi_config_ctrl(cap); 595 596 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 597 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK; 598 mi_ctrl |= cap->pix.cfg->write_format | 599 RKISP1_MI_CTRL_SP_INPUT_YUV422 | 600 cap->pix.cfg->output_format | 601 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; 602 rkisp1_write(rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 603 } 604 605 static void rkisp1_mp_disable(struct rkisp1_capture *cap) 606 { 607 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 608 609 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE | 610 RKISP1_CIF_MI_CTRL_RAW_ENABLE); 611 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 612 } 613 614 static void rkisp1_sp_disable(struct rkisp1_capture *cap) 615 { 616 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 617 618 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE; 619 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 620 } 621 622 static void rkisp1_mp_enable(struct rkisp1_capture *cap) 623 { 624 u32 mi_ctrl; 625 626 rkisp1_mp_disable(cap); 627 628 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 629 if (v4l2_is_format_bayer(cap->pix.info)) 630 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE; 631 /* YUV */ 632 else 633 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE; 634 635 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 636 } 637 638 static void rkisp1_sp_enable(struct rkisp1_capture *cap) 639 { 640 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 641 642 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE; 643 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_CTRL, mi_ctrl); 644 } 645 646 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap) 647 { 648 if (!cap->is_streaming) 649 return; 650 rkisp1_write(cap->rkisp1, RKISP1_CIF_MI_ICR, RKISP1_CIF_MI_FRAME(cap)); 651 cap->ops->disable(cap); 652 } 653 654 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap) 655 { 656 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED | 657 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED; 658 659 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en); 660 } 661 662 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap) 663 { 664 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & 665 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED); 666 } 667 668 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap) 669 { 670 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 671 672 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP | 673 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI; 674 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl); 675 } 676 677 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap) 678 { 679 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 680 681 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP; 682 rkisp1_write(cap->rkisp1, RKISP1_CIF_VI_DPCL, dpcl); 683 } 684 685 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = { 686 .config = rkisp1_mp_config, 687 .enable = rkisp1_mp_enable, 688 .disable = rkisp1_mp_disable, 689 .stop = rkisp1_mp_sp_stop, 690 .set_data_path = rkisp1_mp_set_data_path, 691 .is_stopped = rkisp1_mp_is_stopped, 692 }; 693 694 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = { 695 .config = rkisp1_sp_config, 696 .enable = rkisp1_sp_enable, 697 .disable = rkisp1_sp_disable, 698 .stop = rkisp1_mp_sp_stop, 699 .set_data_path = rkisp1_sp_set_data_path, 700 .is_stopped = rkisp1_sp_is_stopped, 701 }; 702 703 /* ---------------------------------------------------------------------------- 704 * Frame buffer operations 705 */ 706 707 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap) 708 { 709 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 710 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy; 711 712 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 713 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 714 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 715 716 /* The driver never access vaddr, no mapping is required */ 717 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev, 718 dummy_buf->size, 719 &dummy_buf->dma_addr, 720 GFP_KERNEL, 721 DMA_ATTR_NO_KERNEL_MAPPING); 722 if (!dummy_buf->vaddr) 723 return -ENOMEM; 724 725 return 0; 726 } 727 728 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap) 729 { 730 dma_free_attrs(cap->rkisp1->dev, 731 cap->buf.dummy.size, cap->buf.dummy.vaddr, 732 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING); 733 } 734 735 static void rkisp1_set_next_buf(struct rkisp1_capture *cap) 736 { 737 u8 shift = rkisp1_has_feature(cap->rkisp1, DMA_34BIT) ? 2 : 0; 738 739 cap->buf.curr = cap->buf.next; 740 cap->buf.next = NULL; 741 742 if (!list_empty(&cap->buf.queue)) { 743 dma_addr_t *buff_addr; 744 745 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue); 746 list_del(&cap->buf.next->queue); 747 748 buff_addr = cap->buf.next->buff_addr; 749 750 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init, 751 buff_addr[RKISP1_PLANE_Y] >> shift); 752 /* 753 * In order to support grey format we capture 754 * YUV422 planar format from the camera and 755 * set the U and V planes to the dummy buffer 756 */ 757 if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) { 758 rkisp1_write(cap->rkisp1, 759 cap->config->mi.cb_base_ad_init, 760 cap->buf.dummy.dma_addr >> shift); 761 rkisp1_write(cap->rkisp1, 762 cap->config->mi.cr_base_ad_init, 763 cap->buf.dummy.dma_addr >> shift); 764 } else { 765 rkisp1_write(cap->rkisp1, 766 cap->config->mi.cb_base_ad_init, 767 buff_addr[RKISP1_PLANE_CB] >> shift); 768 rkisp1_write(cap->rkisp1, 769 cap->config->mi.cr_base_ad_init, 770 buff_addr[RKISP1_PLANE_CR] >> shift); 771 } 772 } else { 773 /* 774 * Use the dummy space allocated by dma_alloc_coherent to 775 * throw data if there is no available buffer. 776 */ 777 rkisp1_write(cap->rkisp1, cap->config->mi.y_base_ad_init, 778 cap->buf.dummy.dma_addr >> shift); 779 rkisp1_write(cap->rkisp1, cap->config->mi.cb_base_ad_init, 780 cap->buf.dummy.dma_addr >> shift); 781 rkisp1_write(cap->rkisp1, cap->config->mi.cr_base_ad_init, 782 cap->buf.dummy.dma_addr >> shift); 783 } 784 785 /* Set plane offsets */ 786 rkisp1_write(cap->rkisp1, cap->config->mi.y_offs_cnt_init, 0); 787 rkisp1_write(cap->rkisp1, cap->config->mi.cb_offs_cnt_init, 0); 788 rkisp1_write(cap->rkisp1, cap->config->mi.cr_offs_cnt_init, 0); 789 } 790 791 /* 792 * This function is called when a frame end comes. The next frame 793 * is processing and we should set up buffer for next-next frame, 794 * otherwise it will overflow. 795 */ 796 static void rkisp1_handle_buffer(struct rkisp1_capture *cap) 797 { 798 struct rkisp1_isp *isp = &cap->rkisp1->isp; 799 struct rkisp1_buffer *curr_buf; 800 801 spin_lock(&cap->buf.lock); 802 curr_buf = cap->buf.curr; 803 804 if (curr_buf) { 805 curr_buf->vb.sequence = isp->frame_sequence; 806 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns(); 807 curr_buf->vb.field = V4L2_FIELD_NONE; 808 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 809 } else { 810 cap->rkisp1->debug.frame_drop[cap->id]++; 811 } 812 813 rkisp1_set_next_buf(cap); 814 spin_unlock(&cap->buf.lock); 815 } 816 817 irqreturn_t rkisp1_capture_isr(int irq, void *ctx) 818 { 819 struct device *dev = ctx; 820 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 821 unsigned int dev_count = rkisp1_path_count(rkisp1); 822 unsigned int i; 823 u32 status; 824 825 if (!rkisp1->irqs_enabled) 826 return IRQ_NONE; 827 828 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS); 829 if (!status) 830 return IRQ_NONE; 831 832 rkisp1_write(rkisp1, RKISP1_CIF_MI_ICR, status); 833 834 for (i = 0; i < dev_count; ++i) { 835 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 836 837 if (!(status & RKISP1_CIF_MI_FRAME(cap))) 838 continue; 839 if (!cap->is_stopping) { 840 rkisp1_handle_buffer(cap); 841 continue; 842 } 843 /* 844 * Make sure stream is actually stopped, whose state 845 * can be read from the shadow register, before 846 * wake_up() thread which would immediately free all 847 * frame buffers. stop() takes effect at the next 848 * frame end that sync the configurations to shadow 849 * regs. 850 */ 851 if (!cap->ops->is_stopped(cap)) { 852 cap->ops->stop(cap); 853 continue; 854 } 855 cap->is_stopping = false; 856 cap->is_streaming = false; 857 wake_up(&cap->done); 858 } 859 860 return IRQ_HANDLED; 861 } 862 863 /* ---------------------------------------------------------------------------- 864 * Vb2 operations 865 */ 866 867 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue, 868 unsigned int *num_buffers, 869 unsigned int *num_planes, 870 unsigned int sizes[], 871 struct device *alloc_devs[]) 872 { 873 struct rkisp1_capture *cap = queue->drv_priv; 874 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 875 unsigned int i; 876 877 if (*num_planes) { 878 if (*num_planes != pixm->num_planes) 879 return -EINVAL; 880 881 for (i = 0; i < pixm->num_planes; i++) 882 if (sizes[i] < pixm->plane_fmt[i].sizeimage) 883 return -EINVAL; 884 } else { 885 *num_planes = pixm->num_planes; 886 for (i = 0; i < pixm->num_planes; i++) 887 sizes[i] = pixm->plane_fmt[i].sizeimage; 888 } 889 890 return 0; 891 } 892 893 static int rkisp1_vb2_buf_init(struct vb2_buffer *vb) 894 { 895 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 896 struct rkisp1_buffer *ispbuf = 897 container_of(vbuf, struct rkisp1_buffer, vb); 898 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 899 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 900 unsigned int i; 901 902 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); 903 for (i = 0; i < pixm->num_planes; i++) 904 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); 905 906 /* Convert to non-MPLANE */ 907 if (pixm->num_planes == 1) { 908 ispbuf->buff_addr[RKISP1_PLANE_CB] = 909 ispbuf->buff_addr[RKISP1_PLANE_Y] + 910 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y); 911 ispbuf->buff_addr[RKISP1_PLANE_CR] = 912 ispbuf->buff_addr[RKISP1_PLANE_CB] + 913 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB); 914 } 915 916 /* 917 * uv swap can be supported for planar formats by switching 918 * the address of cb and cr 919 */ 920 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap) 921 swap(ispbuf->buff_addr[RKISP1_PLANE_CR], 922 ispbuf->buff_addr[RKISP1_PLANE_CB]); 923 return 0; 924 } 925 926 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb) 927 { 928 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 929 struct rkisp1_buffer *ispbuf = 930 container_of(vbuf, struct rkisp1_buffer, vb); 931 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 932 933 spin_lock_irq(&cap->buf.lock); 934 list_add_tail(&ispbuf->queue, &cap->buf.queue); 935 spin_unlock_irq(&cap->buf.lock); 936 } 937 938 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb) 939 { 940 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 941 unsigned int i; 942 943 for (i = 0; i < cap->pix.fmt.num_planes; i++) { 944 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage; 945 946 if (vb2_plane_size(vb, i) < size) { 947 dev_err(cap->rkisp1->dev, 948 "User buffer too small (%ld < %ld)\n", 949 vb2_plane_size(vb, i), size); 950 return -EINVAL; 951 } 952 vb2_set_plane_payload(vb, i, size); 953 } 954 955 return 0; 956 } 957 958 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap, 959 enum vb2_buffer_state state) 960 { 961 struct rkisp1_buffer *buf; 962 963 spin_lock_irq(&cap->buf.lock); 964 if (cap->buf.curr) { 965 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state); 966 cap->buf.curr = NULL; 967 } 968 if (cap->buf.next) { 969 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state); 970 cap->buf.next = NULL; 971 } 972 while (!list_empty(&cap->buf.queue)) { 973 buf = list_first_entry(&cap->buf.queue, 974 struct rkisp1_buffer, queue); 975 list_del(&buf->queue); 976 vb2_buffer_done(&buf->vb.vb2_buf, state); 977 } 978 spin_unlock_irq(&cap->buf.lock); 979 } 980 981 /* 982 * Most registers inside the rockchip ISP1 have shadow register since 983 * they must not be changed while processing a frame. 984 * Usually, each sub-module updates its shadow register after 985 * processing the last pixel of a frame. 986 */ 987 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) 988 { 989 struct rkisp1_device *rkisp1 = cap->rkisp1; 990 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; 991 bool has_self_path = rkisp1_has_feature(rkisp1, SELF_PATH); 992 993 cap->ops->set_data_path(cap); 994 cap->ops->config(cap); 995 996 /* Setup a buffer for the next frame */ 997 spin_lock_irq(&cap->buf.lock); 998 rkisp1_set_next_buf(cap); 999 cap->ops->enable(cap); 1000 1001 /* 1002 * It's safe to configure ACTIVE and SHADOW registers for the first 1003 * stream. While when the second is starting, do NOT force update 1004 * because it also updates the first one. 1005 * 1006 * The latter case would drop one more buffer(that is 2) since there's 1007 * no buffer in a shadow register when the second FE received. This's 1008 * also required because the second FE maybe corrupt especially when 1009 * run at 120fps. 1010 */ 1011 if (!has_self_path || !other->is_streaming) { 1012 u32 reg; 1013 1014 /* 1015 * Force cfg update. 1016 * 1017 * The ISP8000 (implementing the MAIN_STRIDE feature) as a 1018 * mp_output_format field in the CIF_MI_INIT register that must 1019 * be preserved. It can be read back, but it is not clear what 1020 * other register bits will return. Mask them out. 1021 * 1022 * On Rockchip platforms, the CIF_MI_INIT register is marked as 1023 * write-only and reads as zeros. We can skip reading it. 1024 */ 1025 if (rkisp1_has_feature(rkisp1, MAIN_STRIDE)) 1026 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_INIT) 1027 & RKISP1_CIF_MI_INIT_MP_OUTPUT_MASK; 1028 else 1029 reg = 0; 1030 1031 reg |= RKISP1_CIF_MI_INIT_SOFT_UPD; 1032 rkisp1_write(rkisp1, RKISP1_CIF_MI_INIT, reg); 1033 1034 rkisp1_set_next_buf(cap); 1035 } 1036 spin_unlock_irq(&cap->buf.lock); 1037 cap->is_streaming = true; 1038 } 1039 1040 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap) 1041 { 1042 int ret; 1043 1044 /* Stream should stop in interrupt. If it doesn't, stop it by force. */ 1045 cap->is_stopping = true; 1046 ret = wait_event_timeout(cap->done, 1047 !cap->is_streaming, 1048 msecs_to_jiffies(1000)); 1049 if (!ret) { 1050 cap->rkisp1->debug.stop_timeout[cap->id]++; 1051 cap->ops->stop(cap); 1052 cap->is_stopping = false; 1053 cap->is_streaming = false; 1054 } 1055 } 1056 1057 /* 1058 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline 1059 * 1060 * Call s_stream(false) in the reverse order from 1061 * rkisp1_pipeline_stream_enable() and disable the DMA engine. 1062 * Should be called before video_device_pipeline_stop() 1063 */ 1064 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap) 1065 __must_hold(&cap->rkisp1->stream_lock) 1066 { 1067 struct rkisp1_device *rkisp1 = cap->rkisp1; 1068 1069 rkisp1_cap_stream_disable(cap); 1070 1071 /* 1072 * If the other capture is streaming, isp and sensor nodes shouldn't 1073 * be disabled, skip them. 1074 */ 1075 if (rkisp1->pipe.start_count < 2) 1076 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 1077 1078 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 1079 false); 1080 } 1081 1082 /* 1083 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline 1084 * 1085 * Enable the DMA Engine and call s_stream(true) through the pipeline. 1086 * Should be called after video_device_pipeline_start() 1087 */ 1088 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap) 1089 __must_hold(&cap->rkisp1->stream_lock) 1090 { 1091 struct rkisp1_device *rkisp1 = cap->rkisp1; 1092 int ret; 1093 1094 rkisp1_cap_stream_enable(cap); 1095 1096 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, 1097 s_stream, true); 1098 if (ret) 1099 goto err_disable_cap; 1100 1101 /* 1102 * If the other capture is streaming, isp and sensor nodes are already 1103 * enabled, skip them. 1104 */ 1105 if (rkisp1->pipe.start_count > 1) 1106 return 0; 1107 1108 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true); 1109 if (ret) 1110 goto err_disable_rsz; 1111 1112 return 0; 1113 1114 err_disable_rsz: 1115 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 1116 false); 1117 err_disable_cap: 1118 rkisp1_cap_stream_disable(cap); 1119 1120 return ret; 1121 } 1122 1123 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue) 1124 { 1125 struct rkisp1_capture *cap = queue->drv_priv; 1126 struct rkisp1_vdev_node *node = &cap->vnode; 1127 struct rkisp1_device *rkisp1 = cap->rkisp1; 1128 int ret; 1129 1130 mutex_lock(&cap->rkisp1->stream_lock); 1131 1132 rkisp1_pipeline_stream_disable(cap); 1133 1134 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR); 1135 1136 v4l2_pipeline_pm_put(&node->vdev.entity); 1137 ret = pm_runtime_put(rkisp1->dev); 1138 if (ret < 0) 1139 dev_err(rkisp1->dev, "power down failed error:%d\n", ret); 1140 1141 rkisp1_dummy_buf_destroy(cap); 1142 1143 video_device_pipeline_stop(&node->vdev); 1144 1145 mutex_unlock(&cap->rkisp1->stream_lock); 1146 } 1147 1148 static int 1149 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) 1150 { 1151 struct rkisp1_capture *cap = queue->drv_priv; 1152 struct media_entity *entity = &cap->vnode.vdev.entity; 1153 int ret; 1154 1155 mutex_lock(&cap->rkisp1->stream_lock); 1156 1157 ret = video_device_pipeline_start(&cap->vnode.vdev, &cap->rkisp1->pipe); 1158 if (ret) { 1159 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret); 1160 goto err_ret_buffers; 1161 } 1162 1163 ret = rkisp1_dummy_buf_create(cap); 1164 if (ret) 1165 goto err_pipeline_stop; 1166 1167 ret = pm_runtime_resume_and_get(cap->rkisp1->dev); 1168 if (ret < 0) { 1169 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret); 1170 goto err_destroy_dummy; 1171 } 1172 ret = v4l2_pipeline_pm_get(entity); 1173 if (ret) { 1174 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret); 1175 goto err_pipe_pm_put; 1176 } 1177 1178 ret = rkisp1_pipeline_stream_enable(cap); 1179 if (ret) 1180 goto err_v4l2_pm_put; 1181 1182 mutex_unlock(&cap->rkisp1->stream_lock); 1183 1184 return 0; 1185 1186 err_v4l2_pm_put: 1187 v4l2_pipeline_pm_put(entity); 1188 err_pipe_pm_put: 1189 pm_runtime_put(cap->rkisp1->dev); 1190 err_destroy_dummy: 1191 rkisp1_dummy_buf_destroy(cap); 1192 err_pipeline_stop: 1193 video_device_pipeline_stop(&cap->vnode.vdev); 1194 err_ret_buffers: 1195 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED); 1196 mutex_unlock(&cap->rkisp1->stream_lock); 1197 1198 return ret; 1199 } 1200 1201 static const struct vb2_ops rkisp1_vb2_ops = { 1202 .queue_setup = rkisp1_vb2_queue_setup, 1203 .buf_init = rkisp1_vb2_buf_init, 1204 .buf_queue = rkisp1_vb2_buf_queue, 1205 .buf_prepare = rkisp1_vb2_buf_prepare, 1206 .wait_prepare = vb2_ops_wait_prepare, 1207 .wait_finish = vb2_ops_wait_finish, 1208 .stop_streaming = rkisp1_vb2_stop_streaming, 1209 .start_streaming = rkisp1_vb2_start_streaming, 1210 }; 1211 1212 /* ---------------------------------------------------------------------------- 1213 * IOCTLs operations 1214 */ 1215 1216 static const struct v4l2_format_info * 1217 rkisp1_fill_pixfmt(const struct rkisp1_capture *cap, 1218 struct v4l2_pix_format_mplane *pixm) 1219 { 1220 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0]; 1221 const struct v4l2_format_info *info; 1222 unsigned int i; 1223 u32 stride; 1224 1225 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt)); 1226 info = v4l2_format_info(pixm->pixelformat); 1227 pixm->num_planes = info->mem_planes; 1228 1229 /* 1230 * The SP supports custom strides, expressed as a number of pixels for 1231 * the Y plane, and so does the MP in ISP versions that have the 1232 * MAIN_STRIDE feature. Clamp the stride to a reasonable value to avoid 1233 * integer overflows when calculating the bytesperline and sizeimage 1234 * values. 1235 */ 1236 if (cap->id == RKISP1_SELFPATH || 1237 rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE)) 1238 stride = clamp(DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]), 1239 pixm->width, 65536U); 1240 else 1241 stride = pixm->width; 1242 1243 plane_y->bytesperline = stride * info->bpp[0]; 1244 plane_y->sizeimage = plane_y->bytesperline * pixm->height; 1245 1246 for (i = 1; i < info->comp_planes; i++) { 1247 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i]; 1248 1249 /* bytesperline for other components derive from Y component */ 1250 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) * 1251 info->bpp[i]; 1252 plane->sizeimage = plane->bytesperline * 1253 DIV_ROUND_UP(pixm->height, info->vdiv); 1254 } 1255 1256 /* 1257 * If pixfmt is packed, then plane_fmt[0] should contain the total size 1258 * considering all components. plane_fmt[i] for i > 0 should be ignored 1259 * by userspace as mem_planes == 1, but we are keeping information there 1260 * for convenience. 1261 */ 1262 if (info->mem_planes == 1) 1263 for (i = 1; i < info->comp_planes; i++) 1264 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage; 1265 1266 return info; 1267 } 1268 1269 static const struct rkisp1_capture_fmt_cfg * 1270 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt) 1271 { 1272 bool yc_swap_support = rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE); 1273 unsigned int i; 1274 1275 for (i = 0; i < cap->config->fmt_size; i++) { 1276 const struct rkisp1_capture_fmt_cfg *fmt = &cap->config->fmts[i]; 1277 1278 if (fmt->fourcc == pixelfmt && 1279 (!fmt->yc_swap || yc_swap_support)) 1280 return &cap->config->fmts[i]; 1281 } 1282 return NULL; 1283 } 1284 1285 static void rkisp1_try_fmt(const struct rkisp1_capture *cap, 1286 struct v4l2_pix_format_mplane *pixm, 1287 const struct rkisp1_capture_fmt_cfg **fmt_cfg, 1288 const struct v4l2_format_info **fmt_info) 1289 { 1290 const struct rkisp1_capture_config *config = cap->config; 1291 const struct rkisp1_capture_fmt_cfg *fmt; 1292 const struct v4l2_format_info *info; 1293 static const unsigned int max_widths[] = { 1294 RKISP1_RSZ_MP_SRC_MAX_WIDTH, RKISP1_RSZ_SP_SRC_MAX_WIDTH 1295 }; 1296 static const unsigned int max_heights[] = { 1297 RKISP1_RSZ_MP_SRC_MAX_HEIGHT, RKISP1_RSZ_SP_SRC_MAX_HEIGHT 1298 }; 1299 1300 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat); 1301 if (!fmt) { 1302 fmt = config->fmts; 1303 pixm->pixelformat = fmt->fourcc; 1304 } 1305 1306 pixm->width = clamp_t(u32, pixm->width, 1307 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]); 1308 pixm->height = clamp_t(u32, pixm->height, 1309 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]); 1310 1311 pixm->field = V4L2_FIELD_NONE; 1312 pixm->colorspace = V4L2_COLORSPACE_DEFAULT; 1313 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1314 pixm->quantization = V4L2_QUANTIZATION_DEFAULT; 1315 1316 info = rkisp1_fill_pixfmt(cap, pixm); 1317 1318 if (fmt_cfg) 1319 *fmt_cfg = fmt; 1320 if (fmt_info) 1321 *fmt_info = info; 1322 } 1323 1324 static void rkisp1_set_fmt(struct rkisp1_capture *cap, 1325 struct v4l2_pix_format_mplane *pixm) 1326 { 1327 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info); 1328 1329 cap->pix.fmt = *pixm; 1330 cap->stride = pixm->plane_fmt[0].bytesperline / cap->pix.info->bpp[0]; 1331 } 1332 1333 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh, 1334 struct v4l2_format *f) 1335 { 1336 struct rkisp1_capture *cap = video_drvdata(file); 1337 1338 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL); 1339 1340 return 0; 1341 } 1342 1343 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv, 1344 struct v4l2_fmtdesc *f) 1345 { 1346 struct rkisp1_capture *cap = video_drvdata(file); 1347 const struct rkisp1_capture_fmt_cfg *fmt = NULL; 1348 bool yc_swap_support = rkisp1_has_feature(cap->rkisp1, MAIN_STRIDE); 1349 unsigned int i, n = 0; 1350 1351 if (f->index >= cap->config->fmt_size) 1352 return -EINVAL; 1353 1354 if (!f->mbus_code && yc_swap_support) { 1355 fmt = &cap->config->fmts[f->index]; 1356 f->pixelformat = fmt->fourcc; 1357 return 0; 1358 } 1359 1360 for (i = 0; i < cap->config->fmt_size; i++) { 1361 fmt = &cap->config->fmts[i]; 1362 1363 if (f->mbus_code && fmt->mbus != f->mbus_code) 1364 continue; 1365 1366 if (!yc_swap_support && fmt->yc_swap) 1367 continue; 1368 1369 if (n++ == f->index) { 1370 f->pixelformat = fmt->fourcc; 1371 return 0; 1372 } 1373 } 1374 return -EINVAL; 1375 } 1376 1377 static int rkisp1_enum_framesizes(struct file *file, void *fh, 1378 struct v4l2_frmsizeenum *fsize) 1379 { 1380 static const unsigned int max_widths[] = { 1381 RKISP1_RSZ_MP_SRC_MAX_WIDTH, 1382 RKISP1_RSZ_SP_SRC_MAX_WIDTH, 1383 }; 1384 static const unsigned int max_heights[] = { 1385 RKISP1_RSZ_MP_SRC_MAX_HEIGHT, 1386 RKISP1_RSZ_SP_SRC_MAX_HEIGHT, 1387 }; 1388 struct rkisp1_capture *cap = video_drvdata(file); 1389 1390 if (fsize->index != 0) 1391 return -EINVAL; 1392 1393 fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; 1394 1395 fsize->stepwise.min_width = RKISP1_RSZ_SRC_MIN_WIDTH; 1396 fsize->stepwise.max_width = max_widths[cap->id]; 1397 fsize->stepwise.step_width = 2; 1398 1399 fsize->stepwise.min_height = RKISP1_RSZ_SRC_MIN_HEIGHT; 1400 fsize->stepwise.max_height = max_heights[cap->id]; 1401 fsize->stepwise.step_height = 2; 1402 1403 return 0; 1404 } 1405 1406 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file, 1407 void *priv, struct v4l2_format *f) 1408 { 1409 struct rkisp1_capture *cap = video_drvdata(file); 1410 struct rkisp1_vdev_node *node = 1411 rkisp1_vdev_to_node(&cap->vnode.vdev); 1412 1413 if (vb2_is_busy(&node->buf_queue)) 1414 return -EBUSY; 1415 1416 rkisp1_set_fmt(cap, &f->fmt.pix_mp); 1417 1418 return 0; 1419 } 1420 1421 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh, 1422 struct v4l2_format *f) 1423 { 1424 struct rkisp1_capture *cap = video_drvdata(file); 1425 1426 f->fmt.pix_mp = cap->pix.fmt; 1427 1428 return 0; 1429 } 1430 1431 static int 1432 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 1433 { 1434 strscpy(cap->driver, RKISP1_DRIVER_NAME, sizeof(cap->driver)); 1435 strscpy(cap->card, RKISP1_DRIVER_NAME, sizeof(cap->card)); 1436 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info)); 1437 1438 return 0; 1439 } 1440 1441 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = { 1442 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1443 .vidioc_querybuf = vb2_ioctl_querybuf, 1444 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1445 .vidioc_qbuf = vb2_ioctl_qbuf, 1446 .vidioc_expbuf = vb2_ioctl_expbuf, 1447 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1448 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1449 .vidioc_streamon = vb2_ioctl_streamon, 1450 .vidioc_streamoff = vb2_ioctl_streamoff, 1451 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane, 1452 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane, 1453 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane, 1454 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane, 1455 .vidioc_enum_framesizes = rkisp1_enum_framesizes, 1456 .vidioc_querycap = rkisp1_querycap, 1457 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1458 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1459 }; 1460 1461 static int rkisp1_capture_link_validate(struct media_link *link) 1462 { 1463 struct video_device *vdev = 1464 media_entity_to_video_device(link->sink->entity); 1465 struct v4l2_subdev *sd = 1466 media_entity_to_v4l2_subdev(link->source->entity); 1467 struct rkisp1_capture *cap = video_get_drvdata(vdev); 1468 const struct rkisp1_capture_fmt_cfg *fmt = 1469 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat); 1470 struct v4l2_subdev_format sd_fmt = { 1471 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1472 .pad = link->source->index, 1473 }; 1474 int ret; 1475 1476 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt); 1477 if (ret) 1478 return ret; 1479 1480 if (sd_fmt.format.height != cap->pix.fmt.height || 1481 sd_fmt.format.width != cap->pix.fmt.width || 1482 sd_fmt.format.code != fmt->mbus) { 1483 dev_dbg(cap->rkisp1->dev, 1484 "link '%s':%u -> '%s':%u not valid: 0x%04x/%ux%u != 0x%04x/%ux%u\n", 1485 link->source->entity->name, link->source->index, 1486 link->sink->entity->name, link->sink->index, 1487 sd_fmt.format.code, sd_fmt.format.width, 1488 sd_fmt.format.height, fmt->mbus, cap->pix.fmt.width, 1489 cap->pix.fmt.height); 1490 return -EPIPE; 1491 } 1492 1493 return 0; 1494 } 1495 1496 /* ---------------------------------------------------------------------------- 1497 * core functions 1498 */ 1499 1500 static const struct media_entity_operations rkisp1_media_ops = { 1501 .link_validate = rkisp1_capture_link_validate, 1502 }; 1503 1504 static const struct v4l2_file_operations rkisp1_fops = { 1505 .open = v4l2_fh_open, 1506 .release = vb2_fop_release, 1507 .unlocked_ioctl = video_ioctl2, 1508 .poll = vb2_fop_poll, 1509 .mmap = vb2_fop_mmap, 1510 }; 1511 1512 static void rkisp1_unregister_capture(struct rkisp1_capture *cap) 1513 { 1514 if (!video_is_registered(&cap->vnode.vdev)) 1515 return; 1516 1517 media_entity_cleanup(&cap->vnode.vdev.entity); 1518 vb2_video_unregister_device(&cap->vnode.vdev); 1519 mutex_destroy(&cap->vnode.vlock); 1520 } 1521 1522 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1) 1523 { 1524 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH]; 1525 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH]; 1526 1527 rkisp1_unregister_capture(mp); 1528 rkisp1_unregister_capture(sp); 1529 } 1530 1531 static int rkisp1_register_capture(struct rkisp1_capture *cap) 1532 { 1533 static const char * const dev_names[] = { 1534 RKISP1_MP_DEV_NAME, RKISP1_SP_DEV_NAME 1535 }; 1536 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev; 1537 struct video_device *vdev = &cap->vnode.vdev; 1538 struct rkisp1_vdev_node *node; 1539 struct vb2_queue *q; 1540 int ret; 1541 1542 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name)); 1543 node = rkisp1_vdev_to_node(vdev); 1544 mutex_init(&node->vlock); 1545 1546 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops; 1547 vdev->release = video_device_release_empty; 1548 vdev->fops = &rkisp1_fops; 1549 vdev->minor = -1; 1550 vdev->v4l2_dev = v4l2_dev; 1551 vdev->lock = &node->vlock; 1552 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1553 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; 1554 vdev->entity.ops = &rkisp1_media_ops; 1555 video_set_drvdata(vdev, cap); 1556 vdev->vfl_dir = VFL_DIR_RX; 1557 node->pad.flags = MEDIA_PAD_FL_SINK; 1558 1559 q = &node->buf_queue; 1560 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1561 q->io_modes = VB2_MMAP | VB2_DMABUF; 1562 q->drv_priv = cap; 1563 q->ops = &rkisp1_vb2_ops; 1564 q->mem_ops = &vb2_dma_contig_memops; 1565 q->buf_struct_size = sizeof(struct rkisp1_buffer); 1566 q->min_queued_buffers = RKISP1_MIN_BUFFERS_NEEDED; 1567 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1568 q->lock = &node->vlock; 1569 q->dev = cap->rkisp1->dev; 1570 ret = vb2_queue_init(q); 1571 if (ret) { 1572 dev_err(cap->rkisp1->dev, 1573 "vb2 queue init failed (err=%d)\n", ret); 1574 goto error; 1575 } 1576 1577 vdev->queue = q; 1578 1579 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); 1580 if (ret) 1581 goto error; 1582 1583 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1584 if (ret) { 1585 dev_err(cap->rkisp1->dev, 1586 "failed to register %s, ret=%d\n", vdev->name, ret); 1587 goto error; 1588 } 1589 1590 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, 1591 vdev->num); 1592 1593 return 0; 1594 1595 error: 1596 media_entity_cleanup(&vdev->entity); 1597 mutex_destroy(&node->vlock); 1598 return ret; 1599 } 1600 1601 static void 1602 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id) 1603 { 1604 struct rkisp1_capture *cap = &rkisp1->capture_devs[id]; 1605 struct v4l2_pix_format_mplane pixm; 1606 1607 memset(cap, 0, sizeof(*cap)); 1608 cap->id = id; 1609 cap->rkisp1 = rkisp1; 1610 1611 INIT_LIST_HEAD(&cap->buf.queue); 1612 init_waitqueue_head(&cap->done); 1613 spin_lock_init(&cap->buf.lock); 1614 if (cap->id == RKISP1_SELFPATH) { 1615 cap->ops = &rkisp1_capture_ops_sp; 1616 cap->config = &rkisp1_capture_config_sp; 1617 } else { 1618 cap->ops = &rkisp1_capture_ops_mp; 1619 cap->config = &rkisp1_capture_config_mp; 1620 } 1621 1622 cap->is_streaming = false; 1623 1624 memset(&pixm, 0, sizeof(pixm)); 1625 pixm.pixelformat = V4L2_PIX_FMT_YUYV; 1626 pixm.width = RKISP1_DEFAULT_WIDTH; 1627 pixm.height = RKISP1_DEFAULT_HEIGHT; 1628 rkisp1_set_fmt(cap, &pixm); 1629 } 1630 1631 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1) 1632 { 1633 unsigned int dev_count = rkisp1_path_count(rkisp1); 1634 unsigned int i; 1635 int ret; 1636 1637 for (i = 0; i < dev_count; i++) { 1638 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 1639 1640 rkisp1_capture_init(rkisp1, i); 1641 1642 ret = rkisp1_register_capture(cap); 1643 if (ret) { 1644 rkisp1_capture_devs_unregister(rkisp1); 1645 return ret; 1646 } 1647 } 1648 1649 return 0; 1650 1651 } 1652