xref: /linux/drivers/media/platform/rockchip/rga/rga.h (revision a3a02a52bcfcbcc4a637d4b68bf1bc391c9fad02)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
4  * Author: Jacob Chen <jacob-chen@iotwrt.com>
5  */
6 #ifndef __RGA_H__
7 #define __RGA_H__
8 
9 #include <linux/platform_device.h>
10 #include <media/videobuf2-v4l2.h>
11 #include <media/v4l2-ctrls.h>
12 #include <media/v4l2-device.h>
13 
14 #define RGA_NAME "rockchip-rga"
15 
16 struct rga_fmt {
17 	u32 fourcc;
18 	int depth;
19 	u8 uv_factor;
20 	u8 y_div;
21 	u8 x_div;
22 	u8 color_swap;
23 	u8 hw_format;
24 };
25 
26 struct rga_frame {
27 	/* Original dimensions */
28 	u32 width;
29 	u32 height;
30 	u32 colorspace;
31 
32 	/* Crop */
33 	struct v4l2_rect crop;
34 
35 	/* Image format */
36 	struct rga_fmt *fmt;
37 	struct v4l2_pix_format_mplane pix;
38 
39 	/* Variables that can calculated once and reused */
40 	u32 stride;
41 	u32 size;
42 };
43 
44 struct rga_dma_desc {
45 	u32 addr;
46 };
47 
48 struct rockchip_rga_version {
49 	u32 major;
50 	u32 minor;
51 };
52 
53 struct rga_ctx {
54 	struct v4l2_fh fh;
55 	struct rockchip_rga *rga;
56 	struct rga_frame in;
57 	struct rga_frame out;
58 	struct v4l2_ctrl_handler ctrl_handler;
59 
60 	int osequence;
61 	int csequence;
62 
63 	/* Control values */
64 	u32 op;
65 	u32 hflip;
66 	u32 vflip;
67 	u32 rotate;
68 	u32 fill_color;
69 };
70 
71 struct rockchip_rga {
72 	struct v4l2_device v4l2_dev;
73 	struct v4l2_m2m_dev *m2m_dev;
74 	struct video_device *vfd;
75 
76 	struct device *dev;
77 	struct regmap *grf;
78 	void __iomem *regs;
79 	struct clk *sclk;
80 	struct clk *aclk;
81 	struct clk *hclk;
82 	struct rockchip_rga_version version;
83 
84 	/* vfd lock */
85 	struct mutex mutex;
86 	/* ctrl parm lock */
87 	spinlock_t ctrl_lock;
88 
89 	struct rga_ctx *curr;
90 	dma_addr_t cmdbuf_phy;
91 	void *cmdbuf_virt;
92 };
93 
94 struct rga_addr_offset {
95 	unsigned int y_off;
96 	unsigned int u_off;
97 	unsigned int v_off;
98 };
99 
100 struct rga_vb_buffer {
101 	struct vb2_v4l2_buffer vb_buf;
102 	struct list_head queue;
103 
104 	/* RGA MMU mapping for this buffer */
105 	struct rga_dma_desc *dma_desc;
106 	dma_addr_t dma_desc_pa;
107 	size_t n_desc;
108 
109 	/* Plane offsets of this buffer into the mapping */
110 	struct rga_addr_offset offset;
111 };
112 
113 static inline struct rga_vb_buffer *vb_to_rga(struct vb2_v4l2_buffer *vb)
114 {
115 	return container_of(vb, struct rga_vb_buffer, vb_buf);
116 }
117 
118 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);
119 
120 /* RGA Buffers Manage */
121 extern const struct vb2_ops rga_qops;
122 
123 /* RGA Hardware */
124 static inline void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)
125 {
126 	writel(value, rga->regs + reg);
127 };
128 
129 static inline u32 rga_read(struct rockchip_rga *rga, u32 reg)
130 {
131 	return readl(rga->regs + reg);
132 };
133 
134 static inline void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
135 {
136 	u32 temp = rga_read(rga, reg) & ~(mask);
137 
138 	temp |= val & mask;
139 	rga_write(rga, reg, temp);
140 };
141 
142 void rga_hw_start(struct rockchip_rga *rga,
143 		  struct rga_vb_buffer *src, struct rga_vb_buffer *dst);
144 
145 #endif
146